Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_keymgr_dpe_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1684900	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

236373

1

T1

2904

T2

3057

T3

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1783748	1			T1	184741		T2	33132		T3	1
values[0x0]	68481	1			T1	721		T2	737		T3	9
values[0x1]	69044	1			T1	680		T2	823		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1138326	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

782947

1

T1

63742

T2

13431

T3

4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5010	1			T2	121		T4	51		T5	3
valid_sources[0x01]	4922	1			T2	149		T4	21		T16	1
valid_sources[0x02]	4852	1			T2	197		T4	48		T16	1
valid_sources[0x03]	4271	1			T2	153		T4	17		T5	16
valid_sources[0x04]	4554	1			T2	140		T4	23		T5	8
valid_sources[0x05]	4687	1			T2	62		T4	38		T5	1
valid_sources[0x06]	4872	1			T2	180		T4	42		T10	18
valid_sources[0x07]	4571	1			T2	264		T4	2		T5	2
valid_sources[0x08]	4680	1			T2	179		T4	54		T15	1
valid_sources[0x09]	4936	1			T2	149		T4	19		T5	26
valid_sources[0x0a]	4536	1			T2	126		T4	57		T5	14
valid_sources[0x0b]	4816	1			T2	115		T4	17		T5	20
valid_sources[0x0c]	5077	1			T2	158		T4	88		T5	15
valid_sources[0x0d]	4655	1			T2	141		T4	7		T10	19
valid_sources[0x0e]	4833	1			T2	157		T4	56		T5	13
valid_sources[0x0f]	4273	1			T2	206		T4	46		T5	14
valid_sources[0x10]	4834	1			T2	115		T4	23		T5	11
valid_sources[0x11]	4778	1			T2	83		T4	29		T5	17
valid_sources[0x12]	4867	1			T2	119		T4	22		T10	23
valid_sources[0x13]	4862	1			T2	133		T4	22		T5	15
valid_sources[0x14]	4529	1			T2	167		T4	5		T5	7
valid_sources[0x15]	4771	1			T2	225		T4	3		T5	6
valid_sources[0x16]	4815	1			T2	166		T4	16		T10	45
valid_sources[0x17]	4665	1			T2	94		T4	32		T5	9
valid_sources[0x18]	24665	1			T2	193		T4	28		T5	26
valid_sources[0x19]	4820	1			T2	148		T4	54		T5	19
valid_sources[0x1a]	4929	1			T2	185		T4	31		T5	6
valid_sources[0x1b]	4625	1			T2	100		T4	9		T5	14
valid_sources[0x1c]	4655	1			T2	131		T4	21		T5	4
valid_sources[0x1d]	4819	1			T2	97		T4	2		T5	1
valid_sources[0x1e]	4755	1			T2	151		T4	34		T5	5
valid_sources[0x1f]	4435	1			T2	72		T4	40		T5	4
valid_sources[0x20]	4868	1			T2	236		T4	36		T5	7
valid_sources[0x21]	4733	1			T2	57		T4	10		T10	17
valid_sources[0x22]	4827	1			T2	41		T4	26		T10	28
valid_sources[0x23]	4585	1			T2	160		T4	78		T5	37
valid_sources[0x24]	6357	1			T2	80		T4	72		T5	1
valid_sources[0x25]	4675	1			T2	172		T4	39		T5	3
valid_sources[0x26]	105435	1			T2	76		T4	18		T5	14
valid_sources[0x27]	4696	1			T2	63		T4	15		T5	19
valid_sources[0x28]	4537	1			T2	185		T4	7		T5	11
valid_sources[0x29]	4802	1			T2	39		T4	21		T5	2
valid_sources[0x2a]	9117	1			T2	171		T4	11		T8	1752
valid_sources[0x2b]	5150	1			T2	126		T4	88		T10	24
valid_sources[0x2c]	4994	1			T2	144		T4	16		T5	25
valid_sources[0x2d]	4937	1			T2	310		T4	58		T10	20
valid_sources[0x2e]	11565	1			T2	95		T4	15		T5	15
valid_sources[0x2f]	4665	1			T2	102		T4	31		T5	8
valid_sources[0x30]	5322	1			T2	114		T4	4		T5	14
valid_sources[0x31]	4328	1			T2	132		T4	12		T5	22
valid_sources[0x32]	4828	1			T2	18		T4	31		T5	8
valid_sources[0x33]	4905	1			T2	116		T4	57		T5	9
valid_sources[0x34]	4374	1			T2	119		T4	49		T10	19
valid_sources[0x35]	6417	1			T2	154		T4	46		T5	2
valid_sources[0x36]	4814	1			T2	95		T4	12		T10	31
valid_sources[0x37]	4697	1			T2	97		T4	40		T5	1
valid_sources[0x38]	4806	1			T2	210		T4	19		T5	6
valid_sources[0x39]	8258	1			T2	61		T4	32		T5	5
valid_sources[0x3a]	4582	1			T2	49		T4	45		T16	6
valid_sources[0x3b]	4330	1			T2	74		T4	35		T15	4
valid_sources[0x3c]	4901	1			T2	112		T4	59		T5	25
valid_sources[0x3d]	4543	1			T2	251		T5	4		T10	24
valid_sources[0x3e]	11438	1			T2	131		T4	29		T5	9
valid_sources[0x3f]	4754	1			T2	206		T4	25		T10	23
valid_sources[0x40]	4657	1			T2	27		T4	34		T5	28
valid_sources[0x41]	4870	1			T2	73		T4	10		T5	7
valid_sources[0x42]	4587	1			T2	104		T4	47		T5	14
valid_sources[0x43]	4746	1			T2	172		T4	18		T5	7
valid_sources[0x44]	4909	1			T2	121		T4	46		T5	1
valid_sources[0x45]	5330	1			T2	84		T4	11		T5	7
valid_sources[0x46]	4942	1			T2	134		T4	1		T5	16
valid_sources[0x47]	4696	1			T2	35		T4	53		T5	9
valid_sources[0x48]	4261	1			T2	98		T4	8		T5	13
valid_sources[0x49]	4756	1			T2	168		T4	24		T5	5
valid_sources[0x4a]	4661	1			T2	100		T4	39		T5	4
valid_sources[0x4b]	4896	1			T2	165		T4	17		T5	10
valid_sources[0x4c]	15091	1			T2	72		T4	93		T5	1
valid_sources[0x4d]	4303	1			T2	76		T4	24		T10	18
valid_sources[0x4e]	4720	1			T2	141		T4	26		T5	1
valid_sources[0x4f]	4555	1			T2	122		T4	25		T5	16
valid_sources[0x50]	4735	1			T2	206		T4	36		T5	4
valid_sources[0x51]	4852	1			T2	281		T4	4		T5	21
valid_sources[0x52]	4927	1			T2	95		T4	19		T5	38
valid_sources[0x53]	5119	1			T2	153		T4	11		T10	27
valid_sources[0x54]	4579	1			T2	200		T4	62		T5	31
valid_sources[0x55]	5160	1			T2	80		T4	71		T5	21
valid_sources[0x56]	4612	1			T2	136		T4	23		T10	25
valid_sources[0x57]	4733	1			T2	155		T4	30		T5	1
valid_sources[0x58]	4863	1			T2	99		T4	50		T5	5
valid_sources[0x59]	4945	1			T2	33		T4	10		T5	1
valid_sources[0x5a]	10902	1			T2	104		T4	18		T9	6338
valid_sources[0x5b]	4986	1			T2	283		T4	9		T5	54
valid_sources[0x5c]	12290	1			T2	152		T4	107		T5	7
valid_sources[0x5d]	4842	1			T2	203		T4	7		T5	6
valid_sources[0x5e]	5078	1			T2	225		T4	26		T5	30
valid_sources[0x5f]	8669	1			T2	137		T4	81		T5	8
valid_sources[0x60]	4857	1			T2	114		T4	34		T15	2
valid_sources[0x61]	5000	1			T2	122		T4	16		T10	26
valid_sources[0x62]	4632	1			T2	69		T4	13		T5	15
valid_sources[0x63]	4506	1			T2	84		T4	11		T5	4
valid_sources[0x64]	4594	1			T2	62		T4	26		T10	34
valid_sources[0x65]	4969	1			T2	113		T4	7		T5	7
valid_sources[0x66]	5200	1			T2	271		T4	24		T5	3
valid_sources[0x67]	4910	1			T2	135		T4	45		T5	5
valid_sources[0x68]	5105	1			T2	86		T4	16		T5	15
valid_sources[0x69]	5718	1			T2	34		T4	9		T8	260
valid_sources[0x6a]	4500	1			T2	109		T4	29		T5	40
valid_sources[0x6b]	4486	1			T2	96		T5	10		T10	8
valid_sources[0x6c]	4524	1			T2	90		T4	20		T5	15
valid_sources[0x6d]	4891	1			T2	144		T4	57		T5	40
valid_sources[0x6e]	4305	1			T2	71		T4	22		T5	13
valid_sources[0x6f]	5193	1			T2	121		T4	15		T5	32
valid_sources[0x70]	4955	1			T2	101		T4	37		T5	30
valid_sources[0x71]	5091	1			T2	126		T4	26		T5	17
valid_sources[0x72]	4675	1			T2	75		T4	42		T5	12
valid_sources[0x73]	4958	1			T2	213		T4	56		T5	5
valid_sources[0x74]	4701	1			T2	209		T4	64		T5	5
valid_sources[0x75]	4442	1			T2	135		T4	25		T5	23
valid_sources[0x76]	4732	1			T2	14		T4	9		T5	4
valid_sources[0x77]	4758	1			T2	265		T4	18		T5	6
valid_sources[0x78]	4748	1			T2	72		T4	22		T5	3
valid_sources[0x79]	4535	1			T2	130		T4	11		T10	18
valid_sources[0x7a]	5017	1			T2	202		T4	25		T15	2
valid_sources[0x7b]	4626	1			T2	178		T4	32		T5	9
valid_sources[0x7c]	4661	1			T2	89		T4	39		T5	2
valid_sources[0x7d]	4991	1			T2	149		T4	61		T5	9
valid_sources[0x7e]	5258	1			T2	120		T4	59		T5	9
valid_sources[0x7f]	4645	1			T2	92		T4	47		T5	8
valid_sources[0x80]	5103	1			T2	65		T4	16		T5	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

131451

1

T1

1942

T2

1976

T3

1

values[0x0]

all_enables

biggest_size

56014

1

T1

553

T2

570

T3

1

values[0x1]

all_enables

biggest_size

48908

1

T1

409

T2

511

T3

1