Unified Coverage Report :: Module :: keymgr_dpe_csr_assert_fpv

Module : keymgr_dpe_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_keymgr_dpe_csr_assert_0/keymgr_dpe_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.keymgr_dpe_csr_assert	100.00						100.00

---

Module Instance : tb.dut.keymgr_dpe_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.32	100.00	79.89	53.88		97.83	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : keymgr_dpe_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	22	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	10872400	8693	0	0
intr_enable_rd_A	10872400	1627	0	0
key_version_rd_A	10872400	1423	0	0
reseed_interval_regwen_rd_A	10872400	629	0	0
salt_0_rd_A	10872400	1445	0	0
salt_1_rd_A	10872400	1253	0	0
salt_2_rd_A	10872400	1335	0	0
salt_3_rd_A	10872400	1352	0	0
salt_4_rd_A	10872400	1401	0	0
salt_5_rd_A	10872400	1414	0	0
salt_6_rd_A	10872400	1330	0	0
salt_7_rd_A	10872400	1437	0	0
sideload_clear_rd_A	10872400	1511	0	0
slot_policy_rd_A	10872400	2123	0	0
sw_binding_0_rd_A	10872400	1419	0	0
sw_binding_1_rd_A	10872400	1468	0	0
sw_binding_2_rd_A	10872400	1397	0	0
sw_binding_3_rd_A	10872400	1239	0	0
sw_binding_4_rd_A	10872400	1460	0	0
sw_binding_5_rd_A	10872400	1295	0	0
sw_binding_6_rd_A	10872400	1365	0	0
sw_binding_7_rd_A	10872400	1413	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10872400	8693	0	0
T18	11519	2	0	0
T19	2113	7	0	0
T20	9736	3	0	0
T29	10848	365	0	0
T30	15800	7	0	0
T31	3157	152	0	0
T32	0	125	0	0
T42	0	2	0	0
T43	0	2	0	0
T53	0	2	0	0
T57	20502	0	0	0
T64	791	0	0	0
T65	28701	0	0	0
T66	2218	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10872400	1627	0	0
T18	11519	47	0	0
T19	2113	6	0	0
T29	10848	3	0	0
T35	5054	20	0	0
T38	1238	23	0	0
T43	11011	0	0	0
T55	12936	96	0	0
T57	20502	0	0	0
T58	0	112	0	0
T66	2218	10	0	0
T77	0	7	0	0
T85	1331	22	0	0

key_version_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10872400	1423	0	0
T18	11519	29	0	0
T19	2113	4	0	0
T29	10848	14	0	0
T35	5054	34	0	0
T43	11011	0	0	0
T55	12936	84	0	0
T57	20502	0	0	0
T58	31360	96	0	0
T60	5308	0	0	0
T66	2218	8	0	0
T78	0	5	0	0
T79	0	10	0	0
T86	0	6	0	0

reseed_interval_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10872400	629	0	0
T19	2113	13	0	0
T29	10848	12	0	0
T32	2564	0	0	0
T35	5054	13	0	0
T53	8699	0	0	0
T55	12936	15	0	0
T58	31360	33	0	0
T59	4220	0	0	0
T60	5308	0	0	0
T63	0	33	0	0
T77	1244	0	0	0
T86	0	9	0	0
T87	0	84	0	0
T88	0	19	0	0
T89	0	7	0	0

salt_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10872400	1445	0	0
T18	11519	51	0	0
T19	2113	11	0	0
T29	10848	5	0	0
T35	5054	3	0	0
T43	11011	0	0	0
T55	12936	102	0	0
T57	20502	0	0	0
T58	31360	109	0	0
T60	5308	0	0	0
T66	2218	11	0	0
T79	0	9	0	0
T86	0	3	0	0
T87	0	117	0	0

salt_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10872400	1253	0	0
T18	11519	47	0	0
T19	2113	4	0	0
T29	10848	13	0	0
T35	5054	19	0	0
T43	11011	0	0	0
T55	12936	74	0	0
T57	20502	0	0	0
T58	31360	99	0	0
T60	5308	0	0	0
T66	2218	10	0	0
T79	0	10	0	0
T86	0	2	0	0
T87	0	76	0	0

salt_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10872400	1335	0	0
T18	11519	53	0	0
T19	2113	3	0	0
T29	10848	13	0	0
T35	5054	10	0	0
T43	11011	0	0	0
T55	12936	92	0	0
T57	20502	0	0	0
T58	31360	82	0	0
T60	5308	0	0	0
T66	2218	11	0	0
T78	0	7	0	0
T79	0	2	0	0
T86	0	3	0	0

salt_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10872400	1352	0	0
T18	11519	40	0	0
T19	2113	4	0	0
T29	10848	13	0	0
T35	5054	11	0	0
T43	11011	0	0	0
T55	12936	59	0	0
T57	20502	0	0	0
T58	31360	74	0	0
T60	5308	0	0	0
T66	2218	8	0	0
T78	0	6	0	0
T79	0	8	0	0
T86	0	3	0	0

salt_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10872400	1401	0	0
T18	11519	47	0	0
T19	2113	5	0	0
T29	10848	2	0	0
T35	5054	31	0	0
T43	11011	0	0	0
T55	12936	85	0	0
T57	20502	0	0	0
T58	31360	97	0	0
T60	5308	0	0	0
T66	2218	6	0	0
T79	0	6	0	0
T86	0	5	0	0
T87	0	87	0	0

salt_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10872400	1414	0	0
T18	11519	32	0	0
T19	2113	1	0	0
T29	10848	7	0	0
T35	5054	35	0	0
T43	11011	0	0	0
T55	12936	93	0	0
T57	20502	0	0	0
T58	31360	75	0	0
T60	5308	0	0	0
T66	2218	4	0	0
T79	0	6	0	0
T86	0	9	0	0
T87	0	57	0	0

salt_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10872400	1330	0	0
T18	11519	39	0	0
T19	2113	2	0	0
T29	10848	16	0	0
T35	5054	34	0	0
T43	11011	0	0	0
T55	12936	75	0	0
T57	20502	0	0	0
T58	31360	96	0	0
T60	5308	0	0	0
T66	2218	3	0	0
T79	0	8	0	0
T86	0	4	0	0
T87	0	124	0	0

salt_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10872400	1437	0	0
T18	11519	40	0	0
T19	2113	2	0	0
T29	10848	8	0	0
T32	2564	0	0	0
T35	5054	40	0	0
T53	8699	0	0	0
T55	12936	100	0	0
T58	31360	79	0	0
T60	5308	0	0	0
T77	1244	0	0	0
T78	0	4	0	0
T79	0	10	0	0
T86	0	5	0	0
T87	0	82	0	0

sideload_clear_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10872400	1511	0	0
T18	11519	45	0	0
T19	2113	6	0	0
T29	10848	24	0	0
T35	5054	16	0	0
T43	11011	0	0	0
T55	12936	69	0	0
T57	20502	0	0	0
T58	31360	92	0	0
T60	5308	0	0	0
T66	2218	3	0	0
T78	0	4	0	0
T79	0	15	0	0
T86	0	3	0	0

slot_policy_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10872400	2123	0	0
T18	11519	77	0	0
T19	2113	1	0	0
T29	10848	12	0	0
T35	5054	4	0	0
T43	11011	0	0	0
T55	12936	177	0	0
T57	20502	0	0	0
T58	31360	189	0	0
T60	5308	0	0	0
T66	2218	16	0	0
T78	0	4	0	0
T79	0	12	0	0
T86	0	8	0	0

sw_binding_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10872400	1419	0	0
T18	11519	54	0	0
T19	2113	2	0	0
T32	2564	0	0	0
T35	5054	22	0	0
T43	11011	0	0	0
T55	12936	66	0	0
T57	20502	0	0	0
T58	31360	73	0	0
T60	5308	0	0	0
T66	2218	13	0	0
T78	0	7	0	0
T79	0	6	0	0
T86	0	1	0	0
T87	0	115	0	0

sw_binding_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10872400	1468	0	0
T18	11519	39	0	0
T19	2113	6	0	0
T29	10848	9	0	0
T35	5054	33	0	0
T43	11011	0	0	0
T55	12936	85	0	0
T57	20502	0	0	0
T58	31360	114	0	0
T60	5308	0	0	0
T66	2218	11	0	0
T78	0	4	0	0
T79	0	5	0	0
T86	0	7	0	0

sw_binding_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10872400	1397	0	0
T18	11519	33	0	0
T19	2113	6	0	0
T32	2564	0	0	0
T35	5054	20	0	0
T43	11011	0	0	0
T55	12936	102	0	0
T57	20502	0	0	0
T58	31360	97	0	0
T60	5308	0	0	0
T66	2218	4	0	0
T78	0	3	0	0
T79	0	6	0	0
T86	0	7	0	0
T87	0	95	0	0

sw_binding_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10872400	1239	0	0
T18	11519	12	0	0
T19	2113	4	0	0
T29	10848	15	0	0
T35	5054	6	0	0
T43	11011	0	0	0
T55	12936	68	0	0
T57	20502	0	0	0
T58	31360	83	0	0
T60	5308	0	0	0
T66	2218	9	0	0
T79	0	11	0	0
T86	0	4	0	0
T87	0	78	0	0

sw_binding_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10872400	1460	0	0
T18	11519	42	0	0
T29	10848	6	0	0
T32	2564	0	0	0
T35	5054	29	0	0
T43	11011	0	0	0
T55	12936	81	0	0
T57	20502	0	0	0
T58	31360	91	0	0
T60	5308	0	0	0
T66	2218	12	0	0
T78	0	9	0	0
T79	0	9	0	0
T86	0	9	0	0
T87	0	101	0	0

sw_binding_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10872400	1295	0	0
T18	11519	30	0	0
T19	2113	7	0	0
T29	10848	15	0	0
T35	5054	8	0	0
T43	11011	0	0	0
T55	12936	78	0	0
T57	20502	0	0	0
T58	31360	116	0	0
T60	5308	0	0	0
T66	2218	6	0	0
T79	0	7	0	0
T86	0	5	0	0
T87	0	74	0	0

sw_binding_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10872400	1365	0	0
T18	11519	34	0	0
T19	2113	4	0	0
T29	10848	5	0	0
T35	5054	11	0	0
T43	11011	0	0	0
T55	12936	82	0	0
T57	20502	0	0	0
T58	31360	102	0	0
T60	5308	0	0	0
T66	2218	9	0	0
T78	0	4	0	0
T79	0	4	0	0
T86	0	3	0	0

sw_binding_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10872400	1413	0	0
T18	11519	27	0	0
T19	2113	6	0	0
T29	10848	5	0	0
T35	5054	60	0	0
T43	11011	0	0	0
T55	12936	78	0	0
T57	20502	0	0	0
T58	31360	85	0	0
T60	5308	0	0	0
T66	2218	9	0	0
T78	0	6	0	0
T79	0	7	0	0
T86	0	3	0	0