ADC_CTRL Simulation Results

Wednesday May 17 2023 07:05:42 UTC

GitHub Revision: `3df77bec1`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2320738200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.790s	6.021ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.890s	1.253ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.870s	552.934us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	2.394m	51.957ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.900s	686.249us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.860s	515.727us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.870s	552.934us	20	20	100.00
		adc_ctrl_csr_aliasing	3.900s	686.249us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.468m	493.161ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.650m	496.713ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.012m	495.482ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.311m	489.136ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	19.643m	484.051ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	20.226m	496.031ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	19.921m	495.638ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	17.237m	493.674ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.180s	5.350ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.714m	43.560ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.530m	133.067ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	23.405m	649.407ms	45	50	90.00
V2	alert_test	adc_ctrl_alert_test	1.790s	509.857us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.920s	495.540us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.570s	546.317us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.570s	546.317us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.890s	1.253ms	5	5	100.00
		adc_ctrl_csr_rw	1.870s	552.934us	20	20	100.00
		adc_ctrl_csr_aliasing	3.900s	686.249us	5	5	100.00
		adc_ctrl_same_csr_outstanding	22.580s	4.721ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.890s	1.253ms	5	5	100.00
		adc_ctrl_csr_rw	1.870s	552.934us	20	20	100.00
		adc_ctrl_csr_aliasing	3.900s	686.249us	5	5	100.00
		adc_ctrl_same_csr_outstanding	22.580s	4.721ms	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	tl_intg_err	adc_ctrl_sec_cm	9.270s	8.082ms	5	5	100.00
		adc_ctrl_tl_intg_err	24.540s	9.566ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	24.540s	9.566ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	10.527m	344.246ms	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			892	920	96.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.52	99.01	95.70	100.00	100.00	98.18	98.64	91.12

Failure Buckets

Offending '(wakeup_time == cfg_wakeup_time)' has 21 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 21 failures.
  - 0.adc_ctrl_stress_all_with_rand_reset.2424491254
    Line 419, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(wakeup_time == cfg_wakeup_time)'
  UVM_ERROR @ 369969743979 ps: (tb.sv:256) [ASSERT FAILED] WakeupTime_A
  UVM_INFO @ 369969743979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 3.adc_ctrl_stress_all_with_rand_reset.2746630072
    Line 367, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(wakeup_time == cfg_wakeup_time)'
  UVM_ERROR @ 15066665215 ps: (tb.sv:256) [ASSERT FAILED] WakeupTime_A
  UVM_INFO @ 15066665215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 19 more failures.

UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 6 failures:

Test adc_ctrl_stress_all has 5 failures.

11.adc_ctrl_stress_all.3078729772
Line 501, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/11.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 399222115756 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 399222115756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.adc_ctrl_stress_all.3242333216
Line 518, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/18.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 404777392796 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 404777392796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

19.adc_ctrl_stress_all_with_rand_reset.844679210
Line 474, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/19.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 475803006174 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 475803006174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(np_sample_cnt_q == '0)' has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 16.adc_ctrl_stress_all_with_rand_reset.1091204723
    Line 372, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/16.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(np_sample_cnt_q == '0)'
  UVM_ERROR @ 159356028283 ps: (adc_ctrl_fsm.sv:376) [ASSERT FAILED] NpCntClrPwrDn_A
  UVM_INFO @ 159356028283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```