ADC_CTRL Simulation Results

Wednesday December 27 2023 20:02:24 UTC

GitHub Revision: 0c759b93ab

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85416116840666724748485424200434981761468351851988553961117902923833034512693

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.550s	5.926ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.560s	1.186ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.850s	417.282us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.382m	16.470ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.800s	1.312ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.980s	517.939us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.850s	417.282us	20	20	100.00
		adc_ctrl_csr_aliasing	5.800s	1.312ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.538m	494.495ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.414m	495.429ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.305m	490.845ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.858m	507.972ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	19.734m	496.931ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	20.425m	492.063ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	19.755m	488.541ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	19.273m	496.971ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	14.100s	5.476ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.866m	47.321ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.378m	137.849ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	21.335m	418.719ms	47	50	94.00
V2	alert_test	adc_ctrl_alert_test	1.870s	505.482us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.870s	524.602us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.470s	656.666us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.470s	656.666us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.560s	1.186ms	5	5	100.00
		adc_ctrl_csr_rw	1.850s	417.282us	20	20	100.00
		adc_ctrl_csr_aliasing	5.800s	1.312ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	15.660s	4.506ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.560s	1.186ms	5	5	100.00
		adc_ctrl_csr_rw	1.850s	417.282us	20	20	100.00
		adc_ctrl_csr_aliasing	5.800s	1.312ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	15.660s	4.506ms	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	tl_intg_err	adc_ctrl_sec_cm	9.840s	4.027ms	5	5	100.00
		adc_ctrl_tl_intg_err	22.610s	8.656ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	22.610s	8.656ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	13.484m	474.690ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			916	920	99.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.46	98.98	95.70	100.00	100.00	98.18	98.64	90.72

Failure Buckets

• UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 3 failures:
  • Test adc_ctrl_stress_all has 3 failures.

    • 21.adc_ctrl_stress_all.99063884049657991853589194669217404064189906927458115861625675087743239130751
      Line 360, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/21.adc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 322744342913 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
        UVM_INFO @ 322744342913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 33.adc_ctrl_stress_all.36717234654818016437904920346767266800186816645879350324784539610789667770547
      Line 370, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/33.adc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 330217191388 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
        UVM_INFO @ 330217191388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (adc_ctrl_scoreboard.sv:115) [scoreboard] Check failed m_interrupt == (m_expected_intr_state & intr_en) (* [*] vs * [*]) has 1 failures:
  • Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 18.adc_ctrl_stress_all_with_rand_reset.101526268319630781298342972124711658665766388552922630317906699521792203905020
      Line 393, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/18.adc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 65269668504 ps: (adc_ctrl_scoreboard.sv:115) [uvm_test_top.env.scoreboard] Check failed m_interrupt == (m_expected_intr_state & intr_en) (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 65269668504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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