Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1221358	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1192922

1

T1

329

T2

513

T3

1438

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2118278	1			T1	483		T3	2510		T4	2489
values[0x0]	147494	1			T1	95		T2	618		T3	164
values[0x1]	148508	1			T1	97		T2	650		T3	155

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	978696	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1435584

1

T1

383

T2

617

T3

1752

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7140	1			T1	1		T2	6		T3	3
valid_sources[0x01]	7680	1			T1	7		T2	2		T3	1
valid_sources[0x02]	9622	1			T1	4		T2	3		T3	2
valid_sources[0x03]	7034	1			T1	5		T2	5		T3	4
valid_sources[0x04]	6557	1			T1	1		T2	5		T3	5
valid_sources[0x05]	6364	1			T2	7		T3	7		T4	13
valid_sources[0x06]	6912	1			T1	4		T2	4		T3	3
valid_sources[0x07]	12461	1			T2	5		T3	2		T4	11
valid_sources[0x08]	12906	1			T1	7		T2	5		T3	1
valid_sources[0x09]	8584	1			T2	6		T3	3		T4	24
valid_sources[0x0a]	10666	1			T2	6		T3	4		T4	14
valid_sources[0x0b]	8203	1			T1	2		T2	5		T3	6
valid_sources[0x0c]	7987	1			T1	7		T2	9		T3	4
valid_sources[0x0d]	7457	1			T1	7		T2	4		T3	3
valid_sources[0x0e]	6905	1			T1	7		T2	8		T3	2
valid_sources[0x0f]	8713	1			T1	1		T2	5		T3	85
valid_sources[0x10]	9721	1			T2	7		T3	3		T4	10
valid_sources[0x11]	11017	1			T1	4		T2	4		T3	4
valid_sources[0x12]	10937	1			T1	2		T2	4		T3	6
valid_sources[0x13]	6725	1			T1	6		T2	5		T3	2
valid_sources[0x14]	11374	1			T2	10		T3	5		T4	17
valid_sources[0x15]	6492	1			T1	6		T2	5		T3	6
valid_sources[0x16]	6785	1			T1	4		T2	4		T3	2
valid_sources[0x17]	17159	1			T1	4		T2	8		T3	1
valid_sources[0x18]	12334	1			T1	8		T2	3		T3	5
valid_sources[0x19]	10297	1			T2	5		T3	2		T4	13
valid_sources[0x1a]	10595	1			T1	3		T2	4		T3	7
valid_sources[0x1b]	13435	1			T1	4		T2	6		T3	5
valid_sources[0x1c]	19575	1			T1	1		T2	5		T3	54
valid_sources[0x1d]	6875	1			T1	5		T2	8		T3	2
valid_sources[0x1e]	6894	1			T1	2		T2	5		T3	1
valid_sources[0x1f]	7158	1			T1	1		T2	10		T3	2
valid_sources[0x20]	12007	1			T2	6		T3	4		T4	12
valid_sources[0x21]	12597	1			T1	8		T2	9		T3	6
valid_sources[0x22]	7085	1			T2	8		T3	2		T4	8
valid_sources[0x23]	7668	1			T1	1		T2	6		T3	1
valid_sources[0x24]	8131	1			T2	7		T3	8		T4	12
valid_sources[0x25]	6635	1			T2	5		T3	6		T4	5
valid_sources[0x26]	7045	1			T1	3		T2	6		T3	48
valid_sources[0x27]	8349	1			T1	2		T2	2		T3	155
valid_sources[0x28]	6683	1			T2	4		T3	7		T4	9
valid_sources[0x29]	7921	1			T1	4		T2	2		T3	1
valid_sources[0x2a]	16684	1			T2	3		T3	3		T4	8
valid_sources[0x2b]	20211	1			T2	6		T3	2		T4	12
valid_sources[0x2c]	6269	1			T1	2		T2	4		T4	10
valid_sources[0x2d]	6294	1			T1	13		T2	5		T3	3
valid_sources[0x2e]	7608	1			T1	2		T2	7		T3	5
valid_sources[0x2f]	7190	1			T1	3		T2	6		T3	4
valid_sources[0x30]	7508	1			T1	13		T2	4		T3	6
valid_sources[0x31]	17257	1			T1	6		T2	3		T3	3
valid_sources[0x32]	9342	1			T1	6		T2	2		T3	3
valid_sources[0x33]	6697	1			T1	6		T2	6		T3	2
valid_sources[0x34]	7605	1			T1	7		T2	2		T3	7
valid_sources[0x35]	6825	1			T1	8		T2	4		T3	2
valid_sources[0x36]	13799	1			T1	5		T2	4		T3	4
valid_sources[0x37]	6660	1			T2	2		T3	6		T4	12
valid_sources[0x38]	7079	1			T1	5		T2	5		T3	5
valid_sources[0x39]	6645	1			T1	5		T2	3		T3	7
valid_sources[0x3a]	6776	1			T1	5		T2	3		T3	1
valid_sources[0x3b]	7454	1			T1	6		T2	6		T3	3
valid_sources[0x3c]	10619	1			T2	2		T3	6		T4	9
valid_sources[0x3d]	7595	1			T2	3		T3	5		T4	10
valid_sources[0x3e]	18656	1			T1	5		T2	5		T3	2
valid_sources[0x3f]	6988	1			T1	1		T2	1		T3	1
valid_sources[0x40]	8707	1			T2	4		T3	6		T4	9
valid_sources[0x41]	11329	1			T1	3		T2	5		T3	5
valid_sources[0x42]	10889	1			T1	2		T2	3		T3	1
valid_sources[0x43]	9276	1			T1	1		T2	8		T3	5
valid_sources[0x44]	9769	1			T1	3		T2	3		T3	3
valid_sources[0x45]	6796	1			T1	4		T2	4		T3	6
valid_sources[0x46]	6973	1			T2	12		T3	7		T4	6
valid_sources[0x47]	6808	1			T1	2		T2	3		T3	6
valid_sources[0x48]	14280	1			T1	2		T2	3		T3	5
valid_sources[0x49]	6760	1			T1	3		T2	6		T3	93
valid_sources[0x4a]	6884	1			T1	4		T2	3		T3	2
valid_sources[0x4b]	11447	1			T1	4		T2	8		T3	2
valid_sources[0x4c]	6703	1			T1	1		T2	7		T3	5
valid_sources[0x4d]	11104	1			T1	41		T2	3		T3	4
valid_sources[0x4e]	6998	1			T1	4		T2	6		T3	4
valid_sources[0x4f]	6238	1			T1	1		T2	5		T3	1
valid_sources[0x50]	15362	1			T2	3		T3	5		T4	15
valid_sources[0x51]	6817	1			T1	1		T2	5		T3	6
valid_sources[0x52]	7358	1			T1	1		T2	6		T3	7
valid_sources[0x53]	7610	1			T2	5		T3	2		T4	9
valid_sources[0x54]	7674	1			T2	2		T3	5		T4	19
valid_sources[0x55]	11146	1			T1	3		T2	6		T3	3
valid_sources[0x56]	10629	1			T1	2		T2	4		T3	1
valid_sources[0x57]	7976	1			T2	3		T3	2		T4	18
valid_sources[0x58]	7100	1			T1	6		T2	8		T3	4
valid_sources[0x59]	7006	1			T1	2		T2	3		T3	3
valid_sources[0x5a]	12797	1			T1	6		T2	9		T3	3
valid_sources[0x5b]	6429	1			T2	3		T3	1		T4	11
valid_sources[0x5c]	13511	1			T1	1		T2	13		T3	4
valid_sources[0x5d]	7671	1			T1	3		T2	10		T3	3
valid_sources[0x5e]	7659	1			T2	6		T3	5		T4	17
valid_sources[0x5f]	10851	1			T2	4		T3	4		T4	8
valid_sources[0x60]	10785	1			T1	2		T2	8		T3	8
valid_sources[0x61]	6743	1			T2	7		T3	7		T4	12
valid_sources[0x62]	7767	1			T1	12		T2	4		T3	1
valid_sources[0x63]	10876	1			T1	8		T2	3		T3	4
valid_sources[0x64]	6553	1			T2	7		T3	4		T4	18
valid_sources[0x65]	7192	1			T2	4		T3	6		T4	7
valid_sources[0x66]	10885	1			T1	1		T2	3		T3	6
valid_sources[0x67]	6564	1			T1	6		T2	4		T3	1
valid_sources[0x68]	7604	1			T1	9		T2	3		T3	5
valid_sources[0x69]	7539	1			T2	5		T3	5		T4	11
valid_sources[0x6a]	7267	1			T2	4		T3	1		T4	9
valid_sources[0x6b]	6870	1			T2	3		T3	3		T4	13
valid_sources[0x6c]	6920	1			T1	8		T2	6		T3	2
valid_sources[0x6d]	9692	1			T1	2		T2	7		T3	6
valid_sources[0x6e]	15945	1			T2	8		T3	4		T4	6
valid_sources[0x6f]	6727	1			T1	3		T2	4		T3	4
valid_sources[0x70]	10756	1			T1	3		T2	2		T3	8
valid_sources[0x71]	6377	1			T2	4		T3	3		T4	8
valid_sources[0x72]	13886	1			T1	6		T2	5		T3	8
valid_sources[0x73]	6737	1			T1	2		T2	6		T3	2
valid_sources[0x74]	6427	1			T2	3		T3	1		T4	12
valid_sources[0x75]	7899	1			T1	4		T2	7		T3	2
valid_sources[0x76]	21248	1			T2	3		T3	4		T4	12
valid_sources[0x77]	7851	1			T1	3		T2	8		T3	959
valid_sources[0x78]	16998	1			T2	9		T3	6		T4	10
valid_sources[0x79]	10078	1			T2	3		T3	5		T4	10
valid_sources[0x7a]	7364	1			T2	9		T3	3		T4	9
valid_sources[0x7b]	7986	1			T2	5		T3	4		T4	6
valid_sources[0x7c]	7559	1			T1	1		T2	4		T3	1
valid_sources[0x7d]	6416	1			T1	4		T2	8		T3	3
valid_sources[0x7e]	9042	1			T1	4		T2	3		T3	2
valid_sources[0x7f]	8298	1			T1	8		T2	9		T3	2
valid_sources[0x80]	12076	1			T1	3		T2	3		T3	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1054829

1

T1

240

T3

1272

T4

1248

values[0x0]

all_enables

biggest_size

80214

1

T1

47

T2

291

T3

103

values[0x1]

all_enables

biggest_size

57879

1

T1

42

T2

222

T3

63