Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	28965	1			T1	6		T2	229		T3	24
auto[PWRUP]	115	1			T2	6		T43	3		T35	1
auto[ONEST_0]	55	1			T2	1		T41	2		T43	2
auto[ONEST_021]	20	1			T36	1		T182	1		T183	1
auto[ONEST_1]	84	1			T2	2		T41	2		T43	1
auto[ONEST_DONE]	3	1			T184	1		T78	1		T93	1
auto[LP_0]	137	1			T2	2		T41	2		T43	1
auto[LP_021]	23	1			T41	1		T42	1		T46	1
auto[LP_1]	141	1			T2	2		T5	1		T41	4
auto[LP_EVAL]	75	1			T5	1		T41	1		T32	1
auto[LP_SLP]	479	1			T2	4		T5	4		T41	4
auto[LP_PWRUP]	23	1			T41	1		T43	1		T42	1
auto[NP_0]	162	1			T2	3		T5	2		T41	2
auto[NP_021]	30	1			T41	1		T32	1		T42	1
auto[NP_1]	173	1			T2	3		T5	3		T41	3
auto[NP_EVAL]	28	1			T2	1		T45	1		T46	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

12

1

T45

1

T33

1

T185

1

min

28434

1

T1

5

T2

222

T3

24

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28442	1			T1	5		T2	222		T3	24
pow[0x1]	10	1			T45	1		T186	1		T44	1
pow[0x2]	19	1			T187	1		T188	1		T189	1
pow[0x3]	34	1			T5	1		T46	2		T190	1
pow[0x4]	60	1			T1	1		T5	1		T41	1
pow[0x5]	126	1			T2	1		T5	1		T41	3
pow[0x6]	278	1			T2	6		T5	3		T41	3
pow[0x7]	539	1			T2	12		T5	4		T41	8

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

194

1

T2

1

T5

5

T41

4

min

27981

1

T1

5

T2

221

T3

24

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27981	1			T1	5		T2	221		T3	24
pow[0x4]	1	1			T191	1		-	-		-	-
pow[0x5]	5	1			T192	1		T193	1		T194	1
pow[0x7]	2	1			T41	1		T195	1		-	-
pow[0x8]	4	1			T187	1		T196	1		T197	1
pow[0x9]	11	1			T46	1		T182	1		T198	1
pow[0xa]	23	1			T46	1		T187	2		T195	1
pow[0xb]	24	1			T43	2		T199	1		T195	1
pow[0xc]	58	1			T41	1		T42	1		T45	1
pow[0xd]	185	1			T41	1		T43	4		T42	3
pow[0xe]	280	1			T2	5		T41	3		T32	1
pow[0xf]	603	1			T2	8		T5	7		T41	7