Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.33	93.33	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	93.33	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.33	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	3	42	93.33

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	2	14	87.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2275	1			T1	7		T2	17		T5	9
auto[PWRUP]	132	1			T2	1		T5	1		T41	1
auto[ONEST_0]	69	1			T1	2		T2	1		T5	1
auto[ONEST_021]	15	1			T43	1		T45	1		T46	1
auto[ONEST_1]	84	1			T6	1		T43	3		T45	1
auto[ONEST_DONE]	3	1			T331	1		T332	1		T333	1
auto[LP_0]	131	1			T2	1		T41	1		T43	3
auto[LP_021]	25	1			T2	1		T199	1		T33	1
auto[LP_1]	141	1			T5	2		T41	3		T43	2
auto[LP_EVAL]	60	1			T1	1		T5	1		T32	1
auto[LP_SLP]	517	1			T1	1		T2	12		T5	5
auto[LP_PWRUP]	17	1			T199	1		T186	1		T334	1
auto[NP_0]	213	1			T2	1		T5	1		T6	1
auto[NP_021]	49	1			T42	1		T46	1		T34	2
auto[NP_1]	244	1			T1	1		T2	6		T5	3
auto[NP_EVAL]	29	1			T2	1		T6	1		T41	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

5

1

T185

1

T30

1

T335

1

min

1939

1

T1

10

T2

15

T5

6

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1946	1			T1	10		T2	15		T5	6
pow[0x1]	8	1			T15	1		T18	1		T77	1
pow[0x2]	21	1			T41	2		T46	1		T195	2
pow[0x3]	40	1			T2	1		T5	2		T42	2
pow[0x4]	77	1			T2	1		T43	1		T42	2
pow[0x5]	138	1			T2	2		T5	3		T43	3
pow[0x6]	276	1			T2	5		T41	3		T32	1
pow[0x7]	497	1			T1	2		T2	4		T5	2

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

210

1

T6

1

T41

2

T43

1

min

1385

1

T1

8

T2

8

T5

2

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	2	14	87.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1388	1			T1	8		T2	8		T5	2
pow[0x1]	15	1			T1	1		T36	1		T77	1
pow[0x2]	23	1			T33	2		T35	1		T37	3
pow[0x3]	45	1			T15	5		T33	1		T34	1
pow[0x4]	62	1			T33	5		T34	4		T35	4
pow[0x7]	4	1			T326	1		T336	1		T192	1
pow[0x8]	5	1			T334	1		T337	2		T194	1
pow[0x9]	9	1			T35	1		T338	1		T188	1
pow[0xa]	18	1			T199	1		T16	1		T190	1
pow[0xb]	34	1			T2	1		T41	1		T42	2
pow[0xc]	68	1			T2	2		T43	1		T199	1
pow[0xd]	139	1			T1	1		T41	1		T43	1
pow[0xe]	297	1			T2	4		T5	1		T41	2
pow[0xf]	539	1			T2	8		T5	7		T41	7