Unified Coverage Report :: Module :: adc_ctrl_fsm_sva

Module : adc_ctrl_fsm_sva

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_sva_0.1/adc_ctrl_fsm_sva.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva	100.00						100.00

---

Module Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.75	100.00	100.00		100.00	98.73	100.00	u_adc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_fsm_sva

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FsmDebugOut_A	31088250	31009734	0	0
FsmStateHwReset_A	1111	1111	0	0
FsmStateSwReset_A	31088250	6436	0	0
LpSampleCntHwReset_A	1111	1111	0	0
LpSampleCntSwReset_A	31088250	6436	0	0
NpSampleCntHwReset_A	1111	1111	0	0
NpSampleCntSwReset_A	31088250	6436	0	0
PwrupTimerCntHwReset_A	1111	1111	0	0
PwrupTimerCntSwReset_A	31088250	6436	0	0
WakeupTimerCntHwReset_A	1111	1111	0	0
WakeupTimerCntSwReset_A	31088250	6436	0	0

FsmDebugOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31088250	31009734	0	0
T1	680	347	0	0
T2	1021	812	0	0
T3	106560	106503	0	0
T4	118701	118640	0	0
T5	78	1	0	0
T6	1215	951	0	0
T7	66199	66122	0	0
T8	42438	42369	0	0
T9	65262	65200	0	0
T10	626	545	0	0

FsmStateHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1111	1111	0	0
T1	6	6	0	0
T2	3	3	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	6	6	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

FsmStateSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31088250	6436	0	0
T3	106560	24	0	0
T4	118701	19	0	0
T5	78	0	0	0
T6	1215	0	0	0
T7	66199	15	0	0
T8	42438	5	0	0
T9	65262	14	0	0
T10	626	0	0	0
T11	97283	20	0	0
T12	0	10	0	0
T24	78	0	0	0
T25	0	13	0	0
T26	0	15	0	0
T38	0	16	0	0

LpSampleCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1111	1111	0	0
T1	6	6	0	0
T2	3	3	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	6	6	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

LpSampleCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31088250	6436	0	0
T3	106560	24	0	0
T4	118701	19	0	0
T5	78	0	0	0
T6	1215	0	0	0
T7	66199	15	0	0
T8	42438	5	0	0
T9	65262	14	0	0
T10	626	0	0	0
T11	97283	20	0	0
T12	0	10	0	0
T24	78	0	0	0
T25	0	13	0	0
T26	0	15	0	0
T38	0	16	0	0

NpSampleCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1111	1111	0	0
T1	6	6	0	0
T2	3	3	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	6	6	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

NpSampleCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31088250	6436	0	0
T3	106560	24	0	0
T4	118701	19	0	0
T5	78	0	0	0
T6	1215	0	0	0
T7	66199	15	0	0
T8	42438	5	0	0
T9	65262	14	0	0
T10	626	0	0	0
T11	97283	20	0	0
T12	0	10	0	0
T24	78	0	0	0
T25	0	13	0	0
T26	0	15	0	0
T38	0	16	0	0

PwrupTimerCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1111	1111	0	0
T1	6	6	0	0
T2	3	3	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	6	6	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

PwrupTimerCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31088250	6436	0	0
T3	106560	24	0	0
T4	118701	19	0	0
T5	78	0	0	0
T6	1215	0	0	0
T7	66199	15	0	0
T8	42438	5	0	0
T9	65262	14	0	0
T10	626	0	0	0
T11	97283	20	0	0
T12	0	10	0	0
T24	78	0	0	0
T25	0	13	0	0
T26	0	15	0	0
T38	0	16	0	0

WakeupTimerCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1111	1111	0	0
T1	6	6	0	0
T2	3	3	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	6	6	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

WakeupTimerCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31088250	6436	0	0
T3	106560	24	0	0
T4	118701	19	0	0
T5	78	0	0	0
T6	1215	0	0	0
T7	66199	15	0	0
T8	42438	5	0	0
T9	65262	14	0	0
T10	626	0	0	0
T11	97283	20	0	0
T12	0	10	0	0
T24	78	0	0	0
T25	0	13	0	0
T26	0	15	0	0
T38	0	16	0	0