Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.58	99.68	99.52		100.00	98.69	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	99.75	100.00	100.00		100.00	98.73	100.00
u_adc_ctrl_intr	96.79	98.70	91.67			96.77	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		63	63	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	213	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	8	8
63	8	8
72	1	1
73	1	1
74	1	1
75	1	1
83	1	1
86	1	1
87	1	1
88	1	1
89	1	1
104	8	8
107	8	8
117	8	8
121	8	8
137	1	1
138	1	1
140	1	1
141	1	1
145	1	1
213	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	293	293	100.00
Logical	293	293	100.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       83
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T9
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T11
0	1	Covered	T3,T9,T11
1	0	Covered	T1,T3,T9

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T1,T9,T11
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T11
0	1	Covered	T9,T11,T13
1	0	Covered	T1,T9,T11

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T11
0	1	Covered	T3,T8,T11
1	0	Covered	T1,T3,T6

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T11
0	1	Covered	T3,T9,T11
1	0	Covered	T1,T3,T6

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T9
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T9
0	1	Covered	T3,T9,T11
1	0	Covered	T1,T3,T9

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T9
0	1	Covered	T3,T8,T9
1	0	Covered	T1,T3,T6

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T3,T8,T9
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T9
0	1	Covered	T3,T8,T11
1	0	Covered	T3,T8,T9

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T3,T4,T7
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T7
0	1	Covered	T3,T4,T7
1	0	Covered	T3,T4,T7

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T9
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T11
0	1	Covered	T3,T9,T11
1	0	Covered	T1,T3,T9

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T1,T9,T11
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T26
0	1	Covered	T9,T11,T26
1	0	Covered	T1,T9,T11

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T11
0	1	Covered	T3,T8,T11
1	0	Covered	T1,T3,T6

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T11
0	1	Covered	T3,T9,T11
1	0	Covered	T1,T3,T6

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T9
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T9
0	1	Covered	T3,T9,T11
1	0	Covered	T1,T3,T9

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T9
0	1	Covered	T3,T8,T9
1	0	Covered	T1,T3,T6

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T3,T8,T9
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T9
0	1	Covered	T3,T8,T9
1	0	Covered	T3,T8,T9

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T3,T4,T7
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T7
0	1	Covered	T3,T4,T7
1	0	Covered	T3,T4,T7

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T3,T4,T6
1	1	1	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T7,T8
1	1	0	Covered	T3,T4,T7
1	1	1	Covered	T3,T4,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T8
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T7,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T7
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T7

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T3,T4,T7
1	1	1	Covered	T1,T3,T4

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T7
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T7
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T3,T4,T7
1	1	1	Covered	T3,T4,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T7
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T7
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T7

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T3,T4,T7
1	1	1	Covered	T3,T4,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T6
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T6
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T7

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T7,T9
1	1	0	Covered	T4,T7,T9
1	1	1	Covered	T1,T4,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T9
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T9
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T7

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T3,T4,T7
1	1	1	Covered	T3,T4,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T7

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T7
1	1	0	Covered	T3,T4,T7
1	1	1	Covered	T3,T4,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T7

 LINE       121
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       121
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T7

 LINE       121
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       121
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T7

 LINE       121
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T7

 LINE       121
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T7

 LINE       121
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T7

 LINE       121
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T7

 LINE       140
 EXPRESSION (aon_fsm_trans | reg2hw_i.filter_status.trans.q)
             ------1------   ---------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       145
 EXPRESSION (((|(reg2hw_i.filter_status.match.q & reg2hw_i.adc_wakeup_ctl.match_en.q))) || (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q))
             -------------------------------------1------------------------------------    ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       145
 SUB-EXPRESSION (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q)
                 ---------------1--------------   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T3,T39,T40
1	1	Covered	T1,T3,T4

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	83	3	3	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	83	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T5
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T9

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T9

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T9,T11

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T9,T11

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T9

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T9

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T8,T9

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T8,T9

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T7

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	33693994	33384566	0	0
gen_filter_match[0].MatchCheck00_A	33693994	10116710	0	0
gen_filter_match[0].MatchCheck01_A	33693994	2569439	0	0
gen_filter_match[0].MatchCheck10_A	33693994	2692418	0	0
gen_filter_match[0].MatchCheck11_A	33693994	18005999	0	0
gen_filter_match[1].MatchCheck00_A	33693994	11823933	0	0
gen_filter_match[1].MatchCheck01_A	33693994	1823649	0	0
gen_filter_match[1].MatchCheck10_A	33693994	1350695	0	0
gen_filter_match[1].MatchCheck11_A	33693994	18386289	0	0
gen_filter_match[2].MatchCheck00_A	33693994	11928490	0	0
gen_filter_match[2].MatchCheck01_A	33693994	400557	0	0
gen_filter_match[2].MatchCheck10_A	33693994	445953	0	0
gen_filter_match[2].MatchCheck11_A	33693994	20609566	0	0
gen_filter_match[3].MatchCheck00_A	33693994	12973894	0	0
gen_filter_match[3].MatchCheck01_A	33693994	307665	0	0
gen_filter_match[3].MatchCheck10_A	33693994	354189	0	0
gen_filter_match[3].MatchCheck11_A	33693994	19748818	0	0
gen_filter_match[4].MatchCheck00_A	33693994	11978565	0	0
gen_filter_match[4].MatchCheck01_A	33693994	9	0	0
gen_filter_match[4].MatchCheck10_A	33693994	93	0	0
gen_filter_match[4].MatchCheck11_A	33693994	21405899	0	0
gen_filter_match[5].MatchCheck00_A	33693994	12954041	0	0
gen_filter_match[5].MatchCheck01_A	33693994	12	0	0
gen_filter_match[5].MatchCheck10_A	33693994	17139	0	0
gen_filter_match[5].MatchCheck11_A	33693994	20413374	0	0
gen_filter_match[6].MatchCheck00_A	33693994	12897706	0	0
gen_filter_match[6].MatchCheck01_A	33693994	32704	0	0
gen_filter_match[6].MatchCheck10_A	33693994	283139	0	0
gen_filter_match[6].MatchCheck11_A	33693994	20171017	0	0
gen_filter_match[7].MatchCheck00_A	33693994	12482659	0	0
gen_filter_match[7].MatchCheck01_A	33693994	44877	0	0
gen_filter_match[7].MatchCheck10_A	33693994	186325	0	0
gen_filter_match[7].MatchCheck11_A	33693994	20670705	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33693994	33384566	0	0
T1	12114	11451	0	0
T2	26325	23346	0	0
T3	106560	106503	0	0
T4	118701	118640	0	0
T5	15440	13634	0	0
T6	5618	4834	0	0
T7	66199	66122	0	0
T8	42438	42369	0	0
T9	65262	65200	0	0
T10	626	545	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33693994	10116710	0	0
T1	12114	10618	0	0
T2	26325	22636	0	0
T3	106560	32895	0	0
T4	118701	4	0	0
T5	15440	13001	0	0
T6	5618	3996	0	0
T7	66199	3	0	0
T8	42438	4	0	0
T9	65262	32363	0	0
T10	626	545	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33693994	2569439	0	0
T3	106560	38180	0	0
T4	118701	0	0	0
T5	15440	0	0	0
T6	5618	671	0	0
T7	66199	0	0	0
T8	42438	0	0	0
T9	65262	32837	0	0
T10	626	0	0	0
T11	97283	0	0	0
T24	88	0	0	0
T40	0	72641	0	0
T70	0	32450	0	0
T125	0	35973	0	0
T126	0	68990	0	0
T127	0	31723	0	0
T128	0	32986	0	0
T129	0	34633	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33693994	2692418	0	0
T4	118701	1	0	0
T5	15440	0	0	0
T6	5618	0	0	0
T7	66199	0	0	0
T8	42438	42365	0	0
T9	65262	0	0	0
T10	626	0	0	0
T11	97283	32522	0	0
T12	32176	0	0	0
T24	88	0	0	0
T25	0	1	0	0
T40	0	34813	0	0
T130	0	33345	0	0
T131	0	33030	0	0
T132	0	34247	0	0
T133	0	32472	0	0
T134	0	33036	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33693994	18005999	0	0
T1	12114	833	0	0
T2	26325	710	0	0
T3	106560	35428	0	0
T4	118701	118635	0	0
T5	15440	633	0	0
T6	5618	167	0	0
T7	66199	66119	0	0
T8	42438	0	0	0
T9	65262	0	0	0
T10	626	0	0	0
T11	0	32281	0	0
T12	0	32110	0	0
T25	0	79252	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33693994	11823933	0	0
T1	12114	11451	0	0
T2	26325	23346	0	0
T3	106560	71075	0	0
T4	118701	4	0	0
T5	15440	13634	0	0
T6	5618	4834	0	0
T7	66199	3	0	0
T8	42438	4	0	0
T9	65262	4	0	0
T10	626	545	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33693994	1823649	0	0
T3	106560	35428	0	0
T4	118701	0	0	0
T5	15440	0	0	0
T6	5618	0	0	0
T7	66199	0	0	0
T8	42438	0	0	0
T9	65262	0	0	0
T10	626	0	0	0
T11	97283	32400	0	0
T24	88	0	0	0
T26	0	33346	0	0
T34	0	8963	0	0
T74	0	33627	0	0
T127	0	36143	0	0
T133	0	1	0	0
T135	0	40978	0	0
T136	0	35696	0	0
T137	0	32924	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33693994	1350695	0	0
T4	118701	2	0	0
T5	15440	0	0	0
T6	5618	0	0	0
T7	66199	0	0	0
T8	42438	0	0	0
T9	65262	0	0	0
T10	626	0	0	0
T11	97283	0	0	0
T12	32176	0	0	0
T16	0	4	0	0
T24	88	0	0	0
T25	0	1	0	0
T36	0	2	0	0
T133	0	4	0	0
T138	0	32071	0	0
T139	0	38636	0	0
T140	0	33281	0	0
T141	0	32767	0	0
T142	0	32524	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33693994	18386289	0	0
T4	118701	118634	0	0
T5	15440	0	0	0
T6	5618	0	0	0
T7	66199	66119	0	0
T8	42438	42365	0	0
T9	65262	65196	0	0
T10	626	0	0	0
T11	97283	32281	0	0
T12	32176	32110	0	0
T24	88	0	0	0
T25	0	79252	0	0
T26	0	32288	0	0
T38	0	80310	0	0
T143	0	64826	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33693994	11928490	0	0
T1	12114	2677	0	0
T2	26325	23346	0	0
T3	106560	73611	0	0
T4	118701	4	0	0
T5	15440	13634	0	0
T6	5618	4834	0	0
T7	66199	3	0	0
T8	42438	42369	0	0
T9	65262	32841	0	0
T10	626	545	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33693994	400557	0	0
T3	106560	1	0	0
T4	118701	0	0	0
T5	15440	0	0	0
T6	5618	0	0	0
T7	66199	0	0	0
T8	42438	0	0	0
T9	65262	0	0	0
T10	626	0	0	0
T11	97283	0	0	0
T24	88	0	0	0
T26	0	1	0	0
T29	0	32343	0	0
T74	0	32356	0	0
T134	0	35632	0	0
T144	0	32643	0	0
T145	0	33120	0	0
T146	0	32418	0	0
T147	0	1	0	0
T148	0	2	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33693994	445953	0	0
T3	106560	1	0	0
T4	118701	2	0	0
T5	15440	0	0	0
T6	5618	0	0	0
T7	66199	0	0	0
T8	42438	0	0	0
T9	65262	0	0	0
T10	626	0	0	0
T11	97283	0	0	0
T16	0	4	0	0
T24	88	0	0	0
T25	0	1	0	0
T36	0	1	0	0
T133	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	2	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33693994	20609566	0	0
T1	12114	8774	0	0
T2	26325	0	0	0
T3	106560	32890	0	0
T4	118701	118634	0	0
T5	15440	0	0	0
T6	5618	0	0	0
T7	66199	66119	0	0
T8	42438	0	0	0
T9	65262	32359	0	0
T10	626	0	0	0
T11	0	64922	0	0
T12	0	32110	0	0
T25	0	79252	0	0
T26	0	33346	0	0
T38	0	80310	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33693994	12973894	0	0
T1	12114	11451	0	0
T2	26325	23346	0	0
T3	106560	73611	0	0
T4	118701	5	0	0
T5	15440	13634	0	0
T6	5618	4834	0	0
T7	66199	3	0	0
T8	42438	42369	0	0
T9	65262	32363	0	0
T10	626	545	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33693994	307665	0	0
T3	106560	1	0	0
T4	118701	0	0	0
T5	15440	0	0	0
T6	5618	0	0	0
T7	66199	0	0	0
T8	42438	0	0	0
T9	65262	0	0	0
T10	626	0	0	0
T11	97283	0	0	0
T24	88	0	0	0
T132	0	37517	0	0
T138	0	1	0	0
T147	0	32299	0	0
T153	0	33278	0	0
T154	0	32657	0	0
T155	0	33527	0	0
T156	0	1	0	0
T157	0	32919	0	0
T158	0	36826	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33693994	354189	0	0
T3	106560	1	0	0
T4	118701	1	0	0
T5	15440	0	0	0
T6	5618	0	0	0
T7	66199	0	0	0
T8	42438	0	0	0
T9	65262	0	0	0
T10	626	0	0	0
T11	97283	0	0	0
T16	0	4	0	0
T24	88	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T35	0	4	0	0
T36	0	2	0	0
T138	0	1	0	0
T150	0	2	0	0
T151	0	1	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33693994	19748818	0	0
T3	106560	32890	0	0
T4	118701	118634	0	0
T5	15440	0	0	0
T6	5618	0	0	0
T7	66199	66119	0	0
T8	42438	0	0	0
T9	65262	32837	0	0
T10	626	0	0	0
T11	97283	32281	0	0
T12	0	32110	0	0
T24	88	0	0	0
T25	0	79252	0	0
T26	0	32287	0	0
T38	0	80310	0	0
T102	0	32989	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33693994	11978565	0	0
T1	12114	11451	0	0
T2	26325	23346	0	0
T3	106560	68322	0	0
T4	118701	5	0	0
T5	15440	13634	0	0
T6	5618	4164	0	0
T7	66199	3	0	0
T8	42438	4	0	0
T9	65262	32841	0	0
T10	626	545	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33693994	9	0	0
T3	106560	1	0	0
T4	118701	0	0	0
T5	15440	0	0	0
T6	5618	0	0	0
T7	66199	0	0	0
T8	42438	0	0	0
T9	65262	0	0	0
T10	626	0	0	0
T11	97283	0	0	0
T24	88	0	0	0
T26	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33693994	93	0	0
T3	106560	1	0	0
T4	118701	1	0	0
T5	15440	0	0	0
T6	5618	0	0	0
T7	66199	0	0	0
T8	42438	0	0	0
T9	65262	0	0	0
T10	626	0	0	0
T11	97283	0	0	0
T16	0	3	0	0
T24	88	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T35	0	7	0	0
T133	0	2	0	0
T138	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33693994	21405899	0	0
T3	106560	38179	0	0
T4	118701	118634	0	0
T5	15440	0	0	0
T6	5618	670	0	0
T7	66199	66119	0	0
T8	42438	42365	0	0
T9	65262	32359	0	0
T10	626	0	0	0
T11	97283	32522	0	0
T12	0	32110	0	0
T24	88	0	0	0
T25	0	79252	0	0
T26	0	33345	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33693994	12954041	0	0
T1	12114	2677	0	0
T2	26325	23346	0	0
T3	106560	106503	0	0
T4	118701	5	0	0
T5	15440	13634	0	0
T6	5618	4834	0	0
T7	66199	3	0	0
T8	42438	42369	0	0
T9	65262	4	0	0
T10	626	545	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33693994	12	0	0
T13	32303	0	0	0
T26	65717	1	0	0
T32	6368	0	0	0
T38	80412	0	0	0
T41	16721	0	0	0
T63	85	0	0	0
T101	32262	0	0	0
T102	33091	0	0	0
T129	0	1	0	0
T133	0	2	0	0
T143	64910	0	0	0
T147	0	1	0	0
T148	0	1	0	0
T161	0	1	0	0
T168	0	2	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	7055	0	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33693994	17139	0	0
T4	118701	1	0	0
T5	15440	0	0	0
T6	5618	0	0	0
T7	66199	0	0	0
T8	42438	0	0	0
T9	65262	0	0	0
T10	626	0	0	0
T11	97283	0	0	0
T12	32176	0	0	0
T24	88	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T36	0	17054	0	0
T129	0	1	0	0
T133	0	2	0	0
T138	0	1	0	0
T142	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33693994	20413374	0	0
T1	12114	8774	0	0
T2	26325	0	0	0
T3	106560	0	0	0
T4	118701	118634	0	0
T5	15440	0	0	0
T6	5618	0	0	0
T7	66199	66119	0	0
T8	42438	0	0	0
T9	65262	65196	0	0
T10	626	0	0	0
T12	0	32110	0	0
T25	0	79252	0	0
T26	0	33345	0	0
T38	0	80310	0	0
T103	0	65085	0	0
T143	0	64826	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33693994	12897706	0	0
T1	12114	2677	0	0
T2	26325	23346	0	0
T3	106560	68322	0	0
T4	118701	5	0	0
T5	15440	13634	0	0
T6	5618	4164	0	0
T7	66199	3	0	0
T8	42438	4	0	0
T9	65262	32841	0	0
T10	626	545	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33693994	32704	0	0
T3	106560	1	0	0
T4	118701	0	0	0
T5	15440	0	0	0
T6	5618	0	0	0
T7	66199	0	0	0
T8	42438	0	0	0
T9	65262	0	0	0
T10	626	0	0	0
T11	97283	0	0	0
T24	88	0	0	0
T138	0	1	0	0
T146	0	2	0	0
T149	0	1	0	0
T159	0	2	0	0
T173	0	1	0	0
T174	0	32684	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	0	1	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33693994	283139	0	0
T3	106560	1	0	0
T4	118701	1	0	0
T5	15440	0	0	0
T6	5618	0	0	0
T7	66199	1	0	0
T8	42438	0	0	0
T9	65262	0	0	0
T10	626	0	0	0
T11	97283	0	0	0
T24	88	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T35	0	5	0	0
T129	0	1	0	0
T133	0	1	0	0
T138	0	1	0	0
T173	0	1	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33693994	20171017	0	0
T1	12114	8774	0	0
T2	26325	0	0	0
T3	106560	38179	0	0
T4	118701	118634	0	0
T5	15440	0	0	0
T6	5618	670	0	0
T7	66199	66118	0	0
T8	42438	42365	0	0
T9	65262	32359	0	0
T10	626	0	0	0
T11	0	64681	0	0
T12	0	32110	0	0
T25	0	79252	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33693994	12482659	0	0
T1	12114	2677	0	0
T2	26325	23346	0	0
T3	106560	35431	0	0
T4	118701	5	0	0
T5	15440	13634	0	0
T6	5618	4834	0	0
T7	66199	3	0	0
T8	42438	4	0	0
T9	65262	65200	0	0
T10	626	545	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33693994	44877	0	0
T3	106560	1	0	0
T4	118701	0	0	0
T5	15440	0	0	0
T6	5618	0	0	0
T7	66199	0	0	0
T8	42438	0	0	0
T9	65262	0	0	0
T10	626	0	0	0
T11	97283	0	0	0
T24	88	0	0	0
T138	0	1	0	0
T149	0	1	0	0
T159	0	2	0	0
T168	0	1	0	0
T173	0	44864	0	0
T175	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33693994	186325	0	0
T3	106560	1	0	0
T4	118701	1	0	0
T5	15440	0	0	0
T6	5618	0	0	0
T7	66199	1	0	0
T8	42438	0	0	0
T9	65262	0	0	0
T10	626	0	0	0
T11	97283	0	0	0
T12	0	1	0	0
T24	88	0	0	0
T25	0	2	0	0
T26	0	1	0	0
T102	0	1	0	0
T133	0	2	0	0
T138	0	1	0	0
T173	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33693994	20670705	0	0
T1	12114	8774	0	0
T2	26325	0	0	0
T3	106560	71070	0	0
T4	118701	118634	0	0
T5	15440	0	0	0
T6	5618	0	0	0
T7	66199	66118	0	0
T8	42438	42365	0	0
T9	65262	0	0	0
T10	626	0	0	0
T11	0	32522	0	0
T12	0	32109	0	0
T25	0	79251	0	0
T26	0	32287	0	0
T38	0	80310	0	0