Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2209	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2501	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2362	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2371	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2346	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2201	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2404	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2466	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2410	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2275	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2350	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2488	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2311	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2282	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2288	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2413	0	0
adc_en_ctl_rd_A	2147483647	1888	0	0
adc_fsm_rst_rd_A	2147483647	1664	0	0
adc_intr_ctl_rd_A	2147483647	2253	0	0
adc_lp_sample_ctl_rd_A	2147483647	1765	0	0
adc_pd_ctl_rd_A	2147483647	2070	0	0
adc_sample_ctl_rd_A	2147483647	1880	0	0
adc_wakeup_ctl_rd_A	2147483647	2040	0	0
intr_enable_rd_A	2147483647	2263	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2209	0	0
T6	137683	48	0	0
T7	728201	0	0	0
T8	445617	0	0	0
T9	153365	0	0	0
T10	313945	0	0	0
T11	282131	0	0	0
T12	337871	0	0	0
T15	0	39	0	0
T16	0	17	0	0
T17	0	39	0	0
T18	0	35	0	0
T19	0	10	0	0
T20	0	38	0	0
T21	0	22	0	0
T22	0	30	0	0
T23	0	20	0	0
T24	8490	0	0	0
T25	674272	0	0	0
T26	788621	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2501	0	0
T6	137683	44	0	0
T7	728201	0	0	0
T8	445617	0	0	0
T9	153365	0	0	0
T10	313945	0	0	0
T11	282131	0	0	0
T12	337871	0	0	0
T15	0	29	0	0
T16	0	12	0	0
T17	0	22	0	0
T18	0	52	0	0
T19	0	15	0	0
T20	0	40	0	0
T21	0	27	0	0
T22	0	30	0	0
T23	0	52	0	0
T24	8490	0	0	0
T25	674272	0	0	0
T26	788621	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2362	0	0
T6	137683	35	0	0
T7	728201	0	0	0
T8	445617	0	0	0
T9	153365	0	0	0
T10	313945	0	0	0
T11	282131	0	0	0
T12	337871	0	0	0
T15	0	41	0	0
T16	0	14	0	0
T17	0	28	0	0
T18	0	51	0	0
T19	0	10	0	0
T20	0	34	0	0
T21	0	21	0	0
T22	0	40	0	0
T23	0	44	0	0
T24	8490	0	0	0
T25	674272	0	0	0
T26	788621	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2371	0	0
T6	137683	20	0	0
T7	728201	0	0	0
T8	445617	0	0	0
T9	153365	0	0	0
T10	313945	0	0	0
T11	282131	0	0	0
T12	337871	0	0	0
T15	0	52	0	0
T16	0	21	0	0
T17	0	28	0	0
T18	0	36	0	0
T19	0	14	0	0
T20	0	14	0	0
T21	0	38	0	0
T22	0	36	0	0
T23	0	56	0	0
T24	8490	0	0	0
T25	674272	0	0	0
T26	788621	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2346	0	0
T6	137683	26	0	0
T7	728201	0	0	0
T8	445617	0	0	0
T9	153365	0	0	0
T10	313945	0	0	0
T11	282131	0	0	0
T12	337871	0	0	0
T15	0	28	0	0
T16	0	19	0	0
T17	0	18	0	0
T18	0	35	0	0
T19	0	6	0	0
T20	0	40	0	0
T21	0	13	0	0
T22	0	33	0	0
T23	0	41	0	0
T24	8490	0	0	0
T25	674272	0	0	0
T26	788621	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2201	0	0
T6	137683	40	0	0
T7	728201	0	0	0
T8	445617	0	0	0
T9	153365	0	0	0
T10	313945	0	0	0
T11	282131	0	0	0
T12	337871	0	0	0
T15	0	37	0	0
T16	0	4	0	0
T17	0	9	0	0
T18	0	32	0	0
T19	0	4	0	0
T20	0	48	0	0
T21	0	14	0	0
T22	0	35	0	0
T23	0	33	0	0
T24	8490	0	0	0
T25	674272	0	0	0
T26	788621	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2404	0	0
T6	137683	29	0	0
T7	728201	0	0	0
T8	445617	0	0	0
T9	153365	0	0	0
T10	313945	0	0	0
T11	282131	0	0	0
T12	337871	0	0	0
T15	0	36	0	0
T16	0	22	0	0
T17	0	35	0	0
T18	0	31	0	0
T19	0	14	0	0
T20	0	39	0	0
T21	0	19	0	0
T22	0	33	0	0
T23	0	24	0	0
T24	8490	0	0	0
T25	674272	0	0	0
T26	788621	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2466	0	0
T6	137683	40	0	0
T7	728201	0	0	0
T8	445617	0	0	0
T9	153365	0	0	0
T10	313945	0	0	0
T11	282131	0	0	0
T12	337871	0	0	0
T15	0	25	0	0
T16	0	10	0	0
T17	0	22	0	0
T18	0	30	0	0
T19	0	28	0	0
T20	0	58	0	0
T21	0	46	0	0
T22	0	33	0	0
T23	0	27	0	0
T24	8490	0	0	0
T25	674272	0	0	0
T26	788621	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2410	0	0
T6	137683	47	0	0
T7	728201	0	0	0
T8	445617	0	0	0
T9	153365	0	0	0
T10	313945	0	0	0
T11	282131	0	0	0
T12	337871	0	0	0
T15	0	24	0	0
T16	0	13	0	0
T17	0	32	0	0
T18	0	26	0	0
T19	0	12	0	0
T20	0	41	0	0
T21	0	8	0	0
T22	0	26	0	0
T23	0	30	0	0
T24	8490	0	0	0
T25	674272	0	0	0
T26	788621	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2275	0	0
T6	137683	35	0	0
T7	728201	0	0	0
T8	445617	0	0	0
T9	153365	0	0	0
T10	313945	0	0	0
T11	282131	0	0	0
T12	337871	0	0	0
T15	0	22	0	0
T16	0	15	0	0
T17	0	48	0	0
T18	0	42	0	0
T19	0	15	0	0
T20	0	33	0	0
T21	0	17	0	0
T22	0	33	0	0
T23	0	36	0	0
T24	8490	0	0	0
T25	674272	0	0	0
T26	788621	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2350	0	0
T6	137683	34	0	0
T7	728201	0	0	0
T8	445617	0	0	0
T9	153365	0	0	0
T10	313945	0	0	0
T11	282131	0	0	0
T12	337871	0	0	0
T15	0	29	0	0
T16	0	18	0	0
T17	0	37	0	0
T18	0	46	0	0
T19	0	4	0	0
T20	0	33	0	0
T21	0	47	0	0
T22	0	43	0	0
T23	0	33	0	0
T24	8490	0	0	0
T25	674272	0	0	0
T26	788621	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2488	0	0
T6	137683	58	0	0
T7	728201	0	0	0
T8	445617	0	0	0
T9	153365	0	0	0
T10	313945	0	0	0
T11	282131	0	0	0
T12	337871	0	0	0
T15	0	24	0	0
T16	0	16	0	0
T17	0	30	0	0
T18	0	40	0	0
T19	0	17	0	0
T20	0	49	0	0
T21	0	17	0	0
T22	0	31	0	0
T23	0	33	0	0
T24	8490	0	0	0
T25	674272	0	0	0
T26	788621	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2311	0	0
T6	137683	33	0	0
T7	728201	0	0	0
T8	445617	0	0	0
T9	153365	0	0	0
T10	313945	0	0	0
T11	282131	0	0	0
T12	337871	0	0	0
T15	0	38	0	0
T16	0	14	0	0
T17	0	30	0	0
T18	0	29	0	0
T19	0	15	0	0
T20	0	20	0	0
T21	0	26	0	0
T22	0	22	0	0
T23	0	30	0	0
T24	8490	0	0	0
T25	674272	0	0	0
T26	788621	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2282	0	0
T6	137683	27	0	0
T7	728201	0	0	0
T8	445617	0	0	0
T9	153365	0	0	0
T10	313945	0	0	0
T11	282131	0	0	0
T12	337871	0	0	0
T15	0	40	0	0
T16	0	20	0	0
T17	0	15	0	0
T18	0	45	0	0
T19	0	16	0	0
T20	0	27	0	0
T21	0	34	0	0
T22	0	24	0	0
T23	0	33	0	0
T24	8490	0	0	0
T25	674272	0	0	0
T26	788621	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2288	0	0
T6	137683	32	0	0
T7	728201	0	0	0
T8	445617	0	0	0
T9	153365	0	0	0
T10	313945	0	0	0
T11	282131	0	0	0
T12	337871	0	0	0
T15	0	23	0	0
T16	0	11	0	0
T17	0	8	0	0
T18	0	27	0	0
T19	0	7	0	0
T20	0	53	0	0
T21	0	39	0	0
T22	0	28	0	0
T23	0	41	0	0
T24	8490	0	0	0
T25	674272	0	0	0
T26	788621	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2413	0	0
T6	137683	22	0	0
T7	728201	0	0	0
T8	445617	0	0	0
T9	153365	0	0	0
T10	313945	0	0	0
T11	282131	0	0	0
T12	337871	0	0	0
T15	0	34	0	0
T16	0	13	0	0
T17	0	25	0	0
T18	0	56	0	0
T19	0	14	0	0
T20	0	46	0	0
T21	0	20	0	0
T22	0	47	0	0
T23	0	53	0	0
T24	8490	0	0	0
T25	674272	0	0	0
T26	788621	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1888	0	0
T6	137683	43	0	0
T7	728201	0	0	0
T8	445617	0	0	0
T9	153365	0	0	0
T10	313945	0	0	0
T11	282131	0	0	0
T12	337871	0	0	0
T15	0	32	0	0
T16	0	8	0	0
T17	0	27	0	0
T18	0	42	0	0
T19	0	5	0	0
T20	0	30	0	0
T21	0	24	0	0
T22	0	25	0	0
T23	0	28	0	0
T24	8490	0	0	0
T25	674272	0	0	0
T26	788621	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1664	0	0
T6	137683	44	0	0
T7	728201	0	0	0
T8	445617	0	0	0
T9	153365	0	0	0
T10	313945	0	0	0
T11	282131	0	0	0
T12	337871	0	0	0
T15	0	34	0	0
T16	0	20	0	0
T17	0	9	0	0
T18	0	30	0	0
T19	0	7	0	0
T20	0	25	0	0
T21	0	42	0	0
T22	0	31	0	0
T23	0	15	0	0
T24	8490	0	0	0
T25	674272	0	0	0
T26	788621	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2253	0	0
T6	137683	42	0	0
T7	728201	0	0	0
T8	445617	0	0	0
T9	153365	0	0	0
T10	313945	0	0	0
T11	282131	0	0	0
T12	337871	0	0	0
T15	0	22	0	0
T16	0	13	0	0
T17	0	25	0	0
T18	0	20	0	0
T19	0	7	0	0
T20	0	56	0	0
T21	0	30	0	0
T22	0	33	0	0
T23	0	44	0	0
T24	8490	0	0	0
T25	674272	0	0	0
T26	788621	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1765	0	0
T6	137683	34	0	0
T7	728201	0	0	0
T8	445617	0	0	0
T9	153365	0	0	0
T10	313945	0	0	0
T11	282131	0	0	0
T12	337871	0	0	0
T15	0	35	0	0
T16	0	20	0	0
T17	0	18	0	0
T18	0	33	0	0
T19	0	7	0	0
T20	0	37	0	0
T21	0	9	0	0
T22	0	30	0	0
T23	0	48	0	0
T24	8490	0	0	0
T25	674272	0	0	0
T26	788621	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2070	0	0
T6	137683	31	0	0
T7	728201	0	0	0
T8	445617	0	0	0
T9	153365	0	0	0
T10	313945	0	0	0
T11	282131	0	0	0
T12	337871	0	0	0
T15	0	39	0	0
T16	0	12	0	0
T17	0	28	0	0
T18	0	48	0	0
T19	0	16	0	0
T20	0	25	0	0
T21	0	16	0	0
T22	0	32	0	0
T23	0	18	0	0
T24	8490	0	0	0
T25	674272	0	0	0
T26	788621	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1880	0	0
T6	137683	25	0	0
T7	728201	0	0	0
T8	445617	0	0	0
T9	153365	0	0	0
T10	313945	0	0	0
T11	282131	0	0	0
T12	337871	0	0	0
T15	0	30	0	0
T16	0	25	0	0
T17	0	24	0	0
T18	0	38	0	0
T19	0	29	0	0
T20	0	29	0	0
T21	0	37	0	0
T22	0	44	0	0
T23	0	25	0	0
T24	8490	0	0	0
T25	674272	0	0	0
T26	788621	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2040	0	0
T6	137683	37	0	0
T7	728201	0	0	0
T8	445617	0	0	0
T9	153365	0	0	0
T10	313945	0	0	0
T11	282131	0	0	0
T12	337871	0	0	0
T15	0	43	0	0
T16	0	15	0	0
T17	0	27	0	0
T18	0	24	0	0
T19	0	17	0	0
T20	0	46	0	0
T21	0	6	0	0
T22	0	33	0	0
T23	0	23	0	0
T24	8490	0	0	0
T25	674272	0	0	0
T26	788621	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2263	0	0
T6	137683	51	0	0
T7	728201	0	0	0
T8	445617	0	0	0
T9	153365	0	0	0
T10	313945	0	0	0
T11	282131	0	0	0
T12	337871	0	0	0
T15	0	51	0	0
T16	0	46	0	0
T17	0	18	0	0
T18	0	49	0	0
T24	8490	0	0	0
T25	674272	0	0	0
T26	788621	0	0	0
T27	0	13	0	0
T28	0	27	0	0
T29	0	11	0	0
T30	0	20	0	0
T31	0	15	0	0