Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.59	99.69	99.52		100.00	98.72	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	99.75	100.00	100.00		100.00	98.73	100.00
u_adc_ctrl_intr	97.17	98.75	92.86			97.06	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		63	63	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	213	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	8	8
63	8	8
72	1	1
73	1	1
74	1	1
75	1	1
83	1	1
86	1	1
87	1	1
88	1	1
89	1	1
104	8	8
107	8	8
117	8	8
121	8	8
137	1	1
138	1	1
140	1	1
141	1	1
145	1	1
213	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	293	293	100.00
Logical	293	293	100.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T8,T10,T12

 LINE       83
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T1,T11,T15
1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T18
0	1	Covered	T1,T11,T18
1	0	Covered	T1,T11,T15

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T3,T10,T11
1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T11
0	1	Covered	T3,T10,T11
1	0	Covered	T3,T10,T11

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T11,T12,T15
1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T55,T156
0	1	Covered	T11,T55,T156
1	0	Covered	T11,T12,T15

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T10,T15,T55
1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T15,T55
0	1	Covered	T10,T15,T55
1	0	Covered	T10,T15,T55

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T1,T11,T12
1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T12
0	1	Covered	T1,T11,T15
1	0	Covered	T1,T11,T12

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T3,T12,T15
1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T12,T15
0	1	Covered	T3,T15,T18
1	0	Covered	T3,T12,T15

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T15
0	1	Covered	T1,T15,T18
1	0	Covered	T1,T3,T15

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T18
1	0	Covered	T1,T5,T8
1	1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T1,T11,T15
1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T15
0	1	Covered	T1,T11,T15
1	0	Covered	T1,T11,T15

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T12
1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T15
0	1	Covered	T1,T3,T15
1	0	Covered	T1,T3,T12

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T11,T12,T15
1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T55,T156
0	1	Covered	T11,T55,T156
1	0	Covered	T11,T12,T15

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T10,T15,T55
1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T15,T55
0	1	Covered	T10,T15,T55
1	0	Covered	T10,T15,T55

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T1,T11,T12
1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T12
0	1	Covered	T1,T11,T15
1	0	Covered	T1,T11,T12

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T12,T15,T18
1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T15,T18
0	1	Covered	T15,T18,T17
1	0	Covered	T12,T15,T18

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T15
0	1	Covered	T1,T3,T15
1	0	Covered	T1,T3,T15

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T15
1	0	Covered	T1,T5,T8
1	1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T2,T3,T6
1	1	1	Covered	T2,T3,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T3,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T3,T6

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T6
1	1	0	Covered	T1,T2,T6
1	1	1	Covered	T1,T2,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T6

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T2,T6,T7
1	1	0	Covered	T2,T6,T7
1	1	1	Covered	T2,T6,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T7
0	1	Covered	T2,T6,T7
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T6,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T7
0	1	Covered	T2,T6,T7
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T6,T7

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T6
1	1	0	Covered	T1,T2,T6
1	1	1	Covered	T1,T2,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T6

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T2,T3,T6
1	1	1	Covered	T2,T3,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T3,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T3,T6

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T2,T6,T7
1	1	0	Covered	T1,T2,T6
1	1	1	Covered	T1,T2,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T6

 LINE       121
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       121
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       121
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       121
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T6,T7

 LINE       121
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       121
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       121
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       121
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       140
 EXPRESSION (aon_fsm_trans | reg2hw_i.filter_status.trans.q)
             ------1------   ---------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       145
 EXPRESSION (((|(reg2hw_i.filter_status.match.q & reg2hw_i.adc_wakeup_ctl.match_en.q))) || (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q))
             -------------------------------------1------------------------------------    ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6

 LINE       145
 SUB-EXPRESSION (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q)
                 ---------------1--------------   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T12
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	83	3	3	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	83	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T8,T10,T12
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T11,T15

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T11,T15

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T3,T10,T11

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T3,T12

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T11,T12,T15

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T11,T12,T15

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T10,T15,T55

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T10,T15,T55

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T11,T12

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T11,T12

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T3,T12,T15

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T12,T15,T18

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T3,T15

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T3,T15

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T2,T3,T6

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	34073079	33758515	0	0
gen_filter_match[0].MatchCheck00_A	34073079	11084362	0	0
gen_filter_match[0].MatchCheck01_A	34073079	2447582	0	0
gen_filter_match[0].MatchCheck10_A	34073079	2320485	0	0
gen_filter_match[0].MatchCheck11_A	34073079	17906086	0	0
gen_filter_match[1].MatchCheck00_A	34073079	11331612	0	0
gen_filter_match[1].MatchCheck01_A	34073079	1450320	0	0
gen_filter_match[1].MatchCheck10_A	34073079	719395	0	0
gen_filter_match[1].MatchCheck11_A	34073079	20257188	0	0
gen_filter_match[2].MatchCheck00_A	34073079	12617787	0	0
gen_filter_match[2].MatchCheck01_A	34073079	542686	0	0
gen_filter_match[2].MatchCheck10_A	34073079	405117	0	0
gen_filter_match[2].MatchCheck11_A	34073079	20192925	0	0
gen_filter_match[3].MatchCheck00_A	34073079	13873625	0	0
gen_filter_match[3].MatchCheck01_A	34073079	360490	0	0
gen_filter_match[3].MatchCheck10_A	34073079	271184	0	0
gen_filter_match[3].MatchCheck11_A	34073079	19253216	0	0
gen_filter_match[4].MatchCheck00_A	34073079	12934475	0	0
gen_filter_match[4].MatchCheck01_A	34073079	11	0	0
gen_filter_match[4].MatchCheck10_A	34073079	107	0	0
gen_filter_match[4].MatchCheck11_A	34073079	20823922	0	0
gen_filter_match[5].MatchCheck00_A	34073079	13668309	0	0
gen_filter_match[5].MatchCheck01_A	34073079	33621	0	0
gen_filter_match[5].MatchCheck10_A	34073079	114	0	0
gen_filter_match[5].MatchCheck11_A	34073079	20056471	0	0
gen_filter_match[6].MatchCheck00_A	34073079	13279353	0	0
gen_filter_match[6].MatchCheck01_A	34073079	98117	0	0
gen_filter_match[6].MatchCheck10_A	34073079	102413	0	0
gen_filter_match[6].MatchCheck11_A	34073079	20278632	0	0
gen_filter_match[7].MatchCheck00_A	34073079	13602672	0	0
gen_filter_match[7].MatchCheck01_A	34073079	105868	0	0
gen_filter_match[7].MatchCheck10_A	34073079	187271	0	0
gen_filter_match[7].MatchCheck11_A	34073079	19862704	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34073079	33758515	0	0
T1	92691	92369	0	0
T2	121929	121869	0	0
T3	35022	34955	0	0
T4	100	5	0	0
T5	6530	6456	0	0
T6	80100	80038	0	0
T7	31299	31200	0	0
T8	3450	3049	0	0
T13	85	6	0	0
T14	79	29	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34073079	11084362	0	0
T1	92691	92369	0	0
T2	121929	3	0	0
T3	35022	4	0	0
T4	100	5	0	0
T5	6530	6456	0	0
T6	80100	4	0	0
T7	31299	3	0	0
T8	3450	3049	0	0
T13	85	6	0	0
T14	79	29	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34073079	2447582	0	0
T48	7947	0	0	0
T109	0	38535	0	0
T153	845	0	0	0
T154	655	0	0	0
T155	69813	0	0	0
T156	65464	32441	0	0
T157	65575	33108	0	0
T158	97097	32419	0	0
T159	0	31934	0	0
T160	0	33276	0	0
T161	0	40675	0	0
T162	0	65570	0	0
T163	0	33420	0	0
T164	0	35111	0	0
T165	5825	0	0	0
T166	31887	0	0	0
T167	122079	0	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34073079	2320485	0	0
T2	121929	1	0	0
T3	35022	0	0	0
T4	100	0	0	0
T5	6530	0	0	0
T6	80100	0	0	0
T7	31299	0	0	0
T8	3450	0	0	0
T9	96601	0	0	0
T13	85	0	0	0
T14	79	0	0	0
T51	0	11739	0	0
T52	0	29195	0	0
T110	0	32854	0	0
T155	0	37486	0	0
T157	0	32413	0	0
T161	0	37175	0	0
T168	0	34532	0	0
T169	0	1	0	0
T170	0	32564	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34073079	17906086	0	0
T2	121929	121865	0	0
T3	35022	34951	0	0
T4	100	0	0	0
T5	6530	0	0	0
T6	80100	80034	0	0
T7	31299	31197	0	0
T8	3450	0	0	0
T9	96601	96527	0	0
T10	0	32311	0	0
T12	0	11948	0	0
T13	85	0	0	0
T14	79	0	0	0
T15	0	3734	0	0
T46	0	32596	0	0
T47	0	3199	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34073079	11331612	0	0
T1	92691	4784	0	0
T2	121929	3	0	0
T3	35022	4	0	0
T4	100	5	0	0
T5	6530	6456	0	0
T6	80100	4	0	0
T7	31299	3	0	0
T8	3450	3049	0	0
T13	85	6	0	0
T14	79	29	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34073079	1450320	0	0
T1	92691	33399	0	0
T2	121929	0	0	0
T3	35022	0	0	0
T4	100	0	0	0
T5	6530	0	0	0
T6	80100	0	0	0
T7	31299	0	0	0
T8	3450	0	0	0
T12	0	18997	0	0
T13	85	0	0	0
T14	79	0	0	0
T54	0	10692	0	0
T110	0	36804	0	0
T155	0	32264	0	0
T161	0	35463	0	0
T171	0	41378	0	0
T172	0	36800	0	0
T173	0	32288	0	0
T174	0	32606	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34073079	719395	0	0
T2	121929	1	0	0
T3	35022	0	0	0
T4	100	0	0	0
T5	6530	0	0	0
T6	80100	0	0	0
T7	31299	0	0	0
T8	3450	0	0	0
T9	96601	0	0	0
T13	85	0	0	0
T14	79	0	0	0
T109	0	32757	0	0
T135	0	1	0	0
T163	0	40848	0	0
T169	0	1	0	0
T175	0	3	0	0
T176	0	2	0	0
T177	0	2	0	0
T178	0	3	0	0
T179	0	1	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34073079	20257188	0	0
T1	92691	54186	0	0
T2	121929	121865	0	0
T3	35022	34951	0	0
T4	100	0	0	0
T5	6530	0	0	0
T6	80100	80034	0	0
T7	31299	31197	0	0
T8	3450	0	0	0
T9	0	96527	0	0
T10	0	32311	0	0
T13	85	0	0	0
T14	79	0	0	0
T15	0	151	0	0
T18	0	33615	0	0
T46	0	32596	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34073079	12617787	0	0
T1	92691	58970	0	0
T2	121929	3	0	0
T3	35022	34955	0	0
T4	100	5	0	0
T5	6530	6456	0	0
T6	80100	4	0	0
T7	31299	3	0	0
T8	3450	3049	0	0
T13	85	6	0	0
T14	79	29	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34073079	542686	0	0
T21	0	5932	0	0
T49	37690	0	0	0
T50	1947	0	0	0
T109	104931	0	0	0
T110	69763	0	0	0
T111	81	0	0	0
T112	33150	0	0	0
T113	1220	0	0	0
T114	66067	0	0	0
T115	70183	0	0	0
T168	106751	35559	0	0
T176	0	1	0	0
T179	0	1	0	0
T180	0	33090	0	0
T181	0	32365	0	0
T182	0	32835	0	0
T183	0	32652	0	0
T184	0	31776	0	0
T185	0	32385	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34073079	405117	0	0
T2	121929	1	0	0
T3	35022	0	0	0
T4	100	0	0	0
T5	6530	0	0	0
T6	80100	0	0	0
T7	31299	0	0	0
T8	3450	0	0	0
T9	96601	0	0	0
T11	0	2	0	0
T13	85	0	0	0
T14	79	0	0	0
T135	0	1	0	0
T169	0	1	0	0
T175	0	2	0	0
T176	0	2	0	0
T177	0	2	0	0
T178	0	2	0	0
T186	0	32327	0	0
T187	0	37441	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34073079	20192925	0	0
T1	92691	33399	0	0
T2	121929	121865	0	0
T3	35022	0	0	0
T4	100	0	0	0
T5	6530	0	0	0
T6	80100	80034	0	0
T7	31299	31197	0	0
T8	3450	0	0	0
T9	0	96527	0	0
T11	0	34304	0	0
T12	0	30781	0	0
T13	85	0	0	0
T14	79	0	0	0
T15	0	148379	0	0
T18	0	33615	0	0
T46	0	32596	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34073079	13873625	0	0
T1	92691	92369	0	0
T2	121929	3	0	0
T3	35022	34955	0	0
T4	100	5	0	0
T5	6530	6456	0	0
T6	80100	4	0	0
T7	31299	3	0	0
T8	3450	1143	0	0
T13	85	6	0	0
T14	79	29	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34073079	360490	0	0
T179	0	1	0	0
T180	33192	0	0	0
T188	64798	31889	0	0
T189	0	1	0	0
T190	0	1	0	0
T191	0	31994	0	0
T192	0	1	0	0
T193	0	33527	0	0
T194	0	2	0	0
T195	0	32775	0	0
T196	0	5330	0	0
T197	66	0	0	0
T198	37988	0	0	0
T199	7799	0	0	0
T200	70	0	0	0
T201	16904	0	0	0
T202	31901	0	0	0
T203	33078	0	0	0
T204	99268	0	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34073079	271184	0	0
T2	121929	1	0	0
T3	35022	0	0	0
T4	100	0	0	0
T5	6530	0	0	0
T6	80100	0	0	0
T7	31299	1	0	0
T8	3450	0	0	0
T9	96601	0	0	0
T13	85	0	0	0
T14	79	0	0	0
T110	0	2	0	0
T135	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0
T175	0	3	0	0
T176	0	1	0	0
T177	0	2	0	0
T178	0	2	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34073079	19253216	0	0
T2	121929	121865	0	0
T3	35022	0	0	0
T4	100	0	0	0
T5	6530	0	0	0
T6	80100	80034	0	0
T7	31299	31196	0	0
T8	3450	1906	0	0
T9	96601	96527	0	0
T12	0	18997	0	0
T13	85	0	0	0
T14	79	0	0	0
T15	0	146152	0	0
T18	0	33615	0	0
T46	0	32596	0	0
T55	0	36185	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34073079	12934475	0	0
T1	92691	58970	0	0
T2	121929	3	0	0
T3	35022	4	0	0
T4	100	5	0	0
T5	6530	6456	0	0
T6	80100	4	0	0
T7	31299	3	0	0
T8	3450	1143	0	0
T13	85	6	0	0
T14	79	29	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34073079	11	0	0
T89	0	1	0	0
T170	109112	1	0	0
T179	0	1	0	0
T190	0	2	0	0
T194	0	2	0	0
T205	0	1	0	0
T206	0	2	0	0
T207	0	1	0	0
T208	41976	0	0	0
T209	34079	0	0	0
T210	7615	0	0	0
T211	91	0	0	0
T212	1170	0	0	0
T213	66	0	0	0
T214	98281	0	0	0
T215	89	0	0	0
T216	1216	0	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34073079	107	0	0
T2	121929	1	0	0
T3	35022	0	0	0
T4	100	0	0	0
T5	6530	0	0	0
T6	80100	0	0	0
T7	31299	1	0	0
T8	3450	0	0	0
T9	96601	0	0	0
T13	85	0	0	0
T14	79	0	0	0
T110	0	1	0	0
T135	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0
T175	0	3	0	0
T177	0	2	0	0
T178	0	3	0	0
T179	0	1	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34073079	20823922	0	0
T1	92691	33399	0	0
T2	121929	121865	0	0
T3	35022	34951	0	0
T4	100	0	0	0
T5	6530	0	0	0
T6	80100	80034	0	0
T7	31299	31196	0	0
T8	3450	1906	0	0
T9	0	96527	0	0
T10	0	32311	0	0
T12	0	30781	0	0
T13	85	0	0	0
T14	79	0	0	0
T46	0	32596	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34073079	13668309	0	0
T1	92691	58970	0	0
T2	121929	3	0	0
T3	35022	34955	0	0
T4	100	5	0	0
T5	6530	6456	0	0
T6	80100	4	0	0
T7	31299	3	0	0
T8	3450	3049	0	0
T13	85	6	0	0
T14	79	29	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34073079	33621	0	0
T53	23070	0	0	0
T159	96292	0	0	0
T160	33367	0	0	0
T169	66980	0	0	0
T170	0	1	0	0
T172	36883	0	0	0
T176	0	1	0	0
T190	0	2	0	0
T205	0	1	0	0
T206	0	2	0	0
T217	33676	33606	0	0
T218	0	1	0	0
T219	0	1	0	0
T220	0	1	0	0
T221	0	2	0	0
T222	836	0	0	0
T223	119691	0	0	0
T224	69029	0	0	0
T225	1220	0	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34073079	114	0	0
T2	121929	1	0	0
T3	35022	0	0	0
T4	100	0	0	0
T5	6530	0	0	0
T6	80100	0	0	0
T7	31299	1	0	0
T8	3450	0	0	0
T9	96601	0	0	0
T11	0	2	0	0
T13	85	0	0	0
T14	79	0	0	0
T135	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0
T175	0	2	0	0
T176	0	1	0	0
T177	0	2	0	0
T226	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34073079	20056471	0	0
T1	92691	33399	0	0
T2	121929	121865	0	0
T3	35022	0	0	0
T4	100	0	0	0
T5	6530	0	0	0
T6	80100	80034	0	0
T7	31299	31196	0	0
T8	3450	0	0	0
T9	0	96527	0	0
T10	0	32311	0	0
T11	0	34303	0	0
T13	85	0	0	0
T14	79	0	0	0
T15	0	4350	0	0
T18	0	33615	0	0
T46	0	32596	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34073079	13279353	0	0
T1	92691	92369	0	0
T2	121929	3	0	0
T3	35022	4	0	0
T4	100	5	0	0
T5	6530	6456	0	0
T6	80100	4	0	0
T7	31299	3	0	0
T8	3450	1143	0	0
T13	85	6	0	0
T14	79	29	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34073079	98117	0	0
T128	0	1	0	0
T170	109112	1	0	0
T192	0	1	0	0
T208	41976	0	0	0
T209	34079	0	0	0
T210	7615	0	0	0
T211	91	0	0	0
T212	1170	0	0	0
T213	66	0	0	0
T214	98281	0	0	0
T215	89	0	0	0
T216	1216	0	0	0
T218	0	1	0	0
T220	0	1	0	0
T227	0	32406	0	0
T228	0	33663	0	0
T229	0	32038	0	0
T230	0	1	0	0
T231	0	1	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34073079	102413	0	0
T2	121929	1	0	0
T3	35022	0	0	0
T4	100	0	0	0
T5	6530	0	0	0
T6	80100	0	0	0
T7	31299	1	0	0
T8	3450	0	0	0
T9	96601	0	0	0
T11	0	2	0	0
T13	85	0	0	0
T14	79	0	0	0
T135	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0
T175	0	2	0	0
T177	0	2	0	0
T178	0	2	0	0
T226	0	1	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34073079	20278632	0	0
T2	121929	121865	0	0
T3	35022	34951	0	0
T4	100	0	0	0
T5	6530	0	0	0
T6	80100	80034	0	0
T7	31299	31196	0	0
T8	3450	1906	0	0
T9	96601	96527	0	0
T10	0	32311	0	0
T11	0	34303	0	0
T13	85	0	0	0
T14	79	0	0	0
T15	0	2274	0	0
T46	0	32596	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34073079	13602672	0	0
T1	92691	38183	0	0
T2	121929	3	0	0
T3	35022	34955	0	0
T4	100	5	0	0
T5	6530	6456	0	0
T6	80100	4	0	0
T7	31299	3	0	0
T8	3450	1143	0	0
T13	85	6	0	0
T14	79	29	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34073079	105868	0	0
T16	65818	0	0	0
T17	36943	0	0	0
T47	13955	2333	0	0
T55	72530	0	0	0
T56	17860	0	0	0
T57	67097	0	0	0
T89	0	1	0	0
T109	0	33578	0	0
T110	0	2	0	0
T135	97677	0	0	0
T156	65464	0	0	0
T157	65575	0	0	0
T170	0	1	0	0
T176	0	1	0	0
T205	0	1	0	0
T219	0	1	0	0
T232	0	33288	0	0
T233	0	36649	0	0
T234	66373	0	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34073079	187271	0	0
T2	121929	1	0	0
T3	35022	0	0	0
T4	100	0	0	0
T5	6530	0	0	0
T6	80100	0	0	0
T7	31299	1	0	0
T8	3450	0	0	0
T9	96601	0	0	0
T11	0	2	0	0
T12	0	11784	0	0
T13	85	0	0	0
T14	79	0	0	0
T48	0	4611	0	0
T110	0	1	0	0
T114	0	1	0	0
T135	0	1	0	0
T166	0	31792	0	0
T170	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34073079	19862704	0	0
T1	92691	54186	0	0
T2	121929	121865	0	0
T3	35022	0	0	0
T4	100	0	0	0
T5	6530	0	0	0
T6	80100	80034	0	0
T7	31299	31196	0	0
T8	3450	1906	0	0
T9	0	96527	0	0
T10	0	32311	0	0
T11	0	34303	0	0
T12	0	18997	0	0
T13	85	0	0	0
T14	79	0	0	0
T46	0	32596	0	0