Unified Coverage Report :: Module

Module : adc_ctrl_intr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.56	95.45	93.33			88.89

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_intr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr	92.56	95.45	93.33			88.89

Module Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.56	95.45	93.33			88.89

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.17	98.75	92.86			97.06	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_adc_ctrl_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
i_adc_ctrl_intr_o	100.00	100.00	100.00			100.00	100.00
u_match_sync	93.75	100.00	75.00			100.00	100.00

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_intr

	Line No.	Total	Covered	Percent
TOTAL		22	21	95.45
CONT_ASSIGN	39	1	1	100.00
ALWAYS	51	8	7	87.50
CONT_ASSIGN	66	1	1	100.00
ALWAYS	70	6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	109	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_intr.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_intr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
51	1	1
52	1	1
53	1	1
54	0	1
55	1	1
56	1	1
57	1	1
58	1	1
			MISSING_ELSE
66	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
			MISSING_ELSE
96	1	1
101	1	1
102	1	1
103	1	1
105	1	1
109	1	1

Cond Coverage for Module : adc_ctrl_intr

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (aon_ld_req && ((|aon_reqs)))
             -----1----    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       66
 EXPRESSION ((aon_req_hold_q == '0) & ((|staging_reqs_q)))
             -----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T12,T15,T16
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (aon_req_hold_q == '0)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       96
 EXPRESSION (cfg_intr_trans_en_i && dst_ack && aon_req_hold_q[8])
             ---------1---------    ---2---    --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T12,T15,T17
1	1	0	Covered	T9,T12,T18
1	1	1	Covered	T12,T15,T17

 LINE       105
 EXPRESSION (cfg_oneshot_done_i && cfg_oneshot_done_en_i)
             ---------1--------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T12,T19,T15
1	1	Covered	T8,T10,T12

Branch Coverage for Module : adc_ctrl_intr

	Line No.	Total	Covered	Percent
Branches		9	8	88.89
IF	51	5	4	80.00
IF	70	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_intr.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_intr.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	51	if ((!rst_aon_ni))
-2-:	53	if ((aon_ld_req && (|aon_reqs)))
-3-:	55	if (aon_ld_req)
-4-:	57	if ((|aon_reqs))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T4
0	1	-	-	Not Covered
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Covered	T1,T2,T3
0	0	0	0	Covered	T1,T2,T4



	LineNo.	Expression
-1-:	70	if ((!rst_aon_ni))
-2-:	72	if (aon_ld_req)
-3-:	74	if (aon_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T4
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T4