Unified Coverage Report :: Module :: adc_ctrl_fsm_sva

Module : adc_ctrl_fsm_sva

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_sva_0.1/adc_ctrl_fsm_sva.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva	100.00						100.00

---

Module Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.75	100.00	100.00		100.00	98.73	100.00	u_adc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_fsm_sva

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FsmDebugOut_A	31070228	30997539	0	0
FsmStateHwReset_A	1011	1011	0	0
FsmStateSwReset_A	31070228	6470	0	0
LpSampleCntHwReset_A	1011	1011	0	0
LpSampleCntSwReset_A	31070228	6470	0	0
NpSampleCntHwReset_A	1011	1011	0	0
NpSampleCntSwReset_A	31070228	6470	0	0
PwrupTimerCntHwReset_A	1011	1011	0	0
PwrupTimerCntSwReset_A	31070228	6470	0	0
WakeupTimerCntHwReset_A	1011	1011	0	0
WakeupTimerCntSwReset_A	31070228	6470	0	0

FsmDebugOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31070228	30997539	0	0
T1	82	1	0	0
T2	1139	1053	0	0
T3	308	136	0	0
T4	749	676	0	0
T5	1107	1028	0	0
T6	1227	1139	0	0
T7	7255	7183	0	0
T8	63	1	0	0
T21	83	1	0	0
T22	90	1	0	0

FsmStateHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1011	1011	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	4	4	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

FsmStateSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31070228	6470	0	0
T12	96843	24	0	0
T13	35222	7	0	0
T14	75	0	0	0
T15	0	8	0	0
T16	0	6	0	0
T17	0	8	0	0
T19	0	15	0	0
T27	1035	0	0	0
T37	100	0	0	0
T38	6148	0	0	0
T39	5577	0	0	0
T40	313	0	0	0
T41	1185	0	0	0
T42	8111	0	0	0
T47	0	18	0	0
T52	0	6	0	0
T53	0	12	0	0
T81	0	8	0	0

LpSampleCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1011	1011	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	4	4	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

LpSampleCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31070228	6470	0	0
T12	96843	24	0	0
T13	35222	7	0	0
T14	75	0	0	0
T15	0	8	0	0
T16	0	6	0	0
T17	0	8	0	0
T19	0	15	0	0
T27	1035	0	0	0
T37	100	0	0	0
T38	6148	0	0	0
T39	5577	0	0	0
T40	313	0	0	0
T41	1185	0	0	0
T42	8111	0	0	0
T47	0	18	0	0
T52	0	6	0	0
T53	0	12	0	0
T81	0	8	0	0

NpSampleCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1011	1011	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	4	4	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

NpSampleCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31070228	6470	0	0
T12	96843	24	0	0
T13	35222	7	0	0
T14	75	0	0	0
T15	0	8	0	0
T16	0	6	0	0
T17	0	8	0	0
T19	0	15	0	0
T27	1035	0	0	0
T37	100	0	0	0
T38	6148	0	0	0
T39	5577	0	0	0
T40	313	0	0	0
T41	1185	0	0	0
T42	8111	0	0	0
T47	0	18	0	0
T52	0	6	0	0
T53	0	12	0	0
T81	0	8	0	0

PwrupTimerCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1011	1011	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	4	4	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

PwrupTimerCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31070228	6470	0	0
T12	96843	24	0	0
T13	35222	7	0	0
T14	75	0	0	0
T15	0	8	0	0
T16	0	6	0	0
T17	0	8	0	0
T19	0	15	0	0
T27	1035	0	0	0
T37	100	0	0	0
T38	6148	0	0	0
T39	5577	0	0	0
T40	313	0	0	0
T41	1185	0	0	0
T42	8111	0	0	0
T47	0	18	0	0
T52	0	6	0	0
T53	0	12	0	0
T81	0	8	0	0

WakeupTimerCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1011	1011	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	4	4	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

WakeupTimerCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31070228	6470	0	0
T12	96843	24	0	0
T13	35222	7	0	0
T14	75	0	0	0
T15	0	8	0	0
T16	0	6	0	0
T17	0	8	0	0
T19	0	15	0	0
T27	1035	0	0	0
T37	100	0	0	0
T38	6148	0	0	0
T39	5577	0	0	0
T40	313	0	0	0
T41	1185	0	0	0
T42	8111	0	0	0
T47	0	18	0	0
T52	0	6	0	0
T53	0	12	0	0
T81	0	8	0	0