Line Coverage for Module :
adc_ctrl_fsm
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 162 | 162 | 100.00 |
| CONT_ASSIGN | 58 | 1 | 1 | 100.00 |
| ALWAYS | 61 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 71 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| ALWAYS | 77 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
| ALWAYS | 90 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| ALWAYS | 103 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| ALWAYS | 117 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 127 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 129 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| ALWAYS | 136 | 14 | 14 | 100.00 |
| ALWAYS | 157 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 169 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 173 | 1 | 1 | 100.00 |
| ALWAYS | 176 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 186 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| ALWAYS | 190 | 95 | 95 | 100.00 |
57 fsm_state_e fsm_state_q, fsm_state_d;
58 1/1 assign aon_fsm_state_o = fsm_state_q;
Tests: T1 T2 T3
59
60 always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin
61 1/1 if (!rst_aon_ni) begin
Tests: T1 T2 T3
62 1/1 trigger_q <= 1'b0;
Tests: T1 T2 T3
63 end
64 1/1 else if (cfg_fsm_rst_i) begin
Tests: T1 T2 T3
65 1/1 trigger_q <= 1'b0;
Tests: T12 T13 T15
66 end else begin
67 1/1 trigger_q <= cfg_adc_enable_i;
Tests: T1 T2 T3
68 end
69 end
70
71 1/1 assign trigger_l2h = (trigger_q == 1'b0) && (cfg_adc_enable_i == 1'b1);
Tests: T1 T2 T3
72 1/1 assign trigger_h2l = (trigger_q == 1'b1) && (cfg_adc_enable_i == 1'b0);
Tests: T1 T2 T3
73
74 1/1 assign pwrup_timer_cnt_d = (pwrup_timer_cnt_en) ? pwrup_timer_cnt_q + 1'b1 : pwrup_timer_cnt_q;
Tests: T1 T2 T3
75
76 always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin
77 1/1 if (!rst_aon_ni) begin
Tests: T1 T2 T3
78 1/1 pwrup_timer_cnt_q <= '0;
Tests: T1 T2 T3
79 end
80 1/1 else if (pwrup_timer_cnt_clr || cfg_fsm_rst_i || trigger_h2l) begin
Tests: T1 T2 T3
81 1/1 pwrup_timer_cnt_q <= '0;
Tests: T2 T3 T4
82 end else begin
83 1/1 pwrup_timer_cnt_q <= pwrup_timer_cnt_d;
Tests: T1 T2 T3
84 end
85 end
86
87 1/1 assign lp_sample_cnt_d = (lp_sample_cnt_en) ? lp_sample_cnt_q + 1'b1 : lp_sample_cnt_q;
Tests: T1 T2 T3
88
89 always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin
90 1/1 if (!rst_aon_ni) begin
Tests: T1 T2 T3
91 1/1 lp_sample_cnt_q <= '0;
Tests: T1 T2 T3
92 end
93 1/1 else if (lp_sample_cnt_clr || cfg_fsm_rst_i || trigger_h2l) begin
Tests: T1 T2 T3
94 1/1 lp_sample_cnt_q <= '0;
Tests: T2 T4 T5
95 end else begin
96 1/1 lp_sample_cnt_q <= lp_sample_cnt_d;
Tests: T1 T2 T3
97 end
98 end
99
100 1/1 assign np_sample_cnt_d = (np_sample_cnt_en) ? np_sample_cnt_q + 1'b1 : np_sample_cnt_q;
Tests: T1 T2 T3
101
102 always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin
103 1/1 if (!rst_aon_ni) begin
Tests: T1 T2 T3
104 1/1 np_sample_cnt_q <= '0;
Tests: T1 T2 T3
105 end
106 1/1 else if (np_sample_cnt_clr || cfg_fsm_rst_i || trigger_h2l) begin
Tests: T1 T2 T3
107 1/1 np_sample_cnt_q <= '0;
Tests: T2 T4 T5
108 end else begin
109 1/1 np_sample_cnt_q <= np_sample_cnt_d;
Tests: T1 T2 T3
110 end
111 end
112
113 1/1 assign wakeup_timer_cnt_d = (wakeup_timer_cnt_en) ?
Tests: T1 T2 T3
114 wakeup_timer_cnt_q + 1'b1 : wakeup_timer_cnt_q;
115
116 always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin
117 1/1 if (!rst_aon_ni) begin
Tests: T1 T2 T3
118 1/1 wakeup_timer_cnt_q <= '0;
Tests: T1 T2 T3
119 end
120 1/1 else if (wakeup_timer_cnt_clr || cfg_fsm_rst_i || trigger_h2l) begin
Tests: T1 T2 T3
121 1/1 wakeup_timer_cnt_q <= '0;
Tests: T2 T4 T5
122 end else begin
123 1/1 wakeup_timer_cnt_q <= wakeup_timer_cnt_d;
Tests: T1 T2 T3
124 end
125 end
126
127 1/1 assign fsm_chn0_sel = (fsm_state_q == ONEST_0) || (fsm_state_q == LP_0) || (fsm_state_q == NP_0);
Tests: T1 T2 T3
128 1/1 assign chn0_val_we_d = fsm_chn0_sel && adc_d_val_i;//adc_d_val_i is a valid pulse
Tests: T1 T2 T3
129 1/1 assign chn0_val_d = (chn0_val_we_d) ? adc_d_i : chn0_val_o;
Tests: T1 T2 T3
130
131 1/1 assign fsm_chn1_sel = (fsm_state_q == ONEST_1) || (fsm_state_q == LP_1) || (fsm_state_q == NP_1);
Tests: T1 T2 T3
132 1/1 assign chn1_val_we_d = fsm_chn1_sel && adc_d_val_i;
Tests: T1 T2 T3
133 1/1 assign chn1_val_d = (chn1_val_we_d) ? adc_d_i : chn1_val_o;
Tests: T1 T2 T3
134
135 always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin
136 1/1 if (!rst_aon_ni) begin
Tests: T1 T2 T3
137 1/1 chn0_val_we_o <= '0;
Tests: T1 T2 T3
138 1/1 chn1_val_we_o <= '0;
Tests: T1 T2 T3
139 1/1 chn0_val_o <= '0;
Tests: T1 T2 T3
140 1/1 chn1_val_o <= '0;
Tests: T1 T2 T3
141 end
142 1/1 else if (cfg_fsm_rst_i) begin
Tests: T1 T2 T3
143 1/1 chn0_val_we_o <= '0;
Tests: T12 T13 T15
144 1/1 chn1_val_we_o <= '0;
Tests: T12 T13 T15
145 1/1 chn0_val_o <= '0;
Tests: T12 T13 T15
146 1/1 chn1_val_o <= '0;
Tests: T12 T13 T15
147 end else begin
148 1/1 chn0_val_we_o <= chn0_val_we_d;
Tests: T1 T2 T3
149 1/1 chn1_val_we_o <= chn1_val_we_d;
Tests: T1 T2 T3
150 1/1 chn0_val_o <= chn0_val_d;
Tests: T1 T2 T3
151 1/1 chn1_val_o <= chn1_val_d;
Tests: T1 T2 T3
152 end
153 end
154
155 logic ld_match;
156 always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin
157 1/1 if (!rst_aon_ni) begin
Tests: T1 T2 T3
158 1/1 adc_ctrl_match_q <= '0;
Tests: T1 T2 T3
159 end
160 1/1 else if (cfg_fsm_rst_i) begin
Tests: T1 T2 T3
161 1/1 adc_ctrl_match_q <= '0;
Tests: T12 T13 T15
162 end
163 1/1 else if (ld_match) begin
Tests: T1 T2 T3
164 1/1 adc_ctrl_match_q <= adc_ctrl_match_i;
Tests: T2 T3 T4
165 end
MISSING_ELSE
166 end
167
168 logic np_match;
169 1/1 assign np_match = |adc_ctrl_match_i & // if current match is non-zero
Tests: T1 T2 T3
170 ((adc_ctrl_match_i == adc_ctrl_match_q) | // match if same as previous match
171 ~|adc_ctrl_match_q); // or match if previous match was zero
172
173 1/1 assign stay_match = np_match;
Tests: T1 T2 T3
174
175 always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin
176 1/1 if (!rst_aon_ni) begin
Tests: T1 T2 T3
177 1/1 fsm_state_q <= PWRDN;
Tests: T1 T2 T3
178 end
179 1/1 else if (trigger_h2l || cfg_fsm_rst_i) begin
Tests: T1 T2 T3
180 1/1 fsm_state_q <= PWRDN;
Tests: T2 T4 T5
181 end else begin
182 1/1 fsm_state_q <= fsm_state_d;
Tests: T1 T2 T3
183 end
184 end
185
186 1/1 assign lp_sample_cnt_thresh = cfg_lp_sample_cnt_i - 1'b1;
Tests: T1 T2 T3
187 1/1 assign np_sample_cnt_thresh = cfg_np_sample_cnt_i - 1'b1;
Tests: T1 T2 T3
188
189 always_comb begin: adc_fsm
190 1/1 fsm_state_d = fsm_state_q;
Tests: T1 T2 T3
191 //outputs
192 1/1 adc_chn_sel_o = 2'b0;
Tests: T1 T2 T3
193 1/1 adc_pd_o = 1'b0;//default value
Tests: T1 T2 T3
194 1/1 pwrup_timer_cnt_clr = 1'b0;
Tests: T1 T2 T3
195 1/1 pwrup_timer_cnt_en = 1'b0;
Tests: T1 T2 T3
196 1/1 lp_sample_cnt_clr = 1'b0;
Tests: T1 T2 T3
197 1/1 lp_sample_cnt_en = 1'b0;
Tests: T1 T2 T3
198 1/1 wakeup_timer_cnt_clr = 1'b0;
Tests: T1 T2 T3
199 1/1 wakeup_timer_cnt_en = 1'b0;
Tests: T1 T2 T3
200 1/1 np_sample_cnt_clr = 1'b0;
Tests: T1 T2 T3
201 1/1 np_sample_cnt_en = 1'b0;
Tests: T1 T2 T3
202 1/1 adc_ctrl_done_o = 1'b0;
Tests: T1 T2 T3
203 1/1 oneshot_done_o = 1'b0;
Tests: T1 T2 T3
204 1/1 ld_match = 1'b0;
Tests: T1 T2 T3
205 1/1 aon_fsm_trans_o = 1'b0;
Tests: T1 T2 T3
206
207 1/1 unique case (fsm_state_q)
Tests: T1 T2 T3
208 PWRDN: begin
209 1/1 adc_pd_o = 1'b1;
Tests: T1 T2 T3
210 1/1 if (trigger_l2h) begin
Tests: T1 T2 T3
211 1/1 fsm_state_d = PWRUP;
Tests: T2 T3 T4
212 end
MISSING_ELSE
213 end
214
215 PWRUP: begin
216 1/1 if (pwrup_timer_cnt_q != cfg_pwrup_time_i) begin
Tests: T2 T3 T4
217 1/1 pwrup_timer_cnt_en = 1'b1;
Tests: T2 T3 T4
218 end
219 1/1 else if (pwrup_timer_cnt_q == cfg_pwrup_time_i) begin
Tests: T2 T3 T4
220 1/1 pwrup_timer_cnt_clr = 1'b1;
Tests: T2 T3 T4
221 1/1 if (cfg_oneshot_mode_i) begin
Tests: T2 T3 T4
222 1/1 fsm_state_d = ONEST_0;
Tests: T2 T4 T5
223 end
224 1/1 else if (cfg_lp_mode_i) begin
Tests: T2 T3 T4
225 1/1 fsm_state_d = LP_0;
Tests: T7 T8 T13
226 end
227 1/1 else if (!cfg_lp_mode_i) begin
Tests: T2 T3 T4
228 1/1 fsm_state_d = NP_0;
Tests: T2 T3 T4
229 end
==> MISSING_ELSE
230 end
==> MISSING_ELSE
231 end
232
233 ONEST_0: begin
234 1/1 adc_chn_sel_o = 2'b01;
Tests: T2 T4 T5
235 1/1 if (adc_d_val_i) begin//sample chn0 value
Tests: T2 T4 T5
236 1/1 fsm_state_d = ONEST_021;
Tests: T2 T4 T5
237 end
MISSING_ELSE
238 end
239
240 ONEST_021: begin//transition between chn0 and chn1; adc_chn_sel_o=2'b0
241 1/1 if (!adc_d_val_i) begin
Tests: T2 T4 T5
242 1/1 fsm_state_d = ONEST_1;
Tests: T2 T4 T5
243 end
MISSING_ELSE
244 end
245
246 ONEST_1: begin
247 1/1 adc_chn_sel_o = 2'b10;
Tests: T2 T4 T5
248 1/1 if (adc_d_val_i) begin//sample chn1 value
Tests: T2 T4 T5
249 1/1 fsm_state_d = ONEST_DONE;
Tests: T2 T4 T5
250 end
MISSING_ELSE
251 end
252
253 // delay done assertion by one cycle to match
254 // adc capture register timing
255 ONEST_DONE: begin
256 1/1 oneshot_done_o = 1'b1;
Tests: T2 T4 T5
257 1/1 fsm_state_d = PWRDN;
Tests: T2 T4 T5
258 end
259
260 LP_0: begin
261 1/1 adc_chn_sel_o = 2'b01;
Tests: T7 T8 T13
262 1/1 if (adc_d_val_i) begin//sample chn0 value
Tests: T7 T8 T13
263 1/1 fsm_state_d = LP_021;
Tests: T7 T8 T13
264 end
MISSING_ELSE
265 end
266
267 LP_021: begin//transition between chn0 and chn1; adc_chn_sel_o=2'b0
268 1/1 if (!adc_d_val_i) begin
Tests: T7 T8 T13
269 1/1 fsm_state_d = LP_1;
Tests: T7 T8 T13
270 end
MISSING_ELSE
271 end
272
273 LP_1: begin
274 1/1 adc_chn_sel_o = 2'b10;
Tests: T7 T8 T13
275 1/1 if (adc_d_val_i) begin//sample chn1 value
Tests: T7 T8 T13
276 1/1 fsm_state_d = LP_EVAL;
Tests: T7 T8 T13
277 end
MISSING_ELSE
278 end
279
280 LP_EVAL: begin
281 // do not transition forward until handshake with ADC is complete
282 1/1 if (!adc_d_val_i) begin
Tests: T7 T8 T13
283 1/1 ld_match = 1'b1;
Tests: T7 T8 T13
284 1/1 if (!stay_match) begin
Tests: T7 T8 T13
285 1/1 fsm_state_d = LP_SLP;
Tests: T7 T13 T14
286 1/1 lp_sample_cnt_clr = 1'b1;
Tests: T7 T13 T14
287 1/1 end else if (lp_sample_cnt_q < lp_sample_cnt_thresh) begin
Tests: T8 T13 T14
288 1/1 fsm_state_d = LP_SLP;
Tests: T8 T13 T14
289 1/1 lp_sample_cnt_en = 1'b1;
Tests: T8 T13 T14
290 1/1 end else if (lp_sample_cnt_q == lp_sample_cnt_thresh) begin
Tests: T8 T13 T14
291 1/1 fsm_state_d = NP_0;
Tests: T8 T13 T14
292 1/1 lp_sample_cnt_clr = 1'b1;
Tests: T8 T13 T14
293 1/1 aon_fsm_trans_o = 1'b1;
Tests: T8 T13 T14
294 end
MISSING_ELSE
295 end
MISSING_ELSE
296 end
297
298 LP_SLP: begin
299 1/1 adc_pd_o = 1'b1;
Tests: T7 T8 T13
300 1/1 if (wakeup_timer_cnt_q != cfg_wakeup_time_i) begin
Tests: T7 T8 T13
301 1/1 wakeup_timer_cnt_en = 1'b1;
Tests: T7 T8 T13
302 end
303 1/1 else if (wakeup_timer_cnt_q == cfg_wakeup_time_i) begin
Tests: T7 T8 T13
304 1/1 fsm_state_d = LP_PWRUP;
Tests: T7 T8 T13
305 1/1 wakeup_timer_cnt_clr = 1'b1;
Tests: T7 T8 T13
306 end
==> MISSING_ELSE
307 end
308
309 LP_PWRUP: begin
310 1/1 if (pwrup_timer_cnt_q != cfg_pwrup_time_i) begin
Tests: T7 T8 T13
311 1/1 pwrup_timer_cnt_en = 1'b1;
Tests: T7 T8 T13
312 end
313 1/1 else if (pwrup_timer_cnt_q == cfg_pwrup_time_i) begin
Tests: T7 T8 T13
314 1/1 pwrup_timer_cnt_clr = 1'b1;
Tests: T7 T8 T13
315 1/1 fsm_state_d = LP_0;
Tests: T7 T8 T13
316 end
==> MISSING_ELSE
317 end
318
319 NP_0: begin
320 1/1 adc_chn_sel_o = 2'b01;
Tests: T2 T3 T4
321 1/1 if (adc_d_val_i) begin//sample chn0 value
Tests: T2 T3 T4
322 1/1 fsm_state_d = NP_021;
Tests: T2 T3 T4
323 end
MISSING_ELSE
324 end
325
326 NP_021: begin//transition between chn0 and chn1; adc_chn_sel_o=2'b0
327 1/1 if (!adc_d_val_i) begin
Tests: T2 T3 T4
328 1/1 fsm_state_d = NP_1;
Tests: T2 T3 T4
329 end
MISSING_ELSE
330 end
331
332 NP_1: begin
333 1/1 adc_chn_sel_o = 2'b10;
Tests: T2 T3 T4
334 1/1 if (adc_d_val_i) begin//sample chn1 value
Tests: T2 T3 T4
335 1/1 fsm_state_d = NP_EVAL;
Tests: T2 T3 T4
336 end
MISSING_ELSE
337 end
338
339 NP_EVAL: begin
340 // do not transition forward until handshake with ADC is complete
341 1/1 if (!adc_d_val_i) begin
Tests: T2 T3 T4
342 1/1 ld_match = 1'b1;
Tests: T2 T3 T4
343 // if there is no match in normal power mode, clear counter and begin sampling again.
344 // if there is no match and low power mode is enabled, clear counter and go back to LP_0.
345 //
346 // if there is a match, there are 3 conditions:
347 // 1. the sample count is less than the threshold -> still attempting to make a new match,
348 // keep sampling.
349 // 2. the sample count is equal to the threshold -> a new match has just been made, go to
350 // DONE.
351 // 3, the sample count is greater than the threshold -> this is a continued stable match,
352 // keep sampling.
353 1/1 if (!stay_match) begin
Tests: T2 T3 T4
354 1/1 if (cfg_lp_mode_i) begin
Tests: T2 T4 T10
355 1/1 fsm_state_d = LP_0;
Tests: T13 T15 T20
356 end else begin
357 1/1 fsm_state_d = NP_0;
Tests: T2 T4 T10
358 end
359 1/1 np_sample_cnt_clr = 1'b1;
Tests: T2 T4 T10
360 1/1 end else if (np_sample_cnt_q < np_sample_cnt_thresh) begin
Tests: T3 T8 T12
361 1/1 fsm_state_d = NP_0;
Tests: T3 T8 T12
362 1/1 np_sample_cnt_en = 1'b1;
Tests: T3 T8 T12
363 1/1 end else if (np_sample_cnt_q == np_sample_cnt_thresh) begin
Tests: T8 T12 T13
364 1/1 fsm_state_d = NP_DONE;
Tests: T8 T12 T13
365 1/1 np_sample_cnt_en = 1'b1;
Tests: T8 T12 T13
366 1/1 end else if (np_sample_cnt_q > np_sample_cnt_thresh) begin
Tests: T8 T12 T13
367 1/1 fsm_state_d = NP_0;
Tests: T8 T12 T13
368 end
==> MISSING_ELSE
369 end
MISSING_ELSE
370 end
371
372 // delay done assertion by one cycle to match with channel register timing
373 NP_DONE: begin
374 1/1 adc_ctrl_done_o = 1'b1;
Tests: T8 T12 T13
375 1/1 fsm_state_d = NP_0;
Tests: T8 T12 T13
376 end
377
378 default: fsm_state_d = PWRDN;
Cond Coverage for Module :
adc_ctrl_fsm
| Total | Covered | Percent |
|---|
| Conditions | 95 | 92 | 96.84 |
| Logical | 95 | 92 | 96.84 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 71
EXPRESSION ((trigger_q == 1'b0) && (cfg_adc_enable_i == 1'b1))
---------1--------- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T4 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T4 |
LINE 71
SUB-EXPRESSION (trigger_q == 1'b0)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (cfg_adc_enable_i == 1'b1)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 72
EXPRESSION ((trigger_q == 1'b1) && (cfg_adc_enable_i == 1'b0))
---------1--------- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T4 |
| 1 | 1 | Covered | T2,T4,T5 |
LINE 72
SUB-EXPRESSION (trigger_q == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 72
SUB-EXPRESSION (cfg_adc_enable_i == 1'b0)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 74
EXPRESSION (pwrup_timer_cnt_en ? ((pwrup_timer_cnt_q + 1'b1)) : pwrup_timer_cnt_q)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 80
EXPRESSION (pwrup_timer_cnt_clr || cfg_fsm_rst_i || trigger_h2l)
---------1--------- ------2------ -----3-----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T2,T4,T5 |
| 0 | 1 | 0 | Covered | T12,T13,T15 |
| 1 | 0 | 0 | Covered | T2,T3,T4 |
LINE 87
EXPRESSION (lp_sample_cnt_en ? ((lp_sample_cnt_q + 1'b1)) : lp_sample_cnt_q)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T8,T13,T14 |
LINE 93
EXPRESSION (lp_sample_cnt_clr || cfg_fsm_rst_i || trigger_h2l)
--------1-------- ------2------ -----3-----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T2,T4,T5 |
| 0 | 1 | 0 | Covered | T12,T13,T15 |
| 1 | 0 | 0 | Covered | T7,T8,T13 |
LINE 100
EXPRESSION (np_sample_cnt_en ? ((np_sample_cnt_q + 1'b1)) : np_sample_cnt_q)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T8,T12 |
LINE 106
EXPRESSION (np_sample_cnt_clr || cfg_fsm_rst_i || trigger_h2l)
--------1-------- ------2------ -----3-----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T2,T4,T5 |
| 0 | 1 | 0 | Covered | T12,T13,T15 |
| 1 | 0 | 0 | Covered | T2,T4,T10 |
LINE 113
EXPRESSION (wakeup_timer_cnt_en ? ((wakeup_timer_cnt_q + 1'b1)) : wakeup_timer_cnt_q)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T13 |
LINE 120
EXPRESSION (wakeup_timer_cnt_clr || cfg_fsm_rst_i || trigger_h2l)
----------1--------- ------2------ -----3-----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T2,T4,T5 |
| 0 | 1 | 0 | Covered | T12,T13,T15 |
| 1 | 0 | 0 | Covered | T7,T8,T13 |
LINE 127
EXPRESSION ((fsm_state_q == ONEST_0) || (fsm_state_q == LP_0) || (fsm_state_q == NP_0))
------------1----------- ----------2---------- ----------3----------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T2,T3,T4 |
| 0 | 1 | 0 | Covered | T7,T8,T13 |
| 1 | 0 | 0 | Covered | T2,T4,T5 |
LINE 127
SUB-EXPRESSION (fsm_state_q == ONEST_0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 127
SUB-EXPRESSION (fsm_state_q == LP_0)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T13 |
LINE 127
SUB-EXPRESSION (fsm_state_q == NP_0)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 128
EXPRESSION (fsm_chn0_sel && adc_d_val_i)
------1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T4 |
| 1 | 0 | Covered | T2,T3,T4 |
| 1 | 1 | Covered | T2,T3,T4 |
LINE 129
EXPRESSION (chn0_val_we_d ? adc_d_i : chn0_val_o)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 131
EXPRESSION ((fsm_state_q == ONEST_1) || (fsm_state_q == LP_1) || (fsm_state_q == NP_1))
------------1----------- ----------2---------- ----------3----------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T2,T3,T4 |
| 0 | 1 | 0 | Covered | T7,T8,T13 |
| 1 | 0 | 0 | Covered | T2,T4,T5 |
LINE 131
SUB-EXPRESSION (fsm_state_q == ONEST_1)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 131
SUB-EXPRESSION (fsm_state_q == LP_1)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T13 |
LINE 131
SUB-EXPRESSION (fsm_state_q == NP_1)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 132
EXPRESSION (fsm_chn1_sel && adc_d_val_i)
------1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T4 |
| 1 | 0 | Covered | T2,T3,T4 |
| 1 | 1 | Covered | T2,T3,T4 |
LINE 133
EXPRESSION (chn1_val_we_d ? adc_d_i : chn1_val_o)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 169
EXPRESSION (((|adc_ctrl_match_i)) & ((adc_ctrl_match_i == adc_ctrl_match_q) | ((~|adc_ctrl_match_q))))
----------1---------- --------------------------------2--------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T12,T14,T15 |
| 1 | 1 | Covered | T3,T8,T12 |
LINE 169
SUB-EXPRESSION ((adc_ctrl_match_i == adc_ctrl_match_q) | ((~|adc_ctrl_match_q)))
-------------------1------------------ -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T12,T13,T14 |
| 0 | 1 | Covered | T3,T8,T12 |
| 1 | 0 | Covered | T3,T8,T12 |
LINE 169
SUB-EXPRESSION (adc_ctrl_match_i == adc_ctrl_match_q)
-------------------1------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 179
EXPRESSION (trigger_h2l || cfg_fsm_rst_i)
-----1----- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T12,T13,T15 |
| 1 | 0 | Covered | T2,T4,T5 |
LINE 216
EXPRESSION (pwrup_timer_cnt_q != cfg_pwrup_time_i)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T4 |
| 1 | Covered | T2,T3,T4 |
LINE 219
EXPRESSION (pwrup_timer_cnt_q == cfg_pwrup_time_i)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T2,T3,T4 |
LINE 290
EXPRESSION (lp_sample_cnt_q == lp_sample_cnt_thresh)
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T14,T55,T56 |
| 1 | Covered | T8,T13,T14 |
LINE 300
EXPRESSION (wakeup_timer_cnt_q != cfg_wakeup_time_i)
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T7,T8,T13 |
| 1 | Covered | T7,T8,T13 |
LINE 303
EXPRESSION (wakeup_timer_cnt_q == cfg_wakeup_time_i)
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T7,T8,T13 |
LINE 310
EXPRESSION (pwrup_timer_cnt_q != cfg_pwrup_time_i)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T7,T8,T13 |
| 1 | Covered | T7,T8,T13 |
LINE 313
EXPRESSION (pwrup_timer_cnt_q == cfg_pwrup_time_i)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T7,T8,T13 |
LINE 363
EXPRESSION (np_sample_cnt_q == np_sample_cnt_thresh)
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T8,T12,T13 |
| 1 | Covered | T8,T12,T13 |
FSM Coverage for Module :
adc_ctrl_fsm
Summary for FSM :: fsm_state_q
| Total | Covered | Percent | |
| States |
17 |
17 |
100.00 |
(Not included in score) |
| Transitions |
37 |
37 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: fsm_state_q
| states | Line No. | Covered | Tests |
| LP_0 |
225 |
Covered |
T7,T8,T13 |
| LP_021 |
263 |
Covered |
T7,T8,T13 |
| LP_1 |
269 |
Covered |
T7,T8,T13 |
| LP_EVAL |
276 |
Covered |
T7,T8,T13 |
| LP_PWRUP |
304 |
Covered |
T7,T8,T13 |
| LP_SLP |
285 |
Covered |
T7,T8,T13 |
| NP_0 |
228 |
Covered |
T2,T3,T4 |
| NP_021 |
322 |
Covered |
T2,T3,T4 |
| NP_1 |
328 |
Covered |
T2,T3,T4 |
| NP_DONE |
364 |
Covered |
T8,T12,T13 |
| NP_EVAL |
335 |
Covered |
T2,T3,T4 |
| ONEST_0 |
222 |
Covered |
T2,T4,T5 |
| ONEST_021 |
236 |
Covered |
T2,T4,T5 |
| ONEST_1 |
242 |
Covered |
T2,T4,T5 |
| ONEST_DONE |
249 |
Covered |
T2,T4,T5 |
| PWRDN |
180 |
Covered |
T1,T2,T3 |
| PWRUP |
211 |
Covered |
T2,T3,T4 |
| transitions | Line No. | Covered | Tests |
| LP_0->LP_021 |
263 |
Covered |
T7,T8,T13 |
| LP_0->PWRDN |
180 |
Covered |
T8,T14,T15 |
| LP_021->LP_1 |
269 |
Covered |
T7,T8,T13 |
| LP_021->PWRDN |
180 |
Covered |
T55,T57,T58 |
| LP_1->LP_EVAL |
276 |
Covered |
T7,T8,T13 |
| LP_1->PWRDN |
180 |
Covered |
T56,T57,T59 |
| LP_EVAL->LP_SLP |
285 |
Covered |
T7,T8,T13 |
| LP_EVAL->NP_0 |
291 |
Covered |
T8,T13,T14 |
| LP_EVAL->PWRDN |
180 |
Covered |
T7,T14,T38 |
| LP_PWRUP->LP_0 |
315 |
Covered |
T7,T8,T13 |
| LP_PWRUP->PWRDN |
180 |
Covered |
T14,T20,T60 |
| LP_SLP->LP_PWRUP |
304 |
Covered |
T7,T8,T13 |
| LP_SLP->PWRDN |
180 |
Covered |
T7,T38,T39 |
| NP_0->NP_021 |
322 |
Covered |
T2,T3,T4 |
| NP_0->PWRDN |
180 |
Covered |
T2,T4,T10 |
| NP_021->NP_1 |
328 |
Covered |
T2,T3,T4 |
| NP_021->PWRDN |
180 |
Covered |
T49,T60,T56 |
| NP_1->NP_EVAL |
335 |
Covered |
T2,T3,T4 |
| NP_1->PWRDN |
180 |
Covered |
T3,T8,T49 |
| NP_DONE->NP_0 |
375 |
Covered |
T8,T12,T13 |
| NP_DONE->PWRDN |
180 |
Covered |
T56,T57,T61 |
| NP_EVAL->LP_0 |
355 |
Covered |
T13,T15,T20 |
| NP_EVAL->NP_0 |
357 |
Covered |
T2,T3,T4 |
| NP_EVAL->NP_DONE |
364 |
Covered |
T8,T12,T13 |
| NP_EVAL->PWRDN |
180 |
Covered |
T2,T3,T4 |
| ONEST_0->ONEST_021 |
236 |
Covered |
T2,T4,T5 |
| ONEST_0->PWRDN |
180 |
Covered |
T14,T40,T18 |
| ONEST_021->ONEST_1 |
242 |
Covered |
T2,T4,T5 |
| ONEST_021->PWRDN |
180 |
Covered |
T40,T60,T55 |
| ONEST_1->ONEST_DONE |
249 |
Covered |
T2,T4,T5 |
| ONEST_1->PWRDN |
180 |
Covered |
T55,T56,T57 |
| ONEST_DONE->PWRDN |
180 |
Covered |
T2,T4,T5 |
| PWRDN->PWRUP |
211 |
Covered |
T2,T3,T4 |
| PWRUP->LP_0 |
225 |
Covered |
T7,T8,T13 |
| PWRUP->NP_0 |
228 |
Covered |
T2,T3,T4 |
| PWRUP->ONEST_0 |
222 |
Covered |
T2,T4,T5 |
| PWRUP->PWRDN |
180 |
Covered |
T18,T48,T60 |
Branch Coverage for Module :
adc_ctrl_fsm
| Line No. | Total | Covered | Percent |
| Branches |
|
84 |
78 |
92.86 |
| TERNARY |
74 |
2 |
2 |
100.00 |
| TERNARY |
87 |
2 |
2 |
100.00 |
| TERNARY |
100 |
2 |
2 |
100.00 |
| TERNARY |
113 |
2 |
2 |
100.00 |
| TERNARY |
129 |
2 |
2 |
100.00 |
| TERNARY |
133 |
2 |
2 |
100.00 |
| IF |
61 |
3 |
3 |
100.00 |
| IF |
77 |
3 |
3 |
100.00 |
| IF |
90 |
3 |
3 |
100.00 |
| IF |
103 |
3 |
3 |
100.00 |
| IF |
117 |
3 |
3 |
100.00 |
| IF |
136 |
3 |
3 |
100.00 |
| IF |
157 |
4 |
4 |
100.00 |
| IF |
176 |
3 |
3 |
100.00 |
| CASE |
207 |
47 |
41 |
87.23 |
74 assign pwrup_timer_cnt_d = (pwrup_timer_cnt_en) ? pwrup_timer_cnt_q + 1'b1 : pwrup_timer_cnt_q;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T4 |
| 0 |
Covered |
T1,T2,T3 |
87 assign lp_sample_cnt_d = (lp_sample_cnt_en) ? lp_sample_cnt_q + 1'b1 : lp_sample_cnt_q;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T8,T13,T14 |
| 0 |
Covered |
T1,T2,T3 |
100 assign np_sample_cnt_d = (np_sample_cnt_en) ? np_sample_cnt_q + 1'b1 : np_sample_cnt_q;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T3,T8,T12 |
| 0 |
Covered |
T1,T2,T3 |
113 assign wakeup_timer_cnt_d = (wakeup_timer_cnt_en) ?
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T8,T13 |
| 0 |
Covered |
T1,T2,T3 |
129 assign chn0_val_d = (chn0_val_we_d) ? adc_d_i : chn0_val_o;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T4 |
| 0 |
Covered |
T1,T2,T3 |
133 assign chn1_val_d = (chn1_val_we_d) ? adc_d_i : chn1_val_o;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T4 |
| 0 |
Covered |
T1,T2,T3 |
61 if (!rst_aon_ni) begin
-1-
62 trigger_q <= 1'b0;
==>
63 end
64 else if (cfg_fsm_rst_i) begin
-2-
65 trigger_q <= 1'b0;
==>
66 end else begin
67 trigger_q <= cfg_adc_enable_i;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T12,T13,T15 |
| 0 |
0 |
Covered |
T1,T2,T3 |
77 if (!rst_aon_ni) begin
-1-
78 pwrup_timer_cnt_q <= '0;
==>
79 end
80 else if (pwrup_timer_cnt_clr || cfg_fsm_rst_i || trigger_h2l) begin
-2-
81 pwrup_timer_cnt_q <= '0;
==>
82 end else begin
83 pwrup_timer_cnt_q <= pwrup_timer_cnt_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T3,T4 |
| 0 |
0 |
Covered |
T1,T2,T3 |
90 if (!rst_aon_ni) begin
-1-
91 lp_sample_cnt_q <= '0;
==>
92 end
93 else if (lp_sample_cnt_clr || cfg_fsm_rst_i || trigger_h2l) begin
-2-
94 lp_sample_cnt_q <= '0;
==>
95 end else begin
96 lp_sample_cnt_q <= lp_sample_cnt_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T4,T5 |
| 0 |
0 |
Covered |
T1,T2,T3 |
103 if (!rst_aon_ni) begin
-1-
104 np_sample_cnt_q <= '0;
==>
105 end
106 else if (np_sample_cnt_clr || cfg_fsm_rst_i || trigger_h2l) begin
-2-
107 np_sample_cnt_q <= '0;
==>
108 end else begin
109 np_sample_cnt_q <= np_sample_cnt_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T4,T5 |
| 0 |
0 |
Covered |
T1,T2,T3 |
117 if (!rst_aon_ni) begin
-1-
118 wakeup_timer_cnt_q <= '0;
==>
119 end
120 else if (wakeup_timer_cnt_clr || cfg_fsm_rst_i || trigger_h2l) begin
-2-
121 wakeup_timer_cnt_q <= '0;
==>
122 end else begin
123 wakeup_timer_cnt_q <= wakeup_timer_cnt_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T4,T5 |
| 0 |
0 |
Covered |
T1,T2,T3 |
136 if (!rst_aon_ni) begin
-1-
137 chn0_val_we_o <= '0;
==>
138 chn1_val_we_o <= '0;
139 chn0_val_o <= '0;
140 chn1_val_o <= '0;
141 end
142 else if (cfg_fsm_rst_i) begin
-2-
143 chn0_val_we_o <= '0;
==>
144 chn1_val_we_o <= '0;
145 chn0_val_o <= '0;
146 chn1_val_o <= '0;
147 end else begin
148 chn0_val_we_o <= chn0_val_we_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T12,T13,T15 |
| 0 |
0 |
Covered |
T1,T2,T3 |
157 if (!rst_aon_ni) begin
-1-
158 adc_ctrl_match_q <= '0;
==>
159 end
160 else if (cfg_fsm_rst_i) begin
-2-
161 adc_ctrl_match_q <= '0;
==>
162 end
163 else if (ld_match) begin
-3-
164 adc_ctrl_match_q <= adc_ctrl_match_i;
==>
165 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T12,T13,T15 |
| 0 |
0 |
1 |
Covered |
T2,T3,T4 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
176 if (!rst_aon_ni) begin
-1-
177 fsm_state_q <= PWRDN;
==>
178 end
179 else if (trigger_h2l || cfg_fsm_rst_i) begin
-2-
180 fsm_state_q <= PWRDN;
==>
181 end else begin
182 fsm_state_q <= fsm_state_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T4,T5 |
| 0 |
0 |
Covered |
T1,T2,T3 |
207 unique case (fsm_state_q)
-1-
208 PWRDN: begin
209 adc_pd_o = 1'b1;
210 if (trigger_l2h) begin
-2-
211 fsm_state_d = PWRUP;
==>
212 end
MISSING_ELSE
==>
213 end
214
215 PWRUP: begin
216 if (pwrup_timer_cnt_q != cfg_pwrup_time_i) begin
-3-
217 pwrup_timer_cnt_en = 1'b1;
==>
218 end
219 else if (pwrup_timer_cnt_q == cfg_pwrup_time_i) begin
-4-
220 pwrup_timer_cnt_clr = 1'b1;
221 if (cfg_oneshot_mode_i) begin
-5-
222 fsm_state_d = ONEST_0;
==>
223 end
224 else if (cfg_lp_mode_i) begin
-6-
225 fsm_state_d = LP_0;
==>
226 end
227 else if (!cfg_lp_mode_i) begin
-7-
228 fsm_state_d = NP_0;
==>
229 end
MISSING_ELSE
==>
230 end
MISSING_ELSE
==>
231 end
232
233 ONEST_0: begin
234 adc_chn_sel_o = 2'b01;
235 if (adc_d_val_i) begin//sample chn0 value
-8-
236 fsm_state_d = ONEST_021;
==>
237 end
MISSING_ELSE
==>
238 end
239
240 ONEST_021: begin//transition between chn0 and chn1; adc_chn_sel_o=2'b0
241 if (!adc_d_val_i) begin
-9-
242 fsm_state_d = ONEST_1;
==>
243 end
MISSING_ELSE
==>
244 end
245
246 ONEST_1: begin
247 adc_chn_sel_o = 2'b10;
248 if (adc_d_val_i) begin//sample chn1 value
-10-
249 fsm_state_d = ONEST_DONE;
==>
250 end
MISSING_ELSE
==>
251 end
252
253 // delay done assertion by one cycle to match
254 // adc capture register timing
255 ONEST_DONE: begin
256 oneshot_done_o = 1'b1;
==>
257 fsm_state_d = PWRDN;
258 end
259
260 LP_0: begin
261 adc_chn_sel_o = 2'b01;
262 if (adc_d_val_i) begin//sample chn0 value
-11-
263 fsm_state_d = LP_021;
==>
264 end
MISSING_ELSE
==>
265 end
266
267 LP_021: begin//transition between chn0 and chn1; adc_chn_sel_o=2'b0
268 if (!adc_d_val_i) begin
-12-
269 fsm_state_d = LP_1;
==>
270 end
MISSING_ELSE
==>
271 end
272
273 LP_1: begin
274 adc_chn_sel_o = 2'b10;
275 if (adc_d_val_i) begin//sample chn1 value
-13-
276 fsm_state_d = LP_EVAL;
==>
277 end
MISSING_ELSE
==>
278 end
279
280 LP_EVAL: begin
281 // do not transition forward until handshake with ADC is complete
282 if (!adc_d_val_i) begin
-14-
283 ld_match = 1'b1;
284 if (!stay_match) begin
-15-
285 fsm_state_d = LP_SLP;
==>
286 lp_sample_cnt_clr = 1'b1;
287 end else if (lp_sample_cnt_q < lp_sample_cnt_thresh) begin
-16-
288 fsm_state_d = LP_SLP;
==>
289 lp_sample_cnt_en = 1'b1;
290 end else if (lp_sample_cnt_q == lp_sample_cnt_thresh) begin
-17-
291 fsm_state_d = NP_0;
==>
292 lp_sample_cnt_clr = 1'b1;
293 aon_fsm_trans_o = 1'b1;
294 end
MISSING_ELSE
==>
295 end
MISSING_ELSE
==>
296 end
297
298 LP_SLP: begin
299 adc_pd_o = 1'b1;
300 if (wakeup_timer_cnt_q != cfg_wakeup_time_i) begin
-18-
301 wakeup_timer_cnt_en = 1'b1;
==>
302 end
303 else if (wakeup_timer_cnt_q == cfg_wakeup_time_i) begin
-19-
304 fsm_state_d = LP_PWRUP;
==>
305 wakeup_timer_cnt_clr = 1'b1;
306 end
MISSING_ELSE
==>
307 end
308
309 LP_PWRUP: begin
310 if (pwrup_timer_cnt_q != cfg_pwrup_time_i) begin
-20-
311 pwrup_timer_cnt_en = 1'b1;
==>
312 end
313 else if (pwrup_timer_cnt_q == cfg_pwrup_time_i) begin
-21-
314 pwrup_timer_cnt_clr = 1'b1;
==>
315 fsm_state_d = LP_0;
316 end
MISSING_ELSE
==>
317 end
318
319 NP_0: begin
320 adc_chn_sel_o = 2'b01;
321 if (adc_d_val_i) begin//sample chn0 value
-22-
322 fsm_state_d = NP_021;
==>
323 end
MISSING_ELSE
==>
324 end
325
326 NP_021: begin//transition between chn0 and chn1; adc_chn_sel_o=2'b0
327 if (!adc_d_val_i) begin
-23-
328 fsm_state_d = NP_1;
==>
329 end
MISSING_ELSE
==>
330 end
331
332 NP_1: begin
333 adc_chn_sel_o = 2'b10;
334 if (adc_d_val_i) begin//sample chn1 value
-24-
335 fsm_state_d = NP_EVAL;
==>
336 end
MISSING_ELSE
==>
337 end
338
339 NP_EVAL: begin
340 // do not transition forward until handshake with ADC is complete
341 if (!adc_d_val_i) begin
-25-
342 ld_match = 1'b1;
343 // if there is no match in normal power mode, clear counter and begin sampling again.
344 // if there is no match and low power mode is enabled, clear counter and go back to LP_0.
345 //
346 // if there is a match, there are 3 conditions:
347 // 1. the sample count is less than the threshold -> still attempting to make a new match,
348 // keep sampling.
349 // 2. the sample count is equal to the threshold -> a new match has just been made, go to
350 // DONE.
351 // 3, the sample count is greater than the threshold -> this is a continued stable match,
352 // keep sampling.
353 if (!stay_match) begin
-26-
354 if (cfg_lp_mode_i) begin
-27-
355 fsm_state_d = LP_0;
==>
356 end else begin
357 fsm_state_d = NP_0;
==>
358 end
359 np_sample_cnt_clr = 1'b1;
360 end else if (np_sample_cnt_q < np_sample_cnt_thresh) begin
-28-
361 fsm_state_d = NP_0;
==>
362 np_sample_cnt_en = 1'b1;
363 end else if (np_sample_cnt_q == np_sample_cnt_thresh) begin
-29-
364 fsm_state_d = NP_DONE;
==>
365 np_sample_cnt_en = 1'b1;
366 end else if (np_sample_cnt_q > np_sample_cnt_thresh) begin
-30-
367 fsm_state_d = NP_0;
==>
368 end
MISSING_ELSE
==>
369 end
MISSING_ELSE
==>
370 end
371
372 // delay done assertion by one cycle to match with channel register timing
373 NP_DONE: begin
374 adc_ctrl_done_o = 1'b1;
==>
375 fsm_state_d = NP_0;
376 end
377
378 default: fsm_state_d = PWRDN;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | -16- | -17- | -18- | -19- | -20- | -21- | -22- | -23- | -24- | -25- | -26- | -27- | -28- | -29- | -30- | Status | Tests |
| PWRDN |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
| PWRDN |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| PWRUP |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
| PWRUP |
- |
0 |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
| PWRUP |
- |
0 |
1 |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T7,T8,T13 |
| PWRUP |
- |
0 |
1 |
0 |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
| PWRUP |
- |
0 |
1 |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| PWRUP |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| ONEST_0 |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
| ONEST_0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
| ONEST_021 |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
| ONEST_021 |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
| ONEST_1 |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
| ONEST_1 |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
| ONEST_DONE |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
| LP_0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T7,T8,T13 |
| LP_0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T7,T8,T13 |
| LP_021 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T7,T8,T13 |
| LP_021 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T7,T8,T13 |
| LP_1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T7,T8,T13 |
| LP_1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T7,T8,T13 |
| LP_EVAL |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T7,T13,T14 |
| LP_EVAL |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T8,T13,T14 |
| LP_EVAL |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T8,T13,T14 |
| LP_EVAL |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T14,T55,T56 |
| LP_EVAL |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T7,T8,T13 |
| LP_SLP |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T7,T8,T13 |
| LP_SLP |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T7,T8,T13 |
| LP_SLP |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| LP_PWRUP |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T7,T8,T13 |
| LP_PWRUP |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T7,T8,T13 |
| LP_PWRUP |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| NP_0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
| NP_0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
| NP_021 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
| NP_021 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
| NP_1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
| NP_1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
| NP_EVAL |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
1 |
- |
- |
- |
Covered |
T13,T15,T20 |
| NP_EVAL |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
0 |
- |
- |
- |
Covered |
T2,T4,T10 |
| NP_EVAL |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
1 |
- |
- |
Covered |
T3,T8,T12 |
| NP_EVAL |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
0 |
1 |
- |
Covered |
T8,T12,T13 |
| NP_EVAL |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
0 |
0 |
1 |
Covered |
T8,T12,T13 |
| NP_EVAL |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
0 |
0 |
0 |
Not Covered |
|
| NP_EVAL |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
| NP_DONE |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T8,T12,T13 |
| default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
Assert Coverage for Module :
adc_ctrl_fsm
Assertion Details
LpSampleCntCfg_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
31070228 |
30997539 |
0 |
0 |
| T1 |
82 |
1 |
0 |
0 |
| T2 |
1139 |
1053 |
0 |
0 |
| T3 |
308 |
136 |
0 |
0 |
| T4 |
749 |
676 |
0 |
0 |
| T5 |
1107 |
1028 |
0 |
0 |
| T6 |
1227 |
1139 |
0 |
0 |
| T7 |
7255 |
7183 |
0 |
0 |
| T8 |
63 |
1 |
0 |
0 |
| T21 |
83 |
1 |
0 |
0 |
| T22 |
90 |
1 |
0 |
0 |
NpCntClrMisMatch_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
31070228 |
152045 |
0 |
0 |
| T2 |
1139 |
10 |
0 |
0 |
| T3 |
308 |
0 |
0 |
0 |
| T4 |
749 |
7 |
0 |
0 |
| T5 |
1107 |
0 |
0 |
0 |
| T6 |
1227 |
0 |
0 |
0 |
| T7 |
7255 |
51 |
0 |
0 |
| T8 |
63 |
0 |
0 |
0 |
| T9 |
1129 |
0 |
0 |
0 |
| T10 |
0 |
3 |
0 |
0 |
| T12 |
0 |
1029 |
0 |
0 |
| T13 |
0 |
129 |
0 |
0 |
| T21 |
83 |
0 |
0 |
0 |
| T22 |
90 |
0 |
0 |
0 |
| T27 |
0 |
10 |
0 |
0 |
| T38 |
0 |
39 |
0 |
0 |
| T39 |
0 |
36 |
0 |
0 |
| T42 |
0 |
54 |
0 |
0 |
NpCntClrPwrDn_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
31070228 |
87916 |
0 |
0 |
| T1 |
82 |
1 |
0 |
0 |
| T2 |
1139 |
123 |
0 |
0 |
| T3 |
308 |
19 |
0 |
0 |
| T4 |
749 |
79 |
0 |
0 |
| T5 |
1107 |
241 |
0 |
0 |
| T6 |
1227 |
241 |
0 |
0 |
| T7 |
7255 |
78 |
0 |
0 |
| T8 |
63 |
1 |
0 |
0 |
| T21 |
83 |
1 |
0 |
0 |
| T22 |
90 |
1 |
0 |
0 |
NpSampleCntCfg_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
31070228 |
30997539 |
0 |
0 |
| T1 |
82 |
1 |
0 |
0 |
| T2 |
1139 |
1053 |
0 |
0 |
| T3 |
308 |
136 |
0 |
0 |
| T4 |
749 |
676 |
0 |
0 |
| T5 |
1107 |
1028 |
0 |
0 |
| T6 |
1227 |
1139 |
0 |
0 |
| T7 |
7255 |
7183 |
0 |
0 |
| T8 |
63 |
1 |
0 |
0 |
| T21 |
83 |
1 |
0 |
0 |
| T22 |
90 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 162 | 162 | 100.00 |
| CONT_ASSIGN | 58 | 1 | 1 | 100.00 |
| ALWAYS | 61 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 71 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| ALWAYS | 77 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
| ALWAYS | 90 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| ALWAYS | 103 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| ALWAYS | 117 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 127 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 129 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| ALWAYS | 136 | 14 | 14 | 100.00 |
| ALWAYS | 157 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 169 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 173 | 1 | 1 | 100.00 |
| ALWAYS | 176 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 186 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| ALWAYS | 190 | 95 | 95 | 100.00 |
57 fsm_state_e fsm_state_q, fsm_state_d;
58 1/1 assign aon_fsm_state_o = fsm_state_q;
Tests: T1 T2 T3
59
60 always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin
61 1/1 if (!rst_aon_ni) begin
Tests: T1 T2 T3
62 1/1 trigger_q <= 1'b0;
Tests: T1 T2 T3
63 end
64 1/1 else if (cfg_fsm_rst_i) begin
Tests: T1 T2 T3
65 1/1 trigger_q <= 1'b0;
Tests: T12 T13 T15
66 end else begin
67 1/1 trigger_q <= cfg_adc_enable_i;
Tests: T1 T2 T3
68 end
69 end
70
71 1/1 assign trigger_l2h = (trigger_q == 1'b0) && (cfg_adc_enable_i == 1'b1);
Tests: T1 T2 T3
72 1/1 assign trigger_h2l = (trigger_q == 1'b1) && (cfg_adc_enable_i == 1'b0);
Tests: T1 T2 T3
73
74 1/1 assign pwrup_timer_cnt_d = (pwrup_timer_cnt_en) ? pwrup_timer_cnt_q + 1'b1 : pwrup_timer_cnt_q;
Tests: T1 T2 T3
75
76 always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin
77 1/1 if (!rst_aon_ni) begin
Tests: T1 T2 T3
78 1/1 pwrup_timer_cnt_q <= '0;
Tests: T1 T2 T3
79 end
80 1/1 else if (pwrup_timer_cnt_clr || cfg_fsm_rst_i || trigger_h2l) begin
Tests: T1 T2 T3
81 1/1 pwrup_timer_cnt_q <= '0;
Tests: T2 T3 T4
82 end else begin
83 1/1 pwrup_timer_cnt_q <= pwrup_timer_cnt_d;
Tests: T1 T2 T3
84 end
85 end
86
87 1/1 assign lp_sample_cnt_d = (lp_sample_cnt_en) ? lp_sample_cnt_q + 1'b1 : lp_sample_cnt_q;
Tests: T1 T2 T3
88
89 always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin
90 1/1 if (!rst_aon_ni) begin
Tests: T1 T2 T3
91 1/1 lp_sample_cnt_q <= '0;
Tests: T1 T2 T3
92 end
93 1/1 else if (lp_sample_cnt_clr || cfg_fsm_rst_i || trigger_h2l) begin
Tests: T1 T2 T3
94 1/1 lp_sample_cnt_q <= '0;
Tests: T2 T4 T5
95 end else begin
96 1/1 lp_sample_cnt_q <= lp_sample_cnt_d;
Tests: T1 T2 T3
97 end
98 end
99
100 1/1 assign np_sample_cnt_d = (np_sample_cnt_en) ? np_sample_cnt_q + 1'b1 : np_sample_cnt_q;
Tests: T1 T2 T3
101
102 always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin
103 1/1 if (!rst_aon_ni) begin
Tests: T1 T2 T3
104 1/1 np_sample_cnt_q <= '0;
Tests: T1 T2 T3
105 end
106 1/1 else if (np_sample_cnt_clr || cfg_fsm_rst_i || trigger_h2l) begin
Tests: T1 T2 T3
107 1/1 np_sample_cnt_q <= '0;
Tests: T2 T4 T5
108 end else begin
109 1/1 np_sample_cnt_q <= np_sample_cnt_d;
Tests: T1 T2 T3
110 end
111 end
112
113 1/1 assign wakeup_timer_cnt_d = (wakeup_timer_cnt_en) ?
Tests: T1 T2 T3
114 wakeup_timer_cnt_q + 1'b1 : wakeup_timer_cnt_q;
115
116 always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin
117 1/1 if (!rst_aon_ni) begin
Tests: T1 T2 T3
118 1/1 wakeup_timer_cnt_q <= '0;
Tests: T1 T2 T3
119 end
120 1/1 else if (wakeup_timer_cnt_clr || cfg_fsm_rst_i || trigger_h2l) begin
Tests: T1 T2 T3
121 1/1 wakeup_timer_cnt_q <= '0;
Tests: T2 T4 T5
122 end else begin
123 1/1 wakeup_timer_cnt_q <= wakeup_timer_cnt_d;
Tests: T1 T2 T3
124 end
125 end
126
127 1/1 assign fsm_chn0_sel = (fsm_state_q == ONEST_0) || (fsm_state_q == LP_0) || (fsm_state_q == NP_0);
Tests: T1 T2 T3
128 1/1 assign chn0_val_we_d = fsm_chn0_sel && adc_d_val_i;//adc_d_val_i is a valid pulse
Tests: T1 T2 T3
129 1/1 assign chn0_val_d = (chn0_val_we_d) ? adc_d_i : chn0_val_o;
Tests: T1 T2 T3
130
131 1/1 assign fsm_chn1_sel = (fsm_state_q == ONEST_1) || (fsm_state_q == LP_1) || (fsm_state_q == NP_1);
Tests: T1 T2 T3
132 1/1 assign chn1_val_we_d = fsm_chn1_sel && adc_d_val_i;
Tests: T1 T2 T3
133 1/1 assign chn1_val_d = (chn1_val_we_d) ? adc_d_i : chn1_val_o;
Tests: T1 T2 T3
134
135 always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin
136 1/1 if (!rst_aon_ni) begin
Tests: T1 T2 T3
137 1/1 chn0_val_we_o <= '0;
Tests: T1 T2 T3
138 1/1 chn1_val_we_o <= '0;
Tests: T1 T2 T3
139 1/1 chn0_val_o <= '0;
Tests: T1 T2 T3
140 1/1 chn1_val_o <= '0;
Tests: T1 T2 T3
141 end
142 1/1 else if (cfg_fsm_rst_i) begin
Tests: T1 T2 T3
143 1/1 chn0_val_we_o <= '0;
Tests: T12 T13 T15
144 1/1 chn1_val_we_o <= '0;
Tests: T12 T13 T15
145 1/1 chn0_val_o <= '0;
Tests: T12 T13 T15
146 1/1 chn1_val_o <= '0;
Tests: T12 T13 T15
147 end else begin
148 1/1 chn0_val_we_o <= chn0_val_we_d;
Tests: T1 T2 T3
149 1/1 chn1_val_we_o <= chn1_val_we_d;
Tests: T1 T2 T3
150 1/1 chn0_val_o <= chn0_val_d;
Tests: T1 T2 T3
151 1/1 chn1_val_o <= chn1_val_d;
Tests: T1 T2 T3
152 end
153 end
154
155 logic ld_match;
156 always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin
157 1/1 if (!rst_aon_ni) begin
Tests: T1 T2 T3
158 1/1 adc_ctrl_match_q <= '0;
Tests: T1 T2 T3
159 end
160 1/1 else if (cfg_fsm_rst_i) begin
Tests: T1 T2 T3
161 1/1 adc_ctrl_match_q <= '0;
Tests: T12 T13 T15
162 end
163 1/1 else if (ld_match) begin
Tests: T1 T2 T3
164 1/1 adc_ctrl_match_q <= adc_ctrl_match_i;
Tests: T2 T3 T4
165 end
MISSING_ELSE
166 end
167
168 logic np_match;
169 1/1 assign np_match = |adc_ctrl_match_i & // if current match is non-zero
Tests: T1 T2 T3
170 ((adc_ctrl_match_i == adc_ctrl_match_q) | // match if same as previous match
171 ~|adc_ctrl_match_q); // or match if previous match was zero
172
173 1/1 assign stay_match = np_match;
Tests: T1 T2 T3
174
175 always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin
176 1/1 if (!rst_aon_ni) begin
Tests: T1 T2 T3
177 1/1 fsm_state_q <= PWRDN;
Tests: T1 T2 T3
178 end
179 1/1 else if (trigger_h2l || cfg_fsm_rst_i) begin
Tests: T1 T2 T3
180 1/1 fsm_state_q <= PWRDN;
Tests: T2 T4 T5
181 end else begin
182 1/1 fsm_state_q <= fsm_state_d;
Tests: T1 T2 T3
183 end
184 end
185
186 1/1 assign lp_sample_cnt_thresh = cfg_lp_sample_cnt_i - 1'b1;
Tests: T1 T2 T3
187 1/1 assign np_sample_cnt_thresh = cfg_np_sample_cnt_i - 1'b1;
Tests: T1 T2 T3
188
189 always_comb begin: adc_fsm
190 1/1 fsm_state_d = fsm_state_q;
Tests: T1 T2 T3
191 //outputs
192 1/1 adc_chn_sel_o = 2'b0;
Tests: T1 T2 T3
193 1/1 adc_pd_o = 1'b0;//default value
Tests: T1 T2 T3
194 1/1 pwrup_timer_cnt_clr = 1'b0;
Tests: T1 T2 T3
195 1/1 pwrup_timer_cnt_en = 1'b0;
Tests: T1 T2 T3
196 1/1 lp_sample_cnt_clr = 1'b0;
Tests: T1 T2 T3
197 1/1 lp_sample_cnt_en = 1'b0;
Tests: T1 T2 T3
198 1/1 wakeup_timer_cnt_clr = 1'b0;
Tests: T1 T2 T3
199 1/1 wakeup_timer_cnt_en = 1'b0;
Tests: T1 T2 T3
200 1/1 np_sample_cnt_clr = 1'b0;
Tests: T1 T2 T3
201 1/1 np_sample_cnt_en = 1'b0;
Tests: T1 T2 T3
202 1/1 adc_ctrl_done_o = 1'b0;
Tests: T1 T2 T3
203 1/1 oneshot_done_o = 1'b0;
Tests: T1 T2 T3
204 1/1 ld_match = 1'b0;
Tests: T1 T2 T3
205 1/1 aon_fsm_trans_o = 1'b0;
Tests: T1 T2 T3
206
207 1/1 unique case (fsm_state_q)
Tests: T1 T2 T3
208 PWRDN: begin
209 1/1 adc_pd_o = 1'b1;
Tests: T1 T2 T3
210 1/1 if (trigger_l2h) begin
Tests: T1 T2 T3
211 1/1 fsm_state_d = PWRUP;
Tests: T2 T3 T4
212 end
MISSING_ELSE
213 end
214
215 PWRUP: begin
216 1/1 if (pwrup_timer_cnt_q != cfg_pwrup_time_i) begin
Tests: T2 T3 T4
217 1/1 pwrup_timer_cnt_en = 1'b1;
Tests: T2 T3 T4
218 end
219 1/1 else if (pwrup_timer_cnt_q == cfg_pwrup_time_i) begin
Tests: T2 T3 T4
220 1/1 pwrup_timer_cnt_clr = 1'b1;
Tests: T2 T3 T4
221 1/1 if (cfg_oneshot_mode_i) begin
Tests: T2 T3 T4
222 1/1 fsm_state_d = ONEST_0;
Tests: T2 T4 T5
223 end
224 1/1 else if (cfg_lp_mode_i) begin
Tests: T2 T3 T4
225 1/1 fsm_state_d = LP_0;
Tests: T7 T8 T13
226 end
227 1/1 else if (!cfg_lp_mode_i) begin
Tests: T2 T3 T4
228 1/1 fsm_state_d = NP_0;
Tests: T2 T3 T4
229 end
==> MISSING_ELSE
230 end
==> MISSING_ELSE
231 end
232
233 ONEST_0: begin
234 1/1 adc_chn_sel_o = 2'b01;
Tests: T2 T4 T5
235 1/1 if (adc_d_val_i) begin//sample chn0 value
Tests: T2 T4 T5
236 1/1 fsm_state_d = ONEST_021;
Tests: T2 T4 T5
237 end
MISSING_ELSE
238 end
239
240 ONEST_021: begin//transition between chn0 and chn1; adc_chn_sel_o=2'b0
241 1/1 if (!adc_d_val_i) begin
Tests: T2 T4 T5
242 1/1 fsm_state_d = ONEST_1;
Tests: T2 T4 T5
243 end
MISSING_ELSE
244 end
245
246 ONEST_1: begin
247 1/1 adc_chn_sel_o = 2'b10;
Tests: T2 T4 T5
248 1/1 if (adc_d_val_i) begin//sample chn1 value
Tests: T2 T4 T5
249 1/1 fsm_state_d = ONEST_DONE;
Tests: T2 T4 T5
250 end
MISSING_ELSE
251 end
252
253 // delay done assertion by one cycle to match
254 // adc capture register timing
255 ONEST_DONE: begin
256 1/1 oneshot_done_o = 1'b1;
Tests: T2 T4 T5
257 1/1 fsm_state_d = PWRDN;
Tests: T2 T4 T5
258 end
259
260 LP_0: begin
261 1/1 adc_chn_sel_o = 2'b01;
Tests: T7 T8 T13
262 1/1 if (adc_d_val_i) begin//sample chn0 value
Tests: T7 T8 T13
263 1/1 fsm_state_d = LP_021;
Tests: T7 T8 T13
264 end
MISSING_ELSE
265 end
266
267 LP_021: begin//transition between chn0 and chn1; adc_chn_sel_o=2'b0
268 1/1 if (!adc_d_val_i) begin
Tests: T7 T8 T13
269 1/1 fsm_state_d = LP_1;
Tests: T7 T8 T13
270 end
MISSING_ELSE
271 end
272
273 LP_1: begin
274 1/1 adc_chn_sel_o = 2'b10;
Tests: T7 T8 T13
275 1/1 if (adc_d_val_i) begin//sample chn1 value
Tests: T7 T8 T13
276 1/1 fsm_state_d = LP_EVAL;
Tests: T7 T8 T13
277 end
MISSING_ELSE
278 end
279
280 LP_EVAL: begin
281 // do not transition forward until handshake with ADC is complete
282 1/1 if (!adc_d_val_i) begin
Tests: T7 T8 T13
283 1/1 ld_match = 1'b1;
Tests: T7 T8 T13
284 1/1 if (!stay_match) begin
Tests: T7 T8 T13
285 1/1 fsm_state_d = LP_SLP;
Tests: T7 T13 T14
286 1/1 lp_sample_cnt_clr = 1'b1;
Tests: T7 T13 T14
287 1/1 end else if (lp_sample_cnt_q < lp_sample_cnt_thresh) begin
Tests: T8 T13 T14
288 1/1 fsm_state_d = LP_SLP;
Tests: T8 T13 T14
289 1/1 lp_sample_cnt_en = 1'b1;
Tests: T8 T13 T14
290 1/1 end else if (lp_sample_cnt_q == lp_sample_cnt_thresh) begin
Tests: T8 T13 T14
291 1/1 fsm_state_d = NP_0;
Tests: T8 T13 T14
292 1/1 lp_sample_cnt_clr = 1'b1;
Tests: T8 T13 T14
293 1/1 aon_fsm_trans_o = 1'b1;
Tests: T8 T13 T14
294 end
MISSING_ELSE
295 end
MISSING_ELSE
296 end
297
298 LP_SLP: begin
299 1/1 adc_pd_o = 1'b1;
Tests: T7 T8 T13
300 1/1 if (wakeup_timer_cnt_q != cfg_wakeup_time_i) begin
Tests: T7 T8 T13
301 1/1 wakeup_timer_cnt_en = 1'b1;
Tests: T7 T8 T13
302 end
303 1/1 else if (wakeup_timer_cnt_q == cfg_wakeup_time_i) begin
Tests: T7 T8 T13
304 1/1 fsm_state_d = LP_PWRUP;
Tests: T7 T8 T13
305 1/1 wakeup_timer_cnt_clr = 1'b1;
Tests: T7 T8 T13
306 end
==> MISSING_ELSE
307 end
308
309 LP_PWRUP: begin
310 1/1 if (pwrup_timer_cnt_q != cfg_pwrup_time_i) begin
Tests: T7 T8 T13
311 1/1 pwrup_timer_cnt_en = 1'b1;
Tests: T7 T8 T13
312 end
313 1/1 else if (pwrup_timer_cnt_q == cfg_pwrup_time_i) begin
Tests: T7 T8 T13
314 1/1 pwrup_timer_cnt_clr = 1'b1;
Tests: T7 T8 T13
315 1/1 fsm_state_d = LP_0;
Tests: T7 T8 T13
316 end
==> MISSING_ELSE
317 end
318
319 NP_0: begin
320 1/1 adc_chn_sel_o = 2'b01;
Tests: T2 T3 T4
321 1/1 if (adc_d_val_i) begin//sample chn0 value
Tests: T2 T3 T4
322 1/1 fsm_state_d = NP_021;
Tests: T2 T3 T4
323 end
MISSING_ELSE
324 end
325
326 NP_021: begin//transition between chn0 and chn1; adc_chn_sel_o=2'b0
327 1/1 if (!adc_d_val_i) begin
Tests: T2 T3 T4
328 1/1 fsm_state_d = NP_1;
Tests: T2 T3 T4
329 end
MISSING_ELSE
330 end
331
332 NP_1: begin
333 1/1 adc_chn_sel_o = 2'b10;
Tests: T2 T3 T4
334 1/1 if (adc_d_val_i) begin//sample chn1 value
Tests: T2 T3 T4
335 1/1 fsm_state_d = NP_EVAL;
Tests: T2 T3 T4
336 end
MISSING_ELSE
337 end
338
339 NP_EVAL: begin
340 // do not transition forward until handshake with ADC is complete
341 1/1 if (!adc_d_val_i) begin
Tests: T2 T3 T4
342 1/1 ld_match = 1'b1;
Tests: T2 T3 T4
343 // if there is no match in normal power mode, clear counter and begin sampling again.
344 // if there is no match and low power mode is enabled, clear counter and go back to LP_0.
345 //
346 // if there is a match, there are 3 conditions:
347 // 1. the sample count is less than the threshold -> still attempting to make a new match,
348 // keep sampling.
349 // 2. the sample count is equal to the threshold -> a new match has just been made, go to
350 // DONE.
351 // 3, the sample count is greater than the threshold -> this is a continued stable match,
352 // keep sampling.
353 1/1 if (!stay_match) begin
Tests: T2 T3 T4
354 1/1 if (cfg_lp_mode_i) begin
Tests: T2 T4 T10
355 1/1 fsm_state_d = LP_0;
Tests: T13 T15 T20
356 end else begin
357 1/1 fsm_state_d = NP_0;
Tests: T2 T4 T10
358 end
359 1/1 np_sample_cnt_clr = 1'b1;
Tests: T2 T4 T10
360 1/1 end else if (np_sample_cnt_q < np_sample_cnt_thresh) begin
Tests: T3 T8 T12
361 1/1 fsm_state_d = NP_0;
Tests: T3 T8 T12
362 1/1 np_sample_cnt_en = 1'b1;
Tests: T3 T8 T12
363 1/1 end else if (np_sample_cnt_q == np_sample_cnt_thresh) begin
Tests: T8 T12 T13
364 1/1 fsm_state_d = NP_DONE;
Tests: T8 T12 T13
365 1/1 np_sample_cnt_en = 1'b1;
Tests: T8 T12 T13
366 1/1 end else if (np_sample_cnt_q > np_sample_cnt_thresh) begin
Tests: T8 T12 T13
367 1/1 fsm_state_d = NP_0;
Tests: T8 T12 T13
368 end
==> MISSING_ELSE
369 end
MISSING_ELSE
370 end
371
372 // delay done assertion by one cycle to match with channel register timing
373 NP_DONE: begin
374 1/1 adc_ctrl_done_o = 1'b1;
Tests: T8 T12 T13
375 1/1 fsm_state_d = NP_0;
Tests: T8 T12 T13
376 end
377
378 default: fsm_state_d = PWRDN;
Cond Coverage for Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm
| Total | Covered | Percent |
|---|
| Conditions | 92 | 92 | 100.00 |
| Logical | 92 | 92 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 71
EXPRESSION ((trigger_q == 1'b0) && (cfg_adc_enable_i == 1'b1))
---------1--------- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T4 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T4 |
LINE 71
SUB-EXPRESSION (trigger_q == 1'b0)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (cfg_adc_enable_i == 1'b1)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 72
EXPRESSION ((trigger_q == 1'b1) && (cfg_adc_enable_i == 1'b0))
---------1--------- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T4 |
| 1 | 1 | Covered | T2,T4,T5 |
LINE 72
SUB-EXPRESSION (trigger_q == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 72
SUB-EXPRESSION (cfg_adc_enable_i == 1'b0)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 74
EXPRESSION (pwrup_timer_cnt_en ? ((pwrup_timer_cnt_q + 1'b1)) : pwrup_timer_cnt_q)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 80
EXPRESSION (pwrup_timer_cnt_clr || cfg_fsm_rst_i || trigger_h2l)
---------1--------- ------2------ -----3-----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T2,T4,T5 |
| 0 | 1 | 0 | Covered | T12,T13,T15 |
| 1 | 0 | 0 | Covered | T2,T3,T4 |
LINE 87
EXPRESSION (lp_sample_cnt_en ? ((lp_sample_cnt_q + 1'b1)) : lp_sample_cnt_q)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T8,T13,T14 |
LINE 93
EXPRESSION (lp_sample_cnt_clr || cfg_fsm_rst_i || trigger_h2l)
--------1-------- ------2------ -----3-----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T2,T4,T5 |
| 0 | 1 | 0 | Covered | T12,T13,T15 |
| 1 | 0 | 0 | Covered | T7,T8,T13 |
LINE 100
EXPRESSION (np_sample_cnt_en ? ((np_sample_cnt_q + 1'b1)) : np_sample_cnt_q)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T8,T12 |
LINE 106
EXPRESSION (np_sample_cnt_clr || cfg_fsm_rst_i || trigger_h2l)
--------1-------- ------2------ -----3-----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T2,T4,T5 |
| 0 | 1 | 0 | Covered | T12,T13,T15 |
| 1 | 0 | 0 | Covered | T2,T4,T10 |
LINE 113
EXPRESSION (wakeup_timer_cnt_en ? ((wakeup_timer_cnt_q + 1'b1)) : wakeup_timer_cnt_q)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T13 |
LINE 120
EXPRESSION (wakeup_timer_cnt_clr || cfg_fsm_rst_i || trigger_h2l)
----------1--------- ------2------ -----3-----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T2,T4,T5 |
| 0 | 1 | 0 | Covered | T12,T13,T15 |
| 1 | 0 | 0 | Covered | T7,T8,T13 |
LINE 127
EXPRESSION ((fsm_state_q == ONEST_0) || (fsm_state_q == LP_0) || (fsm_state_q == NP_0))
------------1----------- ----------2---------- ----------3----------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T2,T3,T4 |
| 0 | 1 | 0 | Covered | T7,T8,T13 |
| 1 | 0 | 0 | Covered | T2,T4,T5 |
LINE 127
SUB-EXPRESSION (fsm_state_q == ONEST_0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 127
SUB-EXPRESSION (fsm_state_q == LP_0)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T13 |
LINE 127
SUB-EXPRESSION (fsm_state_q == NP_0)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 128
EXPRESSION (fsm_chn0_sel && adc_d_val_i)
------1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T4 |
| 1 | 0 | Covered | T2,T3,T4 |
| 1 | 1 | Covered | T2,T3,T4 |
LINE 129
EXPRESSION (chn0_val_we_d ? adc_d_i : chn0_val_o)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 131
EXPRESSION ((fsm_state_q == ONEST_1) || (fsm_state_q == LP_1) || (fsm_state_q == NP_1))
------------1----------- ----------2---------- ----------3----------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T2,T3,T4 |
| 0 | 1 | 0 | Covered | T7,T8,T13 |
| 1 | 0 | 0 | Covered | T2,T4,T5 |
LINE 131
SUB-EXPRESSION (fsm_state_q == ONEST_1)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 131
SUB-EXPRESSION (fsm_state_q == LP_1)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T13 |
LINE 131
SUB-EXPRESSION (fsm_state_q == NP_1)
----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 132
EXPRESSION (fsm_chn1_sel && adc_d_val_i)
------1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T4 |
| 1 | 0 | Covered | T2,T3,T4 |
| 1 | 1 | Covered | T2,T3,T4 |
LINE 133
EXPRESSION (chn1_val_we_d ? adc_d_i : chn1_val_o)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 169
EXPRESSION (((|adc_ctrl_match_i)) & ((adc_ctrl_match_i == adc_ctrl_match_q) | ((~|adc_ctrl_match_q))))
----------1---------- --------------------------------2--------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T12,T14,T15 |
| 1 | 1 | Covered | T3,T8,T12 |
LINE 169
SUB-EXPRESSION ((adc_ctrl_match_i == adc_ctrl_match_q) | ((~|adc_ctrl_match_q)))
-------------------1------------------ -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T12,T13,T14 |
| 0 | 1 | Covered | T3,T8,T12 |
| 1 | 0 | Covered | T3,T8,T12 |
LINE 169
SUB-EXPRESSION (adc_ctrl_match_i == adc_ctrl_match_q)
-------------------1------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 179
EXPRESSION (trigger_h2l || cfg_fsm_rst_i)
-----1----- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T12,T13,T15 |
| 1 | 0 | Covered | T2,T4,T5 |
LINE 216
EXPRESSION (pwrup_timer_cnt_q != cfg_pwrup_time_i)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T4 |
| 1 | Covered | T2,T3,T4 |
LINE 219
EXPRESSION (pwrup_timer_cnt_q == cfg_pwrup_time_i)
-------------------1-------------------
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Excluded | |
VC_COV_UNR |
| 1 | Covered | T2,T3,T4 |
LINE 290
EXPRESSION (lp_sample_cnt_q == lp_sample_cnt_thresh)
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T14,T55,T56 |
| 1 | Covered | T8,T13,T14 |
LINE 300
EXPRESSION (wakeup_timer_cnt_q != cfg_wakeup_time_i)
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T7,T8,T13 |
| 1 | Covered | T7,T8,T13 |
LINE 303
EXPRESSION (wakeup_timer_cnt_q == cfg_wakeup_time_i)
--------------------1--------------------
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Excluded | |
VC_COV_UNR |
| 1 | Covered | T7,T8,T13 |
LINE 310
EXPRESSION (pwrup_timer_cnt_q != cfg_pwrup_time_i)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T7,T8,T13 |
| 1 | Covered | T7,T8,T13 |
LINE 313
EXPRESSION (pwrup_timer_cnt_q == cfg_pwrup_time_i)
-------------------1-------------------
| -1- | Status | Tests | Exclude Annotation |
|---|
| 0 | Excluded | |
VC_COV_UNR |
| 1 | Covered | T7,T8,T13 |
LINE 363
EXPRESSION (np_sample_cnt_q == np_sample_cnt_thresh)
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T8,T12,T13 |
| 1 | Covered | T8,T12,T13 |
FSM Coverage for Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm
Summary for FSM :: fsm_state_q
| Total | Covered | Percent | |
| States |
17 |
17 |
100.00 |
(Not included in score) |
| Transitions |
37 |
37 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: fsm_state_q
| states | Line No. | Covered | Tests |
| LP_0 |
225 |
Covered |
T7,T8,T13 |
| LP_021 |
263 |
Covered |
T7,T8,T13 |
| LP_1 |
269 |
Covered |
T7,T8,T13 |
| LP_EVAL |
276 |
Covered |
T7,T8,T13 |
| LP_PWRUP |
304 |
Covered |
T7,T8,T13 |
| LP_SLP |
285 |
Covered |
T7,T8,T13 |
| NP_0 |
228 |
Covered |
T2,T3,T4 |
| NP_021 |
322 |
Covered |
T2,T3,T4 |
| NP_1 |
328 |
Covered |
T2,T3,T4 |
| NP_DONE |
364 |
Covered |
T8,T12,T13 |
| NP_EVAL |
335 |
Covered |
T2,T3,T4 |
| ONEST_0 |
222 |
Covered |
T2,T4,T5 |
| ONEST_021 |
236 |
Covered |
T2,T4,T5 |
| ONEST_1 |
242 |
Covered |
T2,T4,T5 |
| ONEST_DONE |
249 |
Covered |
T2,T4,T5 |
| PWRDN |
180 |
Covered |
T1,T2,T3 |
| PWRUP |
211 |
Covered |
T2,T3,T4 |
| transitions | Line No. | Covered | Tests |
| LP_0->LP_021 |
263 |
Covered |
T7,T8,T13 |
| LP_0->PWRDN |
180 |
Covered |
T8,T14,T15 |
| LP_021->LP_1 |
269 |
Covered |
T7,T8,T13 |
| LP_021->PWRDN |
180 |
Covered |
T55,T57,T58 |
| LP_1->LP_EVAL |
276 |
Covered |
T7,T8,T13 |
| LP_1->PWRDN |
180 |
Covered |
T56,T57,T59 |
| LP_EVAL->LP_SLP |
285 |
Covered |
T7,T8,T13 |
| LP_EVAL->NP_0 |
291 |
Covered |
T8,T13,T14 |
| LP_EVAL->PWRDN |
180 |
Covered |
T7,T14,T38 |
| LP_PWRUP->LP_0 |
315 |
Covered |
T7,T8,T13 |
| LP_PWRUP->PWRDN |
180 |
Covered |
T14,T20,T60 |
| LP_SLP->LP_PWRUP |
304 |
Covered |
T7,T8,T13 |
| LP_SLP->PWRDN |
180 |
Covered |
T7,T38,T39 |
| NP_0->NP_021 |
322 |
Covered |
T2,T3,T4 |
| NP_0->PWRDN |
180 |
Covered |
T2,T4,T10 |
| NP_021->NP_1 |
328 |
Covered |
T2,T3,T4 |
| NP_021->PWRDN |
180 |
Covered |
T49,T60,T56 |
| NP_1->NP_EVAL |
335 |
Covered |
T2,T3,T4 |
| NP_1->PWRDN |
180 |
Covered |
T3,T8,T49 |
| NP_DONE->NP_0 |
375 |
Covered |
T8,T12,T13 |
| NP_DONE->PWRDN |
180 |
Covered |
T56,T57,T61 |
| NP_EVAL->LP_0 |
355 |
Covered |
T13,T15,T20 |
| NP_EVAL->NP_0 |
357 |
Covered |
T2,T3,T4 |
| NP_EVAL->NP_DONE |
364 |
Covered |
T8,T12,T13 |
| NP_EVAL->PWRDN |
180 |
Covered |
T2,T3,T4 |
| ONEST_0->ONEST_021 |
236 |
Covered |
T2,T4,T5 |
| ONEST_0->PWRDN |
180 |
Covered |
T14,T40,T18 |
| ONEST_021->ONEST_1 |
242 |
Covered |
T2,T4,T5 |
| ONEST_021->PWRDN |
180 |
Covered |
T40,T60,T55 |
| ONEST_1->ONEST_DONE |
249 |
Covered |
T2,T4,T5 |
| ONEST_1->PWRDN |
180 |
Covered |
T55,T56,T57 |
| ONEST_DONE->PWRDN |
180 |
Covered |
T2,T4,T5 |
| PWRDN->PWRUP |
211 |
Covered |
T2,T3,T4 |
| PWRUP->LP_0 |
225 |
Covered |
T7,T8,T13 |
| PWRUP->NP_0 |
228 |
Covered |
T2,T3,T4 |
| PWRUP->ONEST_0 |
222 |
Covered |
T2,T4,T5 |
| PWRUP->PWRDN |
180 |
Covered |
T18,T48,T60 |
Branch Coverage for Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm
| Line No. | Total | Covered | Percent |
| Branches |
|
79 |
78 |
98.73 |
| TERNARY |
74 |
2 |
2 |
100.00 |
| TERNARY |
87 |
2 |
2 |
100.00 |
| TERNARY |
100 |
2 |
2 |
100.00 |
| TERNARY |
113 |
2 |
2 |
100.00 |
| TERNARY |
129 |
2 |
2 |
100.00 |
| TERNARY |
133 |
2 |
2 |
100.00 |
| IF |
61 |
3 |
3 |
100.00 |
| IF |
77 |
3 |
3 |
100.00 |
| IF |
90 |
3 |
3 |
100.00 |
| IF |
103 |
3 |
3 |
100.00 |
| IF |
117 |
3 |
3 |
100.00 |
| IF |
136 |
3 |
3 |
100.00 |
| IF |
157 |
4 |
4 |
100.00 |
| IF |
176 |
3 |
3 |
100.00 |
| CASE |
207 |
42 |
41 |
97.62 |
74 assign pwrup_timer_cnt_d = (pwrup_timer_cnt_en) ? pwrup_timer_cnt_q + 1'b1 : pwrup_timer_cnt_q;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T4 |
| 0 |
Covered |
T1,T2,T3 |
87 assign lp_sample_cnt_d = (lp_sample_cnt_en) ? lp_sample_cnt_q + 1'b1 : lp_sample_cnt_q;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T8,T13,T14 |
| 0 |
Covered |
T1,T2,T3 |
100 assign np_sample_cnt_d = (np_sample_cnt_en) ? np_sample_cnt_q + 1'b1 : np_sample_cnt_q;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T3,T8,T12 |
| 0 |
Covered |
T1,T2,T3 |
113 assign wakeup_timer_cnt_d = (wakeup_timer_cnt_en) ?
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T8,T13 |
| 0 |
Covered |
T1,T2,T3 |
129 assign chn0_val_d = (chn0_val_we_d) ? adc_d_i : chn0_val_o;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T4 |
| 0 |
Covered |
T1,T2,T3 |
133 assign chn1_val_d = (chn1_val_we_d) ? adc_d_i : chn1_val_o;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T4 |
| 0 |
Covered |
T1,T2,T3 |
61 if (!rst_aon_ni) begin
-1-
62 trigger_q <= 1'b0;
==>
63 end
64 else if (cfg_fsm_rst_i) begin
-2-
65 trigger_q <= 1'b0;
==>
66 end else begin
67 trigger_q <= cfg_adc_enable_i;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T12,T13,T15 |
| 0 |
0 |
Covered |
T1,T2,T3 |
77 if (!rst_aon_ni) begin
-1-
78 pwrup_timer_cnt_q <= '0;
==>
79 end
80 else if (pwrup_timer_cnt_clr || cfg_fsm_rst_i || trigger_h2l) begin
-2-
81 pwrup_timer_cnt_q <= '0;
==>
82 end else begin
83 pwrup_timer_cnt_q <= pwrup_timer_cnt_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T3,T4 |
| 0 |
0 |
Covered |
T1,T2,T3 |
90 if (!rst_aon_ni) begin
-1-
91 lp_sample_cnt_q <= '0;
==>
92 end
93 else if (lp_sample_cnt_clr || cfg_fsm_rst_i || trigger_h2l) begin
-2-
94 lp_sample_cnt_q <= '0;
==>
95 end else begin
96 lp_sample_cnt_q <= lp_sample_cnt_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T4,T5 |
| 0 |
0 |
Covered |
T1,T2,T3 |
103 if (!rst_aon_ni) begin
-1-
104 np_sample_cnt_q <= '0;
==>
105 end
106 else if (np_sample_cnt_clr || cfg_fsm_rst_i || trigger_h2l) begin
-2-
107 np_sample_cnt_q <= '0;
==>
108 end else begin
109 np_sample_cnt_q <= np_sample_cnt_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T4,T5 |
| 0 |
0 |
Covered |
T1,T2,T3 |
117 if (!rst_aon_ni) begin
-1-
118 wakeup_timer_cnt_q <= '0;
==>
119 end
120 else if (wakeup_timer_cnt_clr || cfg_fsm_rst_i || trigger_h2l) begin
-2-
121 wakeup_timer_cnt_q <= '0;
==>
122 end else begin
123 wakeup_timer_cnt_q <= wakeup_timer_cnt_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T4,T5 |
| 0 |
0 |
Covered |
T1,T2,T3 |
136 if (!rst_aon_ni) begin
-1-
137 chn0_val_we_o <= '0;
==>
138 chn1_val_we_o <= '0;
139 chn0_val_o <= '0;
140 chn1_val_o <= '0;
141 end
142 else if (cfg_fsm_rst_i) begin
-2-
143 chn0_val_we_o <= '0;
==>
144 chn1_val_we_o <= '0;
145 chn0_val_o <= '0;
146 chn1_val_o <= '0;
147 end else begin
148 chn0_val_we_o <= chn0_val_we_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T12,T13,T15 |
| 0 |
0 |
Covered |
T1,T2,T3 |
157 if (!rst_aon_ni) begin
-1-
158 adc_ctrl_match_q <= '0;
==>
159 end
160 else if (cfg_fsm_rst_i) begin
-2-
161 adc_ctrl_match_q <= '0;
==>
162 end
163 else if (ld_match) begin
-3-
164 adc_ctrl_match_q <= adc_ctrl_match_i;
==>
165 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T12,T13,T15 |
| 0 |
0 |
1 |
Covered |
T2,T3,T4 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
176 if (!rst_aon_ni) begin
-1-
177 fsm_state_q <= PWRDN;
==>
178 end
179 else if (trigger_h2l || cfg_fsm_rst_i) begin
-2-
180 fsm_state_q <= PWRDN;
==>
181 end else begin
182 fsm_state_q <= fsm_state_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T4,T5 |
| 0 |
0 |
Covered |
T1,T2,T3 |
207 unique case (fsm_state_q)
-1-
208 PWRDN: begin
209 adc_pd_o = 1'b1;
210 if (trigger_l2h) begin
-2-
211 fsm_state_d = PWRUP;
==>
212 end
MISSING_ELSE
==>
213 end
214
215 PWRUP: begin
216 if (pwrup_timer_cnt_q != cfg_pwrup_time_i) begin
-3-
217 pwrup_timer_cnt_en = 1'b1;
==>
218 end
219 else if (pwrup_timer_cnt_q == cfg_pwrup_time_i) begin
-4-
220 pwrup_timer_cnt_clr = 1'b1;
221 if (cfg_oneshot_mode_i) begin
-5-
222 fsm_state_d = ONEST_0;
==>
223 end
224 else if (cfg_lp_mode_i) begin
-6-
225 fsm_state_d = LP_0;
==>
226 end
227 else if (!cfg_lp_mode_i) begin
-7-
228 fsm_state_d = NP_0;
==>
229 end
MISSING_ELSE
==> (Excluded)
Exclude Annotation: VC_COV_UNR
230 end
MISSING_ELSE
==> (Excluded)
Exclude Annotation: VC_COV_UNR
231 end
232
233 ONEST_0: begin
234 adc_chn_sel_o = 2'b01;
235 if (adc_d_val_i) begin//sample chn0 value
-8-
236 fsm_state_d = ONEST_021;
==>
237 end
MISSING_ELSE
==>
238 end
239
240 ONEST_021: begin//transition between chn0 and chn1; adc_chn_sel_o=2'b0
241 if (!adc_d_val_i) begin
-9-
242 fsm_state_d = ONEST_1;
==>
243 end
MISSING_ELSE
==>
244 end
245
246 ONEST_1: begin
247 adc_chn_sel_o = 2'b10;
248 if (adc_d_val_i) begin//sample chn1 value
-10-
249 fsm_state_d = ONEST_DONE;
==>
250 end
MISSING_ELSE
==>
251 end
252
253 // delay done assertion by one cycle to match
254 // adc capture register timing
255 ONEST_DONE: begin
256 oneshot_done_o = 1'b1;
==>
257 fsm_state_d = PWRDN;
258 end
259
260 LP_0: begin
261 adc_chn_sel_o = 2'b01;
262 if (adc_d_val_i) begin//sample chn0 value
-11-
263 fsm_state_d = LP_021;
==>
264 end
MISSING_ELSE
==>
265 end
266
267 LP_021: begin//transition between chn0 and chn1; adc_chn_sel_o=2'b0
268 if (!adc_d_val_i) begin
-12-
269 fsm_state_d = LP_1;
==>
270 end
MISSING_ELSE
==>
271 end
272
273 LP_1: begin
274 adc_chn_sel_o = 2'b10;
275 if (adc_d_val_i) begin//sample chn1 value
-13-
276 fsm_state_d = LP_EVAL;
==>
277 end
MISSING_ELSE
==>
278 end
279
280 LP_EVAL: begin
281 // do not transition forward until handshake with ADC is complete
282 if (!adc_d_val_i) begin
-14-
283 ld_match = 1'b1;
284 if (!stay_match) begin
-15-
285 fsm_state_d = LP_SLP;
==>
286 lp_sample_cnt_clr = 1'b1;
287 end else if (lp_sample_cnt_q < lp_sample_cnt_thresh) begin
-16-
288 fsm_state_d = LP_SLP;
==>
289 lp_sample_cnt_en = 1'b1;
290 end else if (lp_sample_cnt_q == lp_sample_cnt_thresh) begin
-17-
291 fsm_state_d = NP_0;
==>
292 lp_sample_cnt_clr = 1'b1;
293 aon_fsm_trans_o = 1'b1;
294 end
MISSING_ELSE
==>
295 end
MISSING_ELSE
==>
296 end
297
298 LP_SLP: begin
299 adc_pd_o = 1'b1;
300 if (wakeup_timer_cnt_q != cfg_wakeup_time_i) begin
-18-
301 wakeup_timer_cnt_en = 1'b1;
==>
302 end
303 else if (wakeup_timer_cnt_q == cfg_wakeup_time_i) begin
-19-
304 fsm_state_d = LP_PWRUP;
==>
305 wakeup_timer_cnt_clr = 1'b1;
306 end
MISSING_ELSE
==> (Excluded)
Exclude Annotation: VC_COV_UNR
307 end
308
309 LP_PWRUP: begin
310 if (pwrup_timer_cnt_q != cfg_pwrup_time_i) begin
-20-
311 pwrup_timer_cnt_en = 1'b1;
==>
312 end
313 else if (pwrup_timer_cnt_q == cfg_pwrup_time_i) begin
-21-
314 pwrup_timer_cnt_clr = 1'b1;
==>
315 fsm_state_d = LP_0;
316 end
MISSING_ELSE
==> (Excluded)
Exclude Annotation: VC_COV_UNR
317 end
318
319 NP_0: begin
320 adc_chn_sel_o = 2'b01;
321 if (adc_d_val_i) begin//sample chn0 value
-22-
322 fsm_state_d = NP_021;
==>
323 end
MISSING_ELSE
==>
324 end
325
326 NP_021: begin//transition between chn0 and chn1; adc_chn_sel_o=2'b0
327 if (!adc_d_val_i) begin
-23-
328 fsm_state_d = NP_1;
==>
329 end
MISSING_ELSE
==>
330 end
331
332 NP_1: begin
333 adc_chn_sel_o = 2'b10;
334 if (adc_d_val_i) begin//sample chn1 value
-24-
335 fsm_state_d = NP_EVAL;
==>
336 end
MISSING_ELSE
==>
337 end
338
339 NP_EVAL: begin
340 // do not transition forward until handshake with ADC is complete
341 if (!adc_d_val_i) begin
-25-
342 ld_match = 1'b1;
343 // if there is no match in normal power mode, clear counter and begin sampling again.
344 // if there is no match and low power mode is enabled, clear counter and go back to LP_0.
345 //
346 // if there is a match, there are 3 conditions:
347 // 1. the sample count is less than the threshold -> still attempting to make a new match,
348 // keep sampling.
349 // 2. the sample count is equal to the threshold -> a new match has just been made, go to
350 // DONE.
351 // 3, the sample count is greater than the threshold -> this is a continued stable match,
352 // keep sampling.
353 if (!stay_match) begin
-26-
354 if (cfg_lp_mode_i) begin
-27-
355 fsm_state_d = LP_0;
==>
356 end else begin
357 fsm_state_d = NP_0;
==>
358 end
359 np_sample_cnt_clr = 1'b1;
360 end else if (np_sample_cnt_q < np_sample_cnt_thresh) begin
-28-
361 fsm_state_d = NP_0;
==>
362 np_sample_cnt_en = 1'b1;
363 end else if (np_sample_cnt_q == np_sample_cnt_thresh) begin
-29-
364 fsm_state_d = NP_DONE;
==>
365 np_sample_cnt_en = 1'b1;
366 end else if (np_sample_cnt_q > np_sample_cnt_thresh) begin
-30-
367 fsm_state_d = NP_0;
==>
368 end
MISSING_ELSE
==> (Excluded)
Exclude Annotation: VC_COV_UNR
369 end
MISSING_ELSE
==>
370 end
371
372 // delay done assertion by one cycle to match with channel register timing
373 NP_DONE: begin
374 adc_ctrl_done_o = 1'b1;
==>
375 fsm_state_d = NP_0;
376 end
377
378 default: fsm_state_d = PWRDN;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | -16- | -17- | -18- | -19- | -20- | -21- | -22- | -23- | -24- | -25- | -26- | -27- | -28- | -29- | -30- | Status | Tests | Exclude Annotation |
| PWRDN |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
|
| PWRDN |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| PWRUP |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
|
| PWRUP |
- |
0 |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
|
| PWRUP |
- |
0 |
1 |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T7,T8,T13 |
|
| PWRUP |
- |
0 |
1 |
0 |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
|
| PWRUP |
- |
0 |
1 |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
| PWRUP |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
| ONEST_0 |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
|
| ONEST_0 |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
|
| ONEST_021 |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
|
| ONEST_021 |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
|
| ONEST_1 |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
|
| ONEST_1 |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
|
| ONEST_DONE |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T4,T5 |
|
| LP_0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T7,T8,T13 |
|
| LP_0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T7,T8,T13 |
|
| LP_021 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T7,T8,T13 |
|
| LP_021 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T7,T8,T13 |
|
| LP_1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T7,T8,T13 |
|
| LP_1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T7,T8,T13 |
|
| LP_EVAL |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T7,T13,T14 |
|
| LP_EVAL |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T8,T13,T14 |
|
| LP_EVAL |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T8,T13,T14 |
|
| LP_EVAL |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T14,T55,T56 |
|
| LP_EVAL |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T7,T8,T13 |
|
| LP_SLP |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T7,T8,T13 |
|
| LP_SLP |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T7,T8,T13 |
|
| LP_SLP |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
| LP_PWRUP |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T7,T8,T13 |
|
| LP_PWRUP |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T7,T8,T13 |
|
| LP_PWRUP |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
| NP_0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
|
| NP_0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
|
| NP_021 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
|
| NP_021 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
|
| NP_1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
|
| NP_1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
|
| NP_EVAL |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
1 |
- |
- |
- |
Covered |
T13,T15,T20 |
|
| NP_EVAL |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
0 |
- |
- |
- |
Covered |
T2,T4,T10 |
|
| NP_EVAL |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
1 |
- |
- |
Covered |
T3,T8,T12 |
|
| NP_EVAL |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
0 |
1 |
- |
Covered |
T8,T12,T13 |
|
| NP_EVAL |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
0 |
0 |
1 |
Covered |
T8,T12,T13 |
|
| NP_EVAL |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
0 |
0 |
0 |
Excluded |
|
VC_COV_UNR |
| NP_EVAL |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
|
| NP_DONE |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T8,T12,T13 |
|
| default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
|
Assert Coverage for Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm
Assertion Details
LpSampleCntCfg_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
31070228 |
30997539 |
0 |
0 |
| T1 |
82 |
1 |
0 |
0 |
| T2 |
1139 |
1053 |
0 |
0 |
| T3 |
308 |
136 |
0 |
0 |
| T4 |
749 |
676 |
0 |
0 |
| T5 |
1107 |
1028 |
0 |
0 |
| T6 |
1227 |
1139 |
0 |
0 |
| T7 |
7255 |
7183 |
0 |
0 |
| T8 |
63 |
1 |
0 |
0 |
| T21 |
83 |
1 |
0 |
0 |
| T22 |
90 |
1 |
0 |
0 |
NpCntClrMisMatch_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
31070228 |
152045 |
0 |
0 |
| T2 |
1139 |
10 |
0 |
0 |
| T3 |
308 |
0 |
0 |
0 |
| T4 |
749 |
7 |
0 |
0 |
| T5 |
1107 |
0 |
0 |
0 |
| T6 |
1227 |
0 |
0 |
0 |
| T7 |
7255 |
51 |
0 |
0 |
| T8 |
63 |
0 |
0 |
0 |
| T9 |
1129 |
0 |
0 |
0 |
| T10 |
0 |
3 |
0 |
0 |
| T12 |
0 |
1029 |
0 |
0 |
| T13 |
0 |
129 |
0 |
0 |
| T21 |
83 |
0 |
0 |
0 |
| T22 |
90 |
0 |
0 |
0 |
| T27 |
0 |
10 |
0 |
0 |
| T38 |
0 |
39 |
0 |
0 |
| T39 |
0 |
36 |
0 |
0 |
| T42 |
0 |
54 |
0 |
0 |
NpCntClrPwrDn_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
31070228 |
87916 |
0 |
0 |
| T1 |
82 |
1 |
0 |
0 |
| T2 |
1139 |
123 |
0 |
0 |
| T3 |
308 |
19 |
0 |
0 |
| T4 |
749 |
79 |
0 |
0 |
| T5 |
1107 |
241 |
0 |
0 |
| T6 |
1227 |
241 |
0 |
0 |
| T7 |
7255 |
78 |
0 |
0 |
| T8 |
63 |
1 |
0 |
0 |
| T21 |
83 |
1 |
0 |
0 |
| T22 |
90 |
1 |
0 |
0 |
NpSampleCntCfg_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
31070228 |
30997539 |
0 |
0 |
| T1 |
82 |
1 |
0 |
0 |
| T2 |
1139 |
1053 |
0 |
0 |
| T3 |
308 |
136 |
0 |
0 |
| T4 |
749 |
676 |
0 |
0 |
| T5 |
1107 |
1028 |
0 |
0 |
| T6 |
1227 |
1139 |
0 |
0 |
| T7 |
7255 |
7183 |
0 |
0 |
| T8 |
63 |
1 |
0 |
0 |
| T21 |
83 |
1 |
0 |
0 |
| T22 |
90 |
1 |
0 |
0 |