Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : adc_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.82 99.07 96.67 100.00 100.00 98.83 98.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
adc_ctrl_csr_assert 96.00 96.00
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_adc_ctrl_core 99.83 100.00 99.76 100.00 99.37 100.00
u_reg 97.96 98.97 96.02 100.00 98.76 96.05

Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : adc_ctrl
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN4911100.00


48                        logic [NumAlerts-1:0] alert_test, alerts;
49         1/1            assign alert_test = {reg2hw.alert_test.q & reg2hw.alert_test.qe};
           Tests:       T1 T2 T3 
Cond Coverage for Module : adc_ctrl
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       49
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------
-1--2-StatusTests
01CoveredT1,T22,T24
10CoveredT1,T2,T3
11CoveredT1,T22,T24
Toggle Coverage for Module : adc_ctrl
TotalCoveredPercent
Totals 34 34 100.00
Total Bits 368 368 100.00
Total Bits 0->1 184 184 100.00
Total Bits 1->0 184 184 100.00

Ports 34 34 100.00
Port Bits 368 368 100.00
Port Bits 0->1 184 184 100.00
Port Bits 1->0 184 184 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_aon_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T21,T8 Yes T1,T2,T3 INPUT
rst_aon_ni Yes Yes T3,T21,T8 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T3,T4,T21 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T3,T5 Yes T1,T3,T5 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T3,T5 Yes T1,T3,T5 INPUT
tl_i.a_address[31:0] Yes Yes T1,T3,T5 Yes T1,T3,T5 INPUT
tl_i.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T3,T5 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T3,T8,T14 Yes T3,T8,T14 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T3,T5,T6 Yes T3,T5,T6 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T3,T5 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T2,T3,T5 Yes T1,T2,T3 OUTPUT
tl_o.d_size[1:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T3,*T5,*T6 Yes T1,T3,T5 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T1,T21,T22 Yes T1,T21,T22 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T1,T21,T22 Yes T1,T21,T22 OUTPUT
adc_o.pd Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
adc_o.channel_sel[1:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
adc_i.data_valid Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
adc_i.data[9:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
intr_match_pending_o Yes Yes T3,T8,T12 Yes T3,T8,T12 OUTPUT
wkup_req_o Yes Yes T8,T13,T14 Yes T8,T13,T14 OUTPUT

*Tests covering at least one bit in the range
Assert Coverage for Module : adc_ctrl
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 7 7 100.00 7 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 7 7 100.00 7 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AdcKnown_A 2147483647 2147483647 0 0
AlertsKnown_A 2147483647 2147483647 0 0
FpvSecCmRegWeOnehotCheck_A 2147483647 80 0 0
IntrKnown 2147483647 2147483647 0 0
TlOAReadyKnown 2147483647 2147483647 0 0
TlODValidKnown 2147483647 2147483647 0 0
WakeKnown 2147483647 2147483647 0 0


AdcKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 6727 6646 0 0
T2 79853 79769 0 0
T3 84623 83689 0 0
T4 63839 63788 0 0
T5 554109 554018 0 0
T6 306983 306930 0 0
T7 362814 362725 0 0
T8 178805 177728 0 0
T21 394406 393655 0 0
T22 8664 8564 0 0

AlertsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 6727 6646 0 0
T2 79853 79769 0 0
T3 84623 83689 0 0
T4 63839 63788 0 0
T5 554109 554018 0 0
T6 306983 306930 0 0
T7 362814 362725 0 0
T8 178805 177728 0 0
T21 394406 393655 0 0
T22 8664 8564 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 80 0 0
T8 178805 0 0 0
T9 67841 0 0 0
T10 148126 0 0 0
T11 141726 0 0 0
T21 394406 10 0 0
T22 8664 0 0 0
T23 790263 20 0 0
T24 10772 0 0 0
T25 97081 10 0 0
T26 42370 0 0 0
T43 0 20 0 0
T80 0 20 0 0

IntrKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 6727 6646 0 0
T2 79853 79769 0 0
T3 84623 83689 0 0
T4 63839 63788 0 0
T5 554109 554018 0 0
T6 306983 306930 0 0
T7 362814 362725 0 0
T8 178805 177728 0 0
T21 394406 393655 0 0
T22 8664 8564 0 0

TlOAReadyKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 6727 6646 0 0
T2 79853 79769 0 0
T3 84623 83689 0 0
T4 63839 63788 0 0
T5 554109 554018 0 0
T6 306983 306930 0 0
T7 362814 362725 0 0
T8 178805 177728 0 0
T21 394406 393655 0 0
T22 8664 8564 0 0

TlODValidKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 6727 6646 0 0
T2 79853 79769 0 0
T3 84623 83689 0 0
T4 63839 63788 0 0
T5 554109 554018 0 0
T6 306983 306930 0 0
T7 362814 362725 0 0
T8 178805 177728 0 0
T21 394406 393655 0 0
T22 8664 8564 0 0

WakeKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 6727 6646 0 0
T2 79853 79769 0 0
T3 84623 83689 0 0
T4 63839 63788 0 0
T5 554109 554018 0 0
T6 306983 306930 0 0
T7 362814 362725 0 0
T8 178805 177728 0 0
T21 394406 393655 0 0
T22 8664 8564 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%