Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1965	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1827	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1799	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1696	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1851	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1801	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1736	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1729	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1964	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1804	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1947	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1981	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1651	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1845	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1896	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1840	0	0
adc_en_ctl_rd_A	2147483647	1512	0	0
adc_fsm_rst_rd_A	2147483647	1152	0	0
adc_intr_ctl_rd_A	2147483647	1670	0	0
adc_lp_sample_ctl_rd_A	2147483647	1336	0	0
adc_pd_ctl_rd_A	2147483647	1531	0	0
adc_sample_ctl_rd_A	2147483647	1205	0	0
adc_wakeup_ctl_rd_A	2147483647	1411	0	0
intr_enable_rd_A	2147483647	1421	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1965	0	0
T14	462658	30	0	0
T15	305871	0	0	0
T28	0	41	0	0
T29	0	17	0	0
T30	0	8	0	0
T31	0	23	0	0
T32	0	4	0	0
T33	0	33	0	0
T34	0	10	0	0
T35	0	42	0	0
T36	0	49	0	0
T37	8441	0	0	0
T38	307501	0	0	0
T39	133908	0	0	0
T40	243288	0	0	0
T41	563985	0	0	0
T42	109525	0	0	0
T43	814578	0	0	0
T44	142581	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1827	0	0
T14	462658	27	0	0
T15	305871	0	0	0
T28	0	53	0	0
T29	0	30	0	0
T30	0	7	0	0
T31	0	15	0	0
T33	0	35	0	0
T34	0	23	0	0
T35	0	33	0	0
T36	0	16	0	0
T37	8441	0	0	0
T38	307501	0	0	0
T39	133908	0	0	0
T40	243288	0	0	0
T41	563985	0	0	0
T42	109525	0	0	0
T43	814578	0	0	0
T44	142581	0	0	0
T45	0	18	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1799	0	0
T14	462658	23	0	0
T15	305871	0	0	0
T28	0	35	0	0
T29	0	10	0	0
T30	0	31	0	0
T31	0	26	0	0
T32	0	14	0	0
T33	0	31	0	0
T34	0	17	0	0
T35	0	23	0	0
T36	0	41	0	0
T37	8441	0	0	0
T38	307501	0	0	0
T39	133908	0	0	0
T40	243288	0	0	0
T41	563985	0	0	0
T42	109525	0	0	0
T43	814578	0	0	0
T44	142581	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1696	0	0
T14	462658	41	0	0
T15	305871	0	0	0
T28	0	34	0	0
T29	0	15	0	0
T30	0	5	0	0
T31	0	17	0	0
T32	0	15	0	0
T33	0	48	0	0
T34	0	30	0	0
T35	0	23	0	0
T36	0	45	0	0
T37	8441	0	0	0
T38	307501	0	0	0
T39	133908	0	0	0
T40	243288	0	0	0
T41	563985	0	0	0
T42	109525	0	0	0
T43	814578	0	0	0
T44	142581	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1851	0	0
T14	462658	6	0	0
T15	305871	0	0	0
T28	0	49	0	0
T29	0	22	0	0
T30	0	14	0	0
T31	0	17	0	0
T32	0	7	0	0
T33	0	38	0	0
T34	0	25	0	0
T35	0	10	0	0
T36	0	44	0	0
T37	8441	0	0	0
T38	307501	0	0	0
T39	133908	0	0	0
T40	243288	0	0	0
T41	563985	0	0	0
T42	109525	0	0	0
T43	814578	0	0	0
T44	142581	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1801	0	0
T14	462658	17	0	0
T15	305871	0	0	0
T28	0	37	0	0
T29	0	10	0	0
T30	0	3	0	0
T31	0	11	0	0
T32	0	13	0	0
T33	0	38	0	0
T34	0	27	0	0
T35	0	12	0	0
T36	0	39	0	0
T37	8441	0	0	0
T38	307501	0	0	0
T39	133908	0	0	0
T40	243288	0	0	0
T41	563985	0	0	0
T42	109525	0	0	0
T43	814578	0	0	0
T44	142581	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1736	0	0
T14	462658	34	0	0
T15	305871	0	0	0
T28	0	35	0	0
T29	0	14	0	0
T30	0	15	0	0
T31	0	14	0	0
T32	0	9	0	0
T33	0	37	0	0
T34	0	20	0	0
T35	0	18	0	0
T36	0	40	0	0
T37	8441	0	0	0
T38	307501	0	0	0
T39	133908	0	0	0
T40	243288	0	0	0
T41	563985	0	0	0
T42	109525	0	0	0
T43	814578	0	0	0
T44	142581	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1729	0	0
T14	462658	4	0	0
T15	305871	0	0	0
T28	0	53	0	0
T29	0	20	0	0
T30	0	9	0	0
T31	0	23	0	0
T32	0	3	0	0
T33	0	29	0	0
T34	0	15	0	0
T35	0	44	0	0
T36	0	26	0	0
T37	8441	0	0	0
T38	307501	0	0	0
T39	133908	0	0	0
T40	243288	0	0	0
T41	563985	0	0	0
T42	109525	0	0	0
T43	814578	0	0	0
T44	142581	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1964	0	0
T14	462658	17	0	0
T15	305871	0	0	0
T28	0	34	0	0
T29	0	14	0	0
T30	0	8	0	0
T31	0	17	0	0
T32	0	5	0	0
T33	0	40	0	0
T34	0	12	0	0
T35	0	31	0	0
T36	0	37	0	0
T37	8441	0	0	0
T38	307501	0	0	0
T39	133908	0	0	0
T40	243288	0	0	0
T41	563985	0	0	0
T42	109525	0	0	0
T43	814578	0	0	0
T44	142581	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1804	0	0
T14	462658	41	0	0
T15	305871	0	0	0
T28	0	34	0	0
T29	0	27	0	0
T30	0	14	0	0
T31	0	22	0	0
T32	0	9	0	0
T33	0	43	0	0
T34	0	19	0	0
T35	0	23	0	0
T36	0	24	0	0
T37	8441	0	0	0
T38	307501	0	0	0
T39	133908	0	0	0
T40	243288	0	0	0
T41	563985	0	0	0
T42	109525	0	0	0
T43	814578	0	0	0
T44	142581	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1947	0	0
T14	462658	18	0	0
T15	305871	0	0	0
T28	0	37	0	0
T29	0	18	0	0
T30	0	14	0	0
T31	0	9	0	0
T32	0	17	0	0
T33	0	42	0	0
T34	0	10	0	0
T35	0	33	0	0
T36	0	47	0	0
T37	8441	0	0	0
T38	307501	0	0	0
T39	133908	0	0	0
T40	243288	0	0	0
T41	563985	0	0	0
T42	109525	0	0	0
T43	814578	0	0	0
T44	142581	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1981	0	0
T14	462658	18	0	0
T15	305871	0	0	0
T28	0	44	0	0
T29	0	27	0	0
T30	0	19	0	0
T31	0	15	0	0
T32	0	14	0	0
T33	0	29	0	0
T34	0	27	0	0
T35	0	33	0	0
T36	0	38	0	0
T37	8441	0	0	0
T38	307501	0	0	0
T39	133908	0	0	0
T40	243288	0	0	0
T41	563985	0	0	0
T42	109525	0	0	0
T43	814578	0	0	0
T44	142581	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1651	0	0
T14	462658	14	0	0
T15	305871	0	0	0
T28	0	52	0	0
T29	0	7	0	0
T30	0	3	0	0
T31	0	12	0	0
T32	0	17	0	0
T33	0	33	0	0
T34	0	11	0	0
T35	0	19	0	0
T36	0	48	0	0
T37	8441	0	0	0
T38	307501	0	0	0
T39	133908	0	0	0
T40	243288	0	0	0
T41	563985	0	0	0
T42	109525	0	0	0
T43	814578	0	0	0
T44	142581	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1845	0	0
T14	462658	5	0	0
T15	305871	0	0	0
T28	0	50	0	0
T29	0	25	0	0
T30	0	1	0	0
T31	0	15	0	0
T32	0	8	0	0
T33	0	44	0	0
T34	0	13	0	0
T35	0	31	0	0
T36	0	40	0	0
T37	8441	0	0	0
T38	307501	0	0	0
T39	133908	0	0	0
T40	243288	0	0	0
T41	563985	0	0	0
T42	109525	0	0	0
T43	814578	0	0	0
T44	142581	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1896	0	0
T14	462658	18	0	0
T15	305871	0	0	0
T28	0	25	0	0
T29	0	18	0	0
T30	0	7	0	0
T31	0	15	0	0
T32	0	14	0	0
T33	0	36	0	0
T34	0	25	0	0
T35	0	24	0	0
T36	0	27	0	0
T37	8441	0	0	0
T38	307501	0	0	0
T39	133908	0	0	0
T40	243288	0	0	0
T41	563985	0	0	0
T42	109525	0	0	0
T43	814578	0	0	0
T44	142581	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1840	0	0
T14	462658	23	0	0
T15	305871	0	0	0
T28	0	33	0	0
T29	0	26	0	0
T30	0	17	0	0
T31	0	14	0	0
T32	0	10	0	0
T33	0	48	0	0
T34	0	9	0	0
T35	0	14	0	0
T36	0	47	0	0
T37	8441	0	0	0
T38	307501	0	0	0
T39	133908	0	0	0
T40	243288	0	0	0
T41	563985	0	0	0
T42	109525	0	0	0
T43	814578	0	0	0
T44	142581	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1512	0	0
T14	462658	34	0	0
T15	305871	0	0	0
T28	0	32	0	0
T29	0	28	0	0
T30	0	5	0	0
T31	0	23	0	0
T32	0	13	0	0
T33	0	37	0	0
T34	0	21	0	0
T35	0	25	0	0
T36	0	48	0	0
T37	8441	0	0	0
T38	307501	0	0	0
T39	133908	0	0	0
T40	243288	0	0	0
T41	563985	0	0	0
T42	109525	0	0	0
T43	814578	0	0	0
T44	142581	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1152	0	0
T14	462658	10	0	0
T15	305871	0	0	0
T28	0	36	0	0
T29	0	13	0	0
T30	0	13	0	0
T31	0	16	0	0
T32	0	7	0	0
T33	0	33	0	0
T34	0	14	0	0
T35	0	19	0	0
T36	0	32	0	0
T37	8441	0	0	0
T38	307501	0	0	0
T39	133908	0	0	0
T40	243288	0	0	0
T41	563985	0	0	0
T42	109525	0	0	0
T43	814578	0	0	0
T44	142581	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1670	0	0
T14	462658	24	0	0
T15	305871	0	0	0
T28	0	21	0	0
T29	0	8	0	0
T30	0	20	0	0
T31	0	7	0	0
T32	0	9	0	0
T33	0	31	0	0
T34	0	21	0	0
T35	0	35	0	0
T36	0	28	0	0
T37	8441	0	0	0
T38	307501	0	0	0
T39	133908	0	0	0
T40	243288	0	0	0
T41	563985	0	0	0
T42	109525	0	0	0
T43	814578	0	0	0
T44	142581	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1336	0	0
T14	462658	15	0	0
T15	305871	0	0	0
T28	0	34	0	0
T29	0	13	0	0
T30	0	5	0	0
T31	0	18	0	0
T32	0	13	0	0
T33	0	38	0	0
T34	0	24	0	0
T35	0	37	0	0
T36	0	52	0	0
T37	8441	0	0	0
T38	307501	0	0	0
T39	133908	0	0	0
T40	243288	0	0	0
T41	563985	0	0	0
T42	109525	0	0	0
T43	814578	0	0	0
T44	142581	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1531	0	0
T14	462658	17	0	0
T15	305871	0	0	0
T28	0	44	0	0
T29	0	8	0	0
T30	0	12	0	0
T31	0	19	0	0
T32	0	5	0	0
T33	0	36	0	0
T34	0	23	0	0
T35	0	21	0	0
T36	0	31	0	0
T37	8441	0	0	0
T38	307501	0	0	0
T39	133908	0	0	0
T40	243288	0	0	0
T41	563985	0	0	0
T42	109525	0	0	0
T43	814578	0	0	0
T44	142581	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1205	0	0
T14	462658	16	0	0
T15	305871	0	0	0
T28	0	48	0	0
T29	0	21	0	0
T30	0	11	0	0
T31	0	26	0	0
T32	0	16	0	0
T33	0	29	0	0
T34	0	19	0	0
T35	0	37	0	0
T36	0	38	0	0
T37	8441	0	0	0
T38	307501	0	0	0
T39	133908	0	0	0
T40	243288	0	0	0
T41	563985	0	0	0
T42	109525	0	0	0
T43	814578	0	0	0
T44	142581	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1411	0	0
T14	462658	29	0	0
T15	305871	0	0	0
T28	0	40	0	0
T29	0	18	0	0
T30	0	16	0	0
T31	0	16	0	0
T32	0	8	0	0
T33	0	24	0	0
T34	0	22	0	0
T35	0	32	0	0
T36	0	38	0	0
T37	8441	0	0	0
T38	307501	0	0	0
T39	133908	0	0	0
T40	243288	0	0	0
T41	563985	0	0	0
T42	109525	0	0	0
T43	814578	0	0	0
T44	142581	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1421	0	0
T11	141726	24	0	0
T12	290532	0	0	0
T13	193731	0	0	0
T14	462658	17	0	0
T24	10772	0	0	0
T25	97081	0	0	0
T26	42370	0	0	0
T27	93333	0	0	0
T28	0	36	0	0
T29	0	28	0	0
T30	0	20	0	0
T31	0	81	0	0
T33	0	53	0	0
T34	0	24	0	0
T35	0	40	0	0
T37	8441	0	0	0
T38	307501	0	0	0
T46	0	7	0	0