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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.76 99.07 96.67 100.00 100.00 98.83 98.33 91.42


Total test records in report: 919
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html

T328 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt.479654664 Aug 28 08:22:56 PM UTC 24 Aug 28 08:39:43 PM UTC 24 320877590191 ps
T470 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_wakeup_fixed.261806290 Aug 28 08:36:07 PM UTC 24 Aug 28 08:39:48 PM UTC 24 586599730819 ps
T471 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_alert_test.274907217 Aug 28 08:39:49 PM UTC 24 Aug 28 08:39:51 PM UTC 24 367188139 ps
T472 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_smoke.3047507354 Aug 28 08:39:52 PM UTC 24 Aug 28 08:40:00 PM UTC 24 6025453146 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2658924262 Aug 28 08:39:36 PM UTC 24 Aug 28 08:40:02 PM UTC 24 3820233339 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt.1126225918 Aug 28 08:27:48 PM UTC 24 Aug 28 08:40:07 PM UTC 24 486119908152 ps
T473 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup_fixed.539458943 Aug 28 08:29:53 PM UTC 24 Aug 28 08:40:20 PM UTC 24 396102524377 ps
T474 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_lowpower_counter.2164752967 Aug 28 08:38:02 PM UTC 24 Aug 28 08:40:35 PM UTC 24 32326351144 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_interrupt.3578164931 Aug 28 08:37:22 PM UTC 24 Aug 28 08:40:36 PM UTC 24 162860146514 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup.4049468051 Aug 28 08:26:28 PM UTC 24 Aug 28 08:40:37 PM UTC 24 544136625119 ps
T475 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup_fixed.988887221 Aug 28 08:34:39 PM UTC 24 Aug 28 08:40:46 PM UTC 24 197590083599 ps
T476 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3160197035 Aug 28 08:37:28 PM UTC 24 Aug 28 08:40:47 PM UTC 24 328018185731 ps
T477 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_poweron_counter.729192569 Aug 28 08:40:47 PM UTC 24 Aug 28 08:40:52 PM UTC 24 4642871777 ps
T478 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_lowpower_counter.1833625146 Aug 28 08:39:21 PM UTC 24 Aug 28 08:41:00 PM UTC 24 28033063931 ps
T479 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_lowpower_counter.3679794155 Aug 28 08:40:52 PM UTC 24 Aug 28 08:41:10 PM UTC 24 34591016363 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_both.637882351 Aug 28 08:39:16 PM UTC 24 Aug 28 08:41:12 PM UTC 24 174486379057 ps
T480 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled_fixed.1544125584 Aug 28 08:18:15 PM UTC 24 Aug 28 08:41:24 PM UTC 24 478340596376 ps
T338 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_interrupt.2897001063 Aug 28 08:38:33 PM UTC 24 Aug 28 08:41:25 PM UTC 24 169013810052 ps
T481 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_alert_test.2511622917 Aug 28 08:41:25 PM UTC 24 Aug 28 08:41:29 PM UTC 24 499462962 ps
T482 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_smoke.2472428770 Aug 28 08:41:26 PM UTC 24 Aug 28 08:41:30 PM UTC 24 5895827771 ps
T483 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled.71883431 Aug 28 08:37:19 PM UTC 24 Aug 28 08:41:33 PM UTC 24 165022801946 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.677986568 Aug 28 08:41:11 PM UTC 24 Aug 28 08:41:50 PM UTC 24 25344340333 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_both.826966669 Aug 28 08:26:51 PM UTC 24 Aug 28 08:41:54 PM UTC 24 322119846767 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_polled.3793805652 Aug 28 08:38:18 PM UTC 24 Aug 28 08:42:00 PM UTC 24 164397099544 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_clock_gating.2358821102 Aug 28 08:30:04 PM UTC 24 Aug 28 08:42:07 PM UTC 24 540730776457 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_fsm_reset.3771957792 Aug 28 08:27:14 PM UTC 24 Aug 28 08:42:58 PM UTC 24 102427948309 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup_fixed.1640202378 Aug 28 08:12:44 PM UTC 24 Aug 28 08:43:05 PM UTC 24 593066940573 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup_fixed.721469657 Aug 28 08:13:17 PM UTC 24 Aug 28 08:43:12 PM UTC 24 580232433263 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_wakeup_fixed.325018505 Aug 28 08:40:37 PM UTC 24 Aug 28 08:43:23 PM UTC 24 593866830971 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_poweron_counter.1317519678 Aug 28 08:43:06 PM UTC 24 Aug 28 08:43:26 PM UTC 24 4364693186 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_stress_all.3430964003 Aug 28 08:41:14 PM UTC 24 Aug 28 08:43:36 PM UTC 24 164839472901 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.680194184 Aug 28 08:43:27 PM UTC 24 Aug 28 08:43:38 PM UTC 24 6973168499 ps
T484 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_alert_test.2813949865 Aug 28 08:43:39 PM UTC 24 Aug 28 08:43:42 PM UTC 24 507952315 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_polled.3996196851 Aug 28 08:40:01 PM UTC 24 Aug 28 08:43:51 PM UTC 24 165085668364 ps
T485 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_wakeup_fixed.2400289492 Aug 28 08:42:01 PM UTC 24 Aug 28 08:43:51 PM UTC 24 190318934781 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_both.2987346569 Aug 28 08:30:07 PM UTC 24 Aug 28 08:43:55 PM UTC 24 337216261276 ps
T486 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2461514753 Aug 28 08:26:32 PM UTC 24 Aug 28 08:43:56 PM UTC 24 397191459755 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_clock_gating.1899985576 Aug 28 08:39:01 PM UTC 24 Aug 28 08:44:02 PM UTC 24 509519745091 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt.1234812573 Aug 28 08:26:03 PM UTC 24 Aug 28 08:44:03 PM UTC 24 337286408439 ps
T332 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_wakeup.1534862069 Aug 28 08:36:03 PM UTC 24 Aug 28 08:44:08 PM UTC 24 184955963928 ps
T487 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_smoke.456553050 Aug 28 08:43:42 PM UTC 24 Aug 28 08:44:08 PM UTC 24 6084695359 ps
T488 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1921031463 Aug 28 08:14:56 PM UTC 24 Aug 28 08:44:17 PM UTC 24 612250499010 ps
T489 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup.2438808260 Aug 28 08:37:32 PM UTC 24 Aug 28 08:44:18 PM UTC 24 171925021019 ps
T490 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_lowpower_counter.1516034809 Aug 28 08:43:13 PM UTC 24 Aug 28 08:44:27 PM UTC 24 38666999722 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_interrupt.3305401661 Aug 28 08:41:33 PM UTC 24 Aug 28 08:44:30 PM UTC 24 166007854282 ps
T491 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_poweron_counter.828924562 Aug 28 08:44:18 PM UTC 24 Aug 28 08:44:34 PM UTC 24 3452713769 ps
T492 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_interrupt_fixed.4134064951 Aug 28 08:40:21 PM UTC 24 Aug 28 08:44:34 PM UTC 24 331264785793 ps
T493 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt.364513298 Aug 28 08:35:45 PM UTC 24 Aug 28 08:44:35 PM UTC 24 165978636078 ps
T494 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_alert_test.3986556343 Aug 28 08:44:35 PM UTC 24 Aug 28 08:44:37 PM UTC 24 348423922 ps
T355 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all.1490832521 Aug 28 08:35:23 PM UTC 24 Aug 28 08:44:42 PM UTC 24 238098373780 ps
T495 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_polled.1830167153 Aug 28 08:41:30 PM UTC 24 Aug 28 08:44:49 PM UTC 24 168918674307 ps
T496 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2268296346 Aug 28 08:38:55 PM UTC 24 Aug 28 08:44:54 PM UTC 24 327274395861 ps
T331 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_clock_gating.3531349195 Aug 28 08:23:23 PM UTC 24 Aug 28 08:44:55 PM UTC 24 530974706802 ps
T497 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_lowpower_counter.2842760209 Aug 28 08:44:19 PM UTC 24 Aug 28 08:44:59 PM UTC 24 38985846122 ps
T498 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_smoke.2757665162 Aug 28 08:44:36 PM UTC 24 Aug 28 08:45:01 PM UTC 24 5516728253 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_both.2971772204 Aug 28 08:36:26 PM UTC 24 Aug 28 08:45:03 PM UTC 24 175564309084 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_both.3536656730 Aug 28 08:42:59 PM UTC 24 Aug 28 08:45:12 PM UTC 24 330557407567 ps
T499 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_poweron_counter.2924531724 Aug 28 08:45:13 PM UTC 24 Aug 28 08:45:18 PM UTC 24 3348288551 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.3895472511 Aug 28 08:44:31 PM UTC 24 Aug 28 08:45:49 PM UTC 24 191499337948 ps
T500 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled_fixed.2873615588 Aug 28 08:35:43 PM UTC 24 Aug 28 08:46:01 PM UTC 24 325416262066 ps
T501 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_interrupt_fixed.223773292 Aug 28 08:41:51 PM UTC 24 Aug 28 08:46:13 PM UTC 24 322738101309 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3275807485 Aug 28 08:46:01 PM UTC 24 Aug 28 08:46:16 PM UTC 24 2665709160 ps
T502 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_fsm_reset.451816711 Aug 28 08:36:45 PM UTC 24 Aug 28 08:46:18 PM UTC 24 107783039010 ps
T503 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_alert_test.1634876905 Aug 28 08:46:17 PM UTC 24 Aug 28 08:46:21 PM UTC 24 496004827 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup.2736636748 Aug 28 08:34:32 PM UTC 24 Aug 28 08:46:22 PM UTC 24 516832975753 ps
T504 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_smoke.4079158628 Aug 28 08:46:19 PM UTC 24 Aug 28 08:46:27 PM UTC 24 5678425987 ps
T505 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all.1952184514 Aug 28 08:44:35 PM UTC 24 Aug 28 08:46:35 PM UTC 24 186608634139 ps
T506 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt_fixed.392689428 Aug 28 08:29:38 PM UTC 24 Aug 28 08:46:41 PM UTC 24 327688384346 ps
T507 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt_fixed.889788962 Aug 28 08:31:36 PM UTC 24 Aug 28 08:46:45 PM UTC 24 327858065625 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all.326460324 Aug 28 08:18:04 PM UTC 24 Aug 28 08:46:55 PM UTC 24 444595497205 ps
T508 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_lowpower_counter.3096538116 Aug 28 08:45:19 PM UTC 24 Aug 28 08:47:03 PM UTC 24 26016738622 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_fsm_reset.748295309 Aug 28 08:38:06 PM UTC 24 Aug 28 08:47:17 PM UTC 24 126961513905 ps
T364 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all.4090471721 Aug 28 08:37:11 PM UTC 24 Aug 28 08:47:22 PM UTC 24 166661877011 ps
T387 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_fsm_reset.265139970 Aug 28 08:39:23 PM UTC 24 Aug 28 08:47:22 PM UTC 24 97831835516 ps
T509 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_poweron_counter.1242835959 Aug 28 08:47:18 PM UTC 24 Aug 28 08:47:23 PM UTC 24 3089776246 ps
T510 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_polled_fixed.1100097608 Aug 28 08:44:42 PM UTC 24 Aug 28 08:47:28 PM UTC 24 166994031109 ps
T511 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_polled_fixed.81657528 Aug 28 08:38:18 PM UTC 24 Aug 28 08:47:34 PM UTC 24 490275827464 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2819299886 Aug 28 08:47:24 PM UTC 24 Aug 28 08:47:36 PM UTC 24 8924513243 ps
T512 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_alert_test.2448533459 Aug 28 08:47:34 PM UTC 24 Aug 28 08:47:38 PM UTC 24 292425121 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_clock_gating.1999445435 Aug 28 08:26:38 PM UTC 24 Aug 28 08:47:38 PM UTC 24 520276376108 ps
T513 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_wakeup_fixed.2616050799 Aug 28 08:46:46 PM UTC 24 Aug 28 08:47:45 PM UTC 24 199038282884 ps
T339 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_both.3978282594 Aug 28 08:45:04 PM UTC 24 Aug 28 08:47:50 PM UTC 24 169258255561 ps
T514 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_smoke.1816657918 Aug 28 08:47:37 PM UTC 24 Aug 28 08:47:51 PM UTC 24 5875912126 ps
T349 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_interrupt.26170403 Aug 28 08:44:50 PM UTC 24 Aug 28 08:48:03 PM UTC 24 329536439023 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_polled.1551286739 Aug 28 08:46:22 PM UTC 24 Aug 28 08:48:05 PM UTC 24 167621317243 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all.1800252701 Aug 28 08:30:35 PM UTC 24 Aug 28 08:48:08 PM UTC 24 331641166304 ps
T515 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_lowpower_counter.2362026995 Aug 28 08:47:23 PM UTC 24 Aug 28 08:48:17 PM UTC 24 40584434742 ps
T516 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_wakeup_fixed.724065351 Aug 28 08:44:04 PM UTC 24 Aug 28 08:48:28 PM UTC 24 392505724801 ps
T517 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled.1247355074 Aug 28 08:21:15 PM UTC 24 Aug 28 08:48:42 PM UTC 24 484826364230 ps
T518 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_poweron_counter.3415220321 Aug 28 08:48:18 PM UTC 24 Aug 28 08:48:42 PM UTC 24 4903672128 ps
T519 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_lowpower_counter.3734568337 Aug 28 08:48:29 PM UTC 24 Aug 28 08:48:52 PM UTC 24 25817615896 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup.2591122660 Aug 28 08:18:39 PM UTC 24 Aug 28 08:48:57 PM UTC 24 527669764381 ps
T520 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_alert_test.2412726840 Aug 28 08:48:58 PM UTC 24 Aug 28 08:49:00 PM UTC 24 476294954 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_clock_gating.1347557212 Aug 28 08:33:20 PM UTC 24 Aug 28 08:49:00 PM UTC 24 366640126167 ps
T521 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_both.1356670463 Aug 28 08:40:47 PM UTC 24 Aug 28 08:49:04 PM UTC 24 166558726674 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.3117182804 Aug 28 08:48:42 PM UTC 24 Aug 28 08:49:06 PM UTC 24 7552150951 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_fsm_reset.542044241 Aug 28 08:33:58 PM UTC 24 Aug 28 08:49:22 PM UTC 24 133129271886 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_smoke.64780308 Aug 28 08:49:01 PM UTC 24 Aug 28 08:49:26 PM UTC 24 6001360828 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_interrupt.2311158163 Aug 28 08:47:46 PM UTC 24 Aug 28 08:49:31 PM UTC 24 162652046907 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_polled_fixed.1563941697 Aug 28 08:46:23 PM UTC 24 Aug 28 08:49:33 PM UTC 24 491278889920 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all.2750798407 Aug 28 08:39:43 PM UTC 24 Aug 28 08:49:34 PM UTC 24 325702736608 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_interrupt.849537607 Aug 28 08:40:08 PM UTC 24 Aug 28 08:49:35 PM UTC 24 333664307017 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_poweron_counter.2599867452 Aug 28 08:49:36 PM UTC 24 Aug 28 08:49:41 PM UTC 24 2800615894 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_lowpower_counter.804094695 Aug 28 08:49:41 PM UTC 24 Aug 28 08:49:53 PM UTC 24 28513667702 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_polled.765314101 Aug 28 08:44:38 PM UTC 24 Aug 28 08:50:10 PM UTC 24 329838646796 ps
T522 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3392279321 Aug 28 08:46:36 PM UTC 24 Aug 28 08:50:15 PM UTC 24 327970254853 ps
T523 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_polled_fixed.2092950839 Aug 28 08:41:31 PM UTC 24 Aug 28 08:50:21 PM UTC 24 326377861410 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_clock_gating.2508872343 Aug 28 08:48:05 PM UTC 24 Aug 28 08:50:22 PM UTC 24 358168044142 ps
T348 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all.1017372125 Aug 28 08:28:50 PM UTC 24 Aug 28 08:50:22 PM UTC 24 446477628444 ps
T524 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_alert_test.470338563 Aug 28 08:50:22 PM UTC 24 Aug 28 08:50:24 PM UTC 24 351515966 ps
T525 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_smoke.2486534312 Aug 28 08:50:23 PM UTC 24 Aug 28 08:50:30 PM UTC 24 5896064074 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2943038010 Aug 28 08:50:10 PM UTC 24 Aug 28 08:50:35 PM UTC 24 15278566096 ps
T526 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3486281568 Aug 28 08:47:51 PM UTC 24 Aug 28 08:50:36 PM UTC 24 166208454035 ps
T330 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_clock_gating.1528822482 Aug 28 08:45:02 PM UTC 24 Aug 28 08:50:49 PM UTC 24 507734031926 ps
T358 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_clock_gating.211657954 Aug 28 08:44:09 PM UTC 24 Aug 28 08:50:51 PM UTC 24 170258811838 ps
T527 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled.3419194619 Aug 28 08:25:58 PM UTC 24 Aug 28 08:51:04 PM UTC 24 486522509556 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_clock_gating.63958427 Aug 28 08:37:40 PM UTC 24 Aug 28 08:51:29 PM UTC 24 363193233549 ps
T528 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_poweron_counter.4222366760 Aug 28 08:51:29 PM UTC 24 Aug 28 08:51:34 PM UTC 24 4598823684 ps
T529 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_fsm_reset.3633796566 Aug 28 08:35:07 PM UTC 24 Aug 28 08:51:40 PM UTC 24 136698278276 ps
T530 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_polled_fixed.715798866 Aug 28 08:49:05 PM UTC 24 Aug 28 08:52:04 PM UTC 24 166986198966 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_clock_gating.3403888957 Aug 28 08:36:12 PM UTC 24 Aug 28 08:52:07 PM UTC 24 489750264749 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_clock_gating.3703948261 Aug 28 08:46:55 PM UTC 24 Aug 28 08:52:10 PM UTC 24 179579664633 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_wakeup.2824421629 Aug 28 08:40:36 PM UTC 24 Aug 28 08:52:11 PM UTC 24 529696619754 ps
T531 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_lowpower_counter.3742297764 Aug 28 08:51:35 PM UTC 24 Aug 28 08:52:12 PM UTC 24 33632176173 ps
T532 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.4214080678 Aug 28 08:52:05 PM UTC 24 Aug 28 08:52:14 PM UTC 24 3628719414 ps
T533 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_alert_test.1904368953 Aug 28 08:52:11 PM UTC 24 Aug 28 08:52:15 PM UTC 24 504244683 ps
T534 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_polled_fixed.1636412898 Aug 28 08:47:39 PM UTC 24 Aug 28 08:52:18 PM UTC 24 493505058225 ps
T535 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_smoke.4218937439 Aug 28 08:52:12 PM UTC 24 Aug 28 08:52:20 PM UTC 24 6036514636 ps
T536 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_interrupt_fixed.4013831518 Aug 28 08:44:55 PM UTC 24 Aug 28 08:52:27 PM UTC 24 495827298636 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_clock_gating.567265857 Aug 28 08:42:08 PM UTC 24 Aug 28 08:52:51 PM UTC 24 333427269481 ps
T537 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2051495345 Aug 28 08:28:05 PM UTC 24 Aug 28 08:52:59 PM UTC 24 491159495257 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all.2191717228 Aug 28 08:22:16 PM UTC 24 Aug 28 08:53:16 PM UTC 24 476874548201 ps
T538 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_polled_fixed.1581981693 Aug 28 08:43:52 PM UTC 24 Aug 28 08:53:09 PM UTC 24 325785929322 ps
T539 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled_fixed.2204302707 Aug 28 08:34:18 PM UTC 24 Aug 28 08:53:09 PM UTC 24 324381796577 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_wakeup.1910191850 Aug 28 08:41:55 PM UTC 24 Aug 28 08:53:13 PM UTC 24 441418687545 ps
T540 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_poweron_counter.2528908991 Aug 28 08:53:10 PM UTC 24 Aug 28 08:53:14 PM UTC 24 5388137225 ps
T381 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_fsm_reset.3313653821 Aug 28 08:44:28 PM UTC 24 Aug 28 08:53:19 PM UTC 24 142574132666 ps
T541 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_alert_test.3097801037 Aug 28 08:53:19 PM UTC 24 Aug 28 08:53:22 PM UTC 24 373249821 ps
T542 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_smoke.3363318366 Aug 28 08:53:23 PM UTC 24 Aug 28 08:53:30 PM UTC 24 5506804090 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_both.679810780 Aug 28 08:47:04 PM UTC 24 Aug 28 08:53:31 PM UTC 24 494852830718 ps
T543 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1962486402 Aug 28 08:35:46 PM UTC 24 Aug 28 08:53:33 PM UTC 24 329841102852 ps
T544 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_fsm_reset.2881997834 Aug 28 08:41:00 PM UTC 24 Aug 28 08:53:33 PM UTC 24 101387395490 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all.739460341 Aug 28 08:19:55 PM UTC 24 Aug 28 08:53:37 PM UTC 24 570784674410 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_interrupt.396097133 Aug 28 09:00:25 PM UTC 24 Aug 28 09:01:32 PM UTC 24 330272742461 ps
T545 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled_fixed.427106205 Aug 28 08:27:46 PM UTC 24 Aug 28 08:53:39 PM UTC 24 486098071579 ps
T546 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_interrupt_fixed.4023010039 Aug 28 08:49:22 PM UTC 24 Aug 28 08:53:43 PM UTC 24 172159949696 ps
T547 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_lowpower_counter.401781502 Aug 28 08:53:10 PM UTC 24 Aug 28 08:53:47 PM UTC 24 44181099748 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.254759105 Aug 28 08:53:15 PM UTC 24 Aug 28 08:54:03 PM UTC 24 76123893419 ps
T548 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_poweron_counter.645439756 Aug 28 08:54:04 PM UTC 24 Aug 28 08:54:14 PM UTC 24 3956901921 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_both.2690607245 Aug 28 08:34:56 PM UTC 24 Aug 28 08:54:24 PM UTC 24 504197704164 ps
T549 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_interrupt_fixed.1508249921 Aug 28 08:53:34 PM UTC 24 Aug 28 08:54:28 PM UTC 24 161154762559 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_wakeup.880216890 Aug 28 08:49:27 PM UTC 24 Aug 28 08:54:28 PM UTC 24 342760225666 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2928908379 Aug 28 08:54:25 PM UTC 24 Aug 28 08:54:31 PM UTC 24 1526550092 ps
T550 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_alert_test.3469467217 Aug 28 08:54:29 PM UTC 24 Aug 28 08:54:32 PM UTC 24 353617874 ps
T551 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_smoke.255536431 Aug 28 08:54:31 PM UTC 24 Aug 28 08:54:39 PM UTC 24 5969564426 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_clock_gating.189186987 Aug 28 08:34:46 PM UTC 24 Aug 28 08:54:40 PM UTC 24 563199772136 ps
T344 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_wakeup.279459168 Aug 28 08:47:52 PM UTC 24 Aug 28 08:54:56 PM UTC 24 362022440988 ps
T552 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_wakeup_fixed.456376522 Aug 28 08:45:00 PM UTC 24 Aug 28 08:55:05 PM UTC 24 402766948153 ps
T553 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_fsm_reset.3646403789 Aug 28 08:47:23 PM UTC 24 Aug 28 08:55:14 PM UTC 24 65540681166 ps
T554 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_lowpower_counter.2765204959 Aug 28 08:54:15 PM UTC 24 Aug 28 08:55:27 PM UTC 24 36027171386 ps
T555 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_polled.1996155637 Aug 28 08:43:52 PM UTC 24 Aug 28 08:55:35 PM UTC 24 324870046075 ps
T333 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_clock_gating.1921394534 Aug 28 08:52:52 PM UTC 24 Aug 28 08:55:45 PM UTC 24 175414836196 ps
T556 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_interrupt.1582070041 Aug 28 08:46:29 PM UTC 24 Aug 28 08:55:45 PM UTC 24 158410896998 ps
T557 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_poweron_counter.2008200120 Aug 28 08:55:46 PM UTC 24 Aug 28 08:55:59 PM UTC 24 5213974728 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_wakeup.1792910826 Aug 28 08:44:04 PM UTC 24 Aug 28 08:56:09 PM UTC 24 198232028479 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_interrupt.1973937281 Aug 28 08:53:34 PM UTC 24 Aug 28 08:56:13 PM UTC 24 322034527442 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_interrupt.1128941004 Aug 28 08:43:55 PM UTC 24 Aug 28 08:56:14 PM UTC 24 327124520882 ps
T558 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_alert_test.1371719751 Aug 28 08:56:15 PM UTC 24 Aug 28 08:56:18 PM UTC 24 317733475 ps
T559 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_wakeup_fixed.961260978 Aug 28 08:50:50 PM UTC 24 Aug 28 08:56:26 PM UTC 24 197875446485 ps
T368 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_both.1469697744 Aug 28 08:44:09 PM UTC 24 Aug 28 08:56:31 PM UTC 24 207025747887 ps
T560 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_smoke.1942072599 Aug 28 08:56:19 PM UTC 24 Aug 28 08:56:44 PM UTC 24 5798412199 ps
T561 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_wakeup_fixed.700424905 Aug 28 08:55:15 PM UTC 24 Aug 28 08:56:50 PM UTC 24 189023770917 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.1601818202 Aug 28 08:56:10 PM UTC 24 Aug 28 08:57:12 PM UTC 24 728690460995 ps
T562 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3079055945 Aug 28 08:48:04 PM UTC 24 Aug 28 08:57:13 PM UTC 24 598318308049 ps
T563 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_fsm_reset.1835770054 Aug 28 08:45:50 PM UTC 24 Aug 28 08:57:25 PM UTC 24 86364714888 ps
T564 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_fsm_reset.255364531 Aug 28 08:43:24 PM UTC 24 Aug 28 08:57:26 PM UTC 24 139292745419 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_wakeup.4160752001 Aug 28 08:50:37 PM UTC 24 Aug 28 08:57:39 PM UTC 24 547628675424 ps
T565 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_poweron_counter.748267460 Aug 28 08:57:39 PM UTC 24 Aug 28 08:57:46 PM UTC 24 5295037078 ps
T566 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_lowpower_counter.3766069256 Aug 28 08:57:47 PM UTC 24 Aug 28 08:58:01 PM UTC 24 43923401716 ps
T567 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_wakeup.3673525011 Aug 28 08:38:55 PM UTC 24 Aug 28 08:58:12 PM UTC 24 407905003003 ps
T568 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.2435509095 Aug 28 08:58:13 PM UTC 24 Aug 28 08:58:28 PM UTC 24 3055319923 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_interrupt.1055708455 Aug 28 08:56:45 PM UTC 24 Aug 28 08:58:42 PM UTC 24 325150441871 ps
T569 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_alert_test.1309599925 Aug 28 08:58:43 PM UTC 24 Aug 28 08:58:45 PM UTC 24 346314983 ps
T570 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_lowpower_counter.3153373393 Aug 28 08:55:46 PM UTC 24 Aug 28 08:58:46 PM UTC 24 44134120087 ps
T571 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_wakeup_fixed.603325139 Aug 28 08:52:27 PM UTC 24 Aug 28 08:58:47 PM UTC 24 626099058240 ps
T572 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_smoke.2150952365 Aug 28 08:58:46 PM UTC 24 Aug 28 08:58:53 PM UTC 24 5929504796 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup.1025822317 Aug 28 08:24:54 PM UTC 24 Aug 28 08:59:03 PM UTC 24 611890203188 ps
T573 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_polled_fixed.1426881066 Aug 28 08:53:32 PM UTC 24 Aug 28 08:59:06 PM UTC 24 164909674153 ps
T353 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_polled.2501578287 Aug 28 08:50:23 PM UTC 24 Aug 28 08:59:09 PM UTC 24 492494684475 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_clock_gating.1218992251 Aug 28 08:50:52 PM UTC 24 Aug 28 08:59:22 PM UTC 24 495296140024 ps
T574 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all.229239445 Aug 28 08:54:29 PM UTC 24 Aug 28 08:59:28 PM UTC 24 324689424711 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all.3830243886 Aug 28 08:53:17 PM UTC 24 Aug 28 08:59:41 PM UTC 24 333938621783 ps
T575 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_poweron_counter.1563440880 Aug 28 08:59:41 PM UTC 24 Aug 28 08:59:45 PM UTC 24 5050569065 ps
T576 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_fsm_reset.4018339133 Aug 28 08:48:42 PM UTC 24 Aug 28 08:59:46 PM UTC 24 109925253396 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_clock_gating.3443848357 Aug 28 08:57:25 PM UTC 24 Aug 28 08:59:49 PM UTC 24 164160659613 ps
T335 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_wakeup.3985660953 Aug 28 08:52:21 PM UTC 24 Aug 28 08:59:56 PM UTC 24 587272046125 ps
T385 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_fsm_reset.2660778625 Aug 28 08:51:41 PM UTC 24 Aug 28 09:00:03 PM UTC 24 121412670733 ps
T577 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_alert_test.3934200576 Aug 28 09:00:07 PM UTC 24 Aug 28 09:00:09 PM UTC 24 535449358 ps
T578 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_both.3827926880 Aug 28 08:51:05 PM UTC 24 Aug 28 09:00:14 PM UTC 24 341708152866 ps
T579 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.3915137127 Aug 28 08:59:49 PM UTC 24 Aug 28 09:00:19 PM UTC 24 68976282694 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_both.3477954585 Aug 28 08:33:35 PM UTC 24 Aug 28 09:00:24 PM UTC 24 547002341487 ps
T580 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_smoke.3366951805 Aug 28 09:00:11 PM UTC 24 Aug 28 09:00:38 PM UTC 24 5824028654 ps
T581 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_lowpower_counter.547411773 Aug 28 08:59:46 PM UTC 24 Aug 28 09:00:50 PM UTC 24 24949828786 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_clock_gating.4289041764 Aug 28 08:40:38 PM UTC 24 Aug 28 09:01:07 PM UTC 24 486257083358 ps
T582 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_polled_fixed.1589981268 Aug 28 08:52:15 PM UTC 24 Aug 28 09:01:08 PM UTC 24 166999181772 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_clock_gating.640577370 Aug 28 09:01:08 PM UTC 24 Aug 28 09:01:16 PM UTC 24 166141035032 ps
T583 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_both.3034124204 Aug 28 08:59:29 PM UTC 24 Aug 28 09:01:22 PM UTC 24 171838196143 ps
T584 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_wakeup_fixed.778389917 Aug 28 08:59:10 PM UTC 24 Aug 28 09:01:31 PM UTC 24 392321808144 ps
T585 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_poweron_counter.370923387 Aug 28 09:01:16 PM UTC 24 Aug 28 09:01:41 PM UTC 24 5296727153 ps
T586 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_polled.249698177 Aug 28 08:54:33 PM UTC 24 Aug 28 09:01:41 PM UTC 24 164226280573 ps
T587 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.990083807 Aug 28 09:01:32 PM UTC 24 Aug 28 09:01:42 PM UTC 24 2943546825 ps
T588 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_alert_test.1618648043 Aug 28 09:01:42 PM UTC 24 Aug 28 09:01:45 PM UTC 24 495695716 ps
T589 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_lowpower_counter.2433490846 Aug 28 09:01:22 PM UTC 24 Aug 28 09:01:47 PM UTC 24 21793128822 ps
T590 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_interrupt_fixed.1462312284 Aug 28 08:54:57 PM UTC 24 Aug 28 09:01:51 PM UTC 24 324360830867 ps
T591 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1564636512 Aug 28 09:00:32 PM UTC 24 Aug 28 09:01:52 PM UTC 24 169822576952 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_wakeup.1053205142 Aug 28 08:59:07 PM UTC 24 Aug 28 09:01:55 PM UTC 24 346601615282 ps
T592 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2971810164 Aug 28 08:56:51 PM UTC 24 Aug 28 09:02:04 PM UTC 24 163746639886 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_wakeup.2348048208 Aug 28 08:46:42 PM UTC 24 Aug 28 09:16:34 PM UTC 24 540370027119 ps
T593 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_smoke.655771298 Aug 28 09:01:42 PM UTC 24 Aug 28 09:02:06 PM UTC 24 5659716235 ps
T594 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_interrupt_fixed.904038588 Aug 28 08:59:04 PM UTC 24 Aug 28 09:02:08 PM UTC 24 163092523341 ps
T595 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_stress_all.1724081892 Aug 28 08:46:13 PM UTC 24 Aug 28 09:02:11 PM UTC 24 145473427803 ps
T596 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_poweron_counter.3961938014 Aug 28 09:02:09 PM UTC 24 Aug 28 09:02:13 PM UTC 24 4367593974 ps
T597 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_fsm_reset.1446973414 Aug 28 08:53:14 PM UTC 24 Aug 28 09:02:19 PM UTC 24 126021478886 ps
T598 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_wakeup_fixed.1341528381 Aug 28 09:00:51 PM UTC 24 Aug 28 09:02:26 PM UTC 24 199654151496 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2220580253 Aug 28 09:02:20 PM UTC 24 Aug 28 09:02:33 PM UTC 24 15846476863 ps
T599 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_alert_test.2920792365 Aug 28 09:02:33 PM UTC 24 Aug 28 09:02:37 PM UTC 24 442101663 ps
T600 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3230680336 Aug 28 08:57:14 PM UTC 24 Aug 28 09:02:39 PM UTC 24 195119418892 ps
T386 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all.3158207999 Aug 28 08:38:13 PM UTC 24 Aug 28 09:02:40 PM UTC 24 426865152067 ps
T601 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_interrupt.3142884097 Aug 28 08:54:41 PM UTC 24 Aug 28 09:02:43 PM UTC 24 167780963158 ps
T602 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_smoke.500484081 Aug 28 09:02:37 PM UTC 24 Aug 28 09:02:46 PM UTC 24 6207668687 ps
T382 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_fsm_reset.3653870262 Aug 28 08:49:53 PM UTC 24 Aug 28 09:02:47 PM UTC 24 130022716666 ps
T365 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_polled.1402515763 Aug 28 08:56:26 PM UTC 24 Aug 28 09:03:50 PM UTC 24 165870701047 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_polled.3238102012 Aug 28 09:00:15 PM UTC 24 Aug 28 09:03:55 PM UTC 24 330525659164 ps
T603 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_stress_all.3972336589 Aug 28 09:01:42 PM UTC 24 Aug 28 09:03:56 PM UTC 24 172224135967 ps
T343 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_stress_all.1046146957 Aug 28 08:56:13 PM UTC 24 Aug 28 09:04:12 PM UTC 24 512384345942 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_clock_gating.288740534 Aug 28 08:59:22 PM UTC 24 Aug 28 09:04:14 PM UTC 24 524228048351 ps
T604 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_poweron_counter.3220348824 Aug 28 09:04:13 PM UTC 24 Aug 28 09:04:18 PM UTC 24 3997156999 ps
T605 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_polled.1645116423 Aug 28 08:47:39 PM UTC 24 Aug 28 09:04:25 PM UTC 24 499652327959 ps
T606 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_interrupt.1252154191 Aug 28 08:49:07 PM UTC 24 Aug 28 09:04:26 PM UTC 24 332472365300 ps
T607 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_wakeup.2951070853 Aug 28 09:00:39 PM UTC 24 Aug 28 09:04:29 PM UTC 24 363538124662 ps
T346 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_both.4035789287 Aug 28 08:52:59 PM UTC 24 Aug 28 09:04:33 PM UTC 24 177194029336 ps
T608 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_alert_test.3994991012 Aug 28 09:04:30 PM UTC 24 Aug 28 09:04:33 PM UTC 24 321874469 ps
T609 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_smoke.1533533246 Aug 28 09:04:34 PM UTC 24 Aug 28 09:04:41 PM UTC 24 6220173228 ps
T610 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_lowpower_counter.1621780746 Aug 28 09:02:12 PM UTC 24 Aug 28 09:04:54 PM UTC 24 37705196841 ps
T350 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_polled.472345345 Aug 28 09:01:46 PM UTC 24 Aug 28 09:04:56 PM UTC 24 488848184892 ps
T611 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_stress_all.447612977 Aug 28 08:52:08 PM UTC 24 Aug 28 09:04:56 PM UTC 24 203345128451 ps
T612 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_clock_gating.780483346 Aug 28 09:02:07 PM UTC 24 Aug 28 09:05:07 PM UTC 24 177321013199 ps
T613 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_polled.2276515974 Aug 28 08:49:01 PM UTC 24 Aug 28 09:05:09 PM UTC 24 323572191850 ps
T614 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2116350823 Aug 28 09:04:26 PM UTC 24 Aug 28 09:05:11 PM UTC 24 5629806996 ps
T615 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_polled_fixed.1578732712 Aug 28 08:56:32 PM UTC 24 Aug 28 09:05:15 PM UTC 24 161049683758 ps