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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.76 99.07 96.67 100.00 100.00 98.83 98.33 91.42


Total test records in report: 919
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T354 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_wakeup.3101620012 Aug 28 09:21:34 PM UTC 24 Aug 28 09:52:20 PM UTC 24 542090202574 ps
T798 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_stress_all.290127254 Aug 28 09:22:25 PM UTC 24 Aug 28 09:52:21 PM UTC 24 516379475968 ps
T360 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_wakeup.308742742 Aug 28 09:20:04 PM UTC 24 Aug 28 09:55:49 PM UTC 24 554979247493 ps
T320 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_stress_all.3029895650 Aug 28 08:58:29 PM UTC 24 Aug 28 10:34:06 PM UTC 24 1848138435016 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3538220461 Aug 28 09:23:28 PM UTC 24 Aug 28 09:23:32 PM UTC 24 681319324 ps
T799 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.2813120008 Aug 28 09:23:30 PM UTC 24 Aug 28 09:23:33 PM UTC 24 293894297 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2898305423 Aug 28 09:23:32 PM UTC 24 Aug 28 09:23:35 PM UTC 24 1114780184 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.4223472701 Aug 28 09:23:28 PM UTC 24 Aug 28 09:23:37 PM UTC 24 4643125724 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2121579234 Aug 28 09:23:33 PM UTC 24 Aug 28 09:23:37 PM UTC 24 402737017 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.672946484 Aug 28 09:23:35 PM UTC 24 Aug 28 09:23:39 PM UTC 24 1004341218 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1836975861 Aug 28 09:23:37 PM UTC 24 Aug 28 09:23:42 PM UTC 24 2343404495 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3333021528 Aug 28 09:23:38 PM UTC 24 Aug 28 09:23:42 PM UTC 24 317756840 ps
T800 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.2396225321 Aug 28 09:23:41 PM UTC 24 Aug 28 09:23:43 PM UTC 24 569979719 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.4080303933 Aug 28 09:23:43 PM UTC 24 Aug 28 09:23:45 PM UTC 24 534191798 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.153168766 Aug 28 09:23:43 PM UTC 24 Aug 28 09:23:46 PM UTC 24 841891266 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1443751737 Aug 28 09:23:41 PM UTC 24 Aug 28 09:23:47 PM UTC 24 426594805 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2362337114 Aug 28 09:23:47 PM UTC 24 Aug 28 09:23:50 PM UTC 24 529370325 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1658727620 Aug 28 09:23:47 PM UTC 24 Aug 28 09:23:52 PM UTC 24 484391665 ps
T801 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.3645591550 Aug 28 09:23:49 PM UTC 24 Aug 28 09:23:53 PM UTC 24 394736924 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3483242442 Aug 28 09:23:50 PM UTC 24 Aug 28 09:23:53 PM UTC 24 698162163 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3142608023 Aug 28 09:23:46 PM UTC 24 Aug 28 09:23:54 PM UTC 24 1152922778 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.869981617 Aug 28 09:23:46 PM UTC 24 Aug 28 09:23:56 PM UTC 24 4286112399 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.4062560653 Aug 28 09:23:52 PM UTC 24 Aug 28 09:23:56 PM UTC 24 454520666 ps
T802 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3759303708 Aug 28 09:23:53 PM UTC 24 Aug 28 09:23:58 PM UTC 24 1221050825 ps
T803 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.1362713455 Aug 28 09:23:58 PM UTC 24 Aug 28 09:24:00 PM UTC 24 346387058 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3079210841 Aug 28 09:23:56 PM UTC 24 Aug 28 09:24:00 PM UTC 24 522378251 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1499587393 Aug 28 09:23:57 PM UTC 24 Aug 28 09:24:01 PM UTC 24 483325433 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2997190562 Aug 28 09:23:59 PM UTC 24 Aug 28 09:24:01 PM UTC 24 402349112 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3203212233 Aug 28 09:23:59 PM UTC 24 Aug 28 09:24:01 PM UTC 24 791814251 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3951207098 Aug 28 09:23:55 PM UTC 24 Aug 28 09:24:03 PM UTC 24 4304625145 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2290603649 Aug 28 09:24:02 PM UTC 24 Aug 28 09:24:06 PM UTC 24 474926908 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3224591386 Aug 28 09:24:02 PM UTC 24 Aug 28 09:24:06 PM UTC 24 4353937338 ps
T804 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_intr_test.3308482993 Aug 28 09:24:04 PM UTC 24 Aug 28 09:24:07 PM UTC 24 529005979 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_errors.632415706 Aug 28 09:24:02 PM UTC 24 Aug 28 09:24:07 PM UTC 24 966188144 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3506931208 Aug 28 09:24:01 PM UTC 24 Aug 28 09:24:09 PM UTC 24 901220368 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1417120409 Aug 28 09:24:08 PM UTC 24 Aug 28 09:24:11 PM UTC 24 323654854 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3999770745 Aug 28 09:23:41 PM UTC 24 Aug 28 09:24:11 PM UTC 24 8304014875 ps
T130 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3751656777 Aug 28 09:24:07 PM UTC 24 Aug 28 09:24:12 PM UTC 24 537115942 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.854344966 Aug 28 09:23:48 PM UTC 24 Aug 28 09:24:12 PM UTC 24 9203925101 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2549212501 Aug 28 09:24:07 PM UTC 24 Aug 28 09:24:12 PM UTC 24 886802476 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3670334815 Aug 28 09:24:07 PM UTC 24 Aug 28 09:24:15 PM UTC 24 1206036673 ps
T131 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3455355992 Aug 28 09:24:13 PM UTC 24 Aug 28 09:24:15 PM UTC 24 431201810 ps
T805 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3827134428 Aug 28 09:24:13 PM UTC 24 Aug 28 09:24:15 PM UTC 24 445133340 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3184915184 Aug 28 09:24:09 PM UTC 24 Aug 28 09:24:16 PM UTC 24 549038935 ps
T806 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_intr_test.2088475612 Aug 28 09:24:13 PM UTC 24 Aug 28 09:24:17 PM UTC 24 437623832 ps
T807 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_intr_test.3121272075 Aug 28 09:24:16 PM UTC 24 Aug 28 09:24:18 PM UTC 24 499712538 ps
T132 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2333152280 Aug 28 09:24:08 PM UTC 24 Aug 28 09:24:19 PM UTC 24 2176773779 ps
T369 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.419962733 Aug 28 09:23:57 PM UTC 24 Aug 28 09:24:19 PM UTC 24 8650415155 ps
T808 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_errors.905571118 Aug 28 09:24:16 PM UTC 24 Aug 28 09:24:20 PM UTC 24 494180075 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3594383256 Aug 28 09:24:13 PM UTC 24 Aug 28 09:24:20 PM UTC 24 4023491176 ps
T809 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1926376953 Aug 28 09:24:17 PM UTC 24 Aug 28 09:24:21 PM UTC 24 366339103 ps
T810 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3112668896 Aug 28 09:24:12 PM UTC 24 Aug 28 09:24:22 PM UTC 24 4584963447 ps
T811 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.994919348 Aug 28 09:24:19 PM UTC 24 Aug 28 09:24:23 PM UTC 24 390191332 ps
T812 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_intr_test.2847529448 Aug 28 09:24:21 PM UTC 24 Aug 28 09:24:24 PM UTC 24 348577813 ps
T371 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.795374278 Aug 28 09:24:16 PM UTC 24 Aug 28 09:24:24 PM UTC 24 4500102220 ps
T813 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_rw.492953055 Aug 28 09:24:21 PM UTC 24 Aug 28 09:24:25 PM UTC 24 548094792 ps
T814 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3780257108 Aug 28 09:24:23 PM UTC 24 Aug 28 09:24:26 PM UTC 24 520500612 ps
T815 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2117914967 Aug 28 09:24:20 PM UTC 24 Aug 28 09:24:26 PM UTC 24 561443746 ps
T816 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_intr_test.2829721323 Aug 28 09:24:24 PM UTC 24 Aug 28 09:24:27 PM UTC 24 625104904 ps
T817 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_rw.582992581 Aug 28 09:24:26 PM UTC 24 Aug 28 09:24:30 PM UTC 24 487208372 ps
T818 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_errors.514432503 Aug 28 09:24:23 PM UTC 24 Aug 28 09:24:30 PM UTC 24 437655729 ps
T819 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3402980279 Aug 28 09:24:17 PM UTC 24 Aug 28 09:24:30 PM UTC 24 2649228320 ps
T820 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1194494741 Aug 28 09:24:27 PM UTC 24 Aug 28 09:24:30 PM UTC 24 482258604 ps
T821 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1790011705 Aug 28 09:24:27 PM UTC 24 Aug 28 09:24:31 PM UTC 24 593083879 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2620402421 Aug 28 09:24:20 PM UTC 24 Aug 28 09:24:31 PM UTC 24 4196152424 ps
T822 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.235222215 Aug 28 09:24:21 PM UTC 24 Aug 28 09:24:31 PM UTC 24 2466092957 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1165662148 Aug 28 09:24:03 PM UTC 24 Aug 28 09:24:33 PM UTC 24 8563630885 ps
T823 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_intr_test.2311848038 Aug 28 09:24:31 PM UTC 24 Aug 28 09:24:34 PM UTC 24 287496982 ps
T824 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.274143268 Aug 28 09:24:31 PM UTC 24 Aug 28 09:24:34 PM UTC 24 617463895 ps
T825 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3130629761 Aug 28 09:24:31 PM UTC 24 Aug 28 09:24:34 PM UTC 24 490194249 ps
T826 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2415336544 Aug 28 09:24:32 PM UTC 24 Aug 28 09:24:36 PM UTC 24 512342845 ps
T827 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.4145308459 Aug 28 09:24:32 PM UTC 24 Aug 28 09:24:36 PM UTC 24 464590840 ps
T828 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2625153873 Aug 28 09:24:34 PM UTC 24 Aug 28 09:24:37 PM UTC 24 430472327 ps
T125 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.4141464110 Aug 28 09:23:34 PM UTC 24 Aug 28 09:24:39 PM UTC 24 14995414595 ps
T829 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.4248083246 Aug 28 09:24:35 PM UTC 24 Aug 28 09:24:40 PM UTC 24 573184479 ps
T830 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.653726997 Aug 28 09:24:38 PM UTC 24 Aug 28 09:24:40 PM UTC 24 390122496 ps
T831 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2152363593 Aug 28 09:24:35 PM UTC 24 Aug 28 09:24:41 PM UTC 24 434083415 ps
T832 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.533820784 Aug 28 09:24:28 PM UTC 24 Aug 28 09:24:41 PM UTC 24 4425907858 ps
T833 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.4085817345 Aug 28 09:24:32 PM UTC 24 Aug 28 09:24:41 PM UTC 24 4664913173 ps
T126 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3388133652 Aug 28 09:24:38 PM UTC 24 Aug 28 09:24:41 PM UTC 24 329277020 ps
T834 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.4114820883 Aug 28 09:24:41 PM UTC 24 Aug 28 09:24:43 PM UTC 24 597616714 ps
T835 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2092577361 Aug 28 09:24:42 PM UTC 24 Aug 28 09:24:45 PM UTC 24 407108371 ps
T836 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.615882053 Aug 28 09:24:41 PM UTC 24 Aug 28 09:24:45 PM UTC 24 464870271 ps
T837 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.3662392243 Aug 28 09:24:42 PM UTC 24 Aug 28 09:24:46 PM UTC 24 433969918 ps
T372 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3257760133 Aug 28 09:24:23 PM UTC 24 Aug 28 09:24:46 PM UTC 24 4159906643 ps
T838 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1413207605 Aug 28 09:24:40 PM UTC 24 Aug 28 09:24:46 PM UTC 24 2603028070 ps
T839 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1956670916 Aug 28 09:24:42 PM UTC 24 Aug 28 09:24:46 PM UTC 24 515519258 ps
T840 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3631433318 Aug 28 09:24:27 PM UTC 24 Aug 28 09:24:46 PM UTC 24 5127626981 ps
T841 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2678150388 Aug 28 09:24:44 PM UTC 24 Aug 28 09:24:48 PM UTC 24 409806316 ps
T842 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3518719796 Aug 28 09:24:35 PM UTC 24 Aug 28 09:24:49 PM UTC 24 2529104937 ps
T843 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.4014839420 Aug 28 09:24:46 PM UTC 24 Aug 28 09:24:49 PM UTC 24 430065274 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.636008325 Aug 28 09:24:46 PM UTC 24 Aug 28 09:24:49 PM UTC 24 304079640 ps
T844 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.904655637 Aug 28 09:24:47 PM UTC 24 Aug 28 09:24:50 PM UTC 24 330573285 ps
T845 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3293270219 Aug 28 09:24:36 PM UTC 24 Aug 28 09:24:51 PM UTC 24 4320748439 ps
T846 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3725237776 Aug 28 09:24:47 PM UTC 24 Aug 28 09:24:51 PM UTC 24 573838436 ps
T847 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.476348826 Aug 28 09:24:31 PM UTC 24 Aug 28 09:24:51 PM UTC 24 2744735786 ps
T848 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2707827203 Aug 28 09:24:50 PM UTC 24 Aug 28 09:24:52 PM UTC 24 578405200 ps
T849 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3988728844 Aug 28 09:24:51 PM UTC 24 Aug 28 09:24:53 PM UTC 24 506489703 ps
T850 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.2796894181 Aug 28 09:24:50 PM UTC 24 Aug 28 09:24:54 PM UTC 24 521092432 ps
T851 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1734014208 Aug 28 09:24:46 PM UTC 24 Aug 28 09:24:54 PM UTC 24 4129193722 ps
T852 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.309881636 Aug 28 09:24:42 PM UTC 24 Aug 28 09:24:55 PM UTC 24 2341504535 ps
T853 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.617051841 Aug 28 09:24:46 PM UTC 24 Aug 28 09:24:55 PM UTC 24 4940108476 ps
T854 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1009289916 Aug 28 09:24:51 PM UTC 24 Aug 28 09:24:55 PM UTC 24 330583221 ps
T855 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.176251375 Aug 28 09:24:53 PM UTC 24 Aug 28 09:24:56 PM UTC 24 558097895 ps
T856 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.4168227651 Aug 28 09:24:52 PM UTC 24 Aug 28 09:24:56 PM UTC 24 484632084 ps
T857 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.4115347030 Aug 28 09:24:52 PM UTC 24 Aug 28 09:24:56 PM UTC 24 501599182 ps
T858 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.2624745299 Aug 28 09:24:55 PM UTC 24 Aug 28 09:24:57 PM UTC 24 293728434 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2416892649 Aug 28 09:24:55 PM UTC 24 Aug 28 09:24:59 PM UTC 24 497795690 ps
T859 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3593798828 Aug 28 09:24:54 PM UTC 24 Aug 28 09:24:59 PM UTC 24 504532631 ps
T860 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2057965993 Aug 28 09:24:56 PM UTC 24 Aug 28 09:24:59 PM UTC 24 311939364 ps
T861 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.252216639 Aug 28 09:24:52 PM UTC 24 Aug 28 09:25:00 PM UTC 24 2467475932 ps
T862 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.107162429 Aug 28 09:24:56 PM UTC 24 Aug 28 09:25:00 PM UTC 24 495336485 ps
T863 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1315469500 Aug 28 09:24:55 PM UTC 24 Aug 28 09:25:00 PM UTC 24 2109533824 ps
T864 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.488731297 Aug 28 09:24:58 PM UTC 24 Aug 28 09:25:01 PM UTC 24 541631762 ps
T865 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2382996212 Aug 28 09:24:59 PM UTC 24 Aug 28 09:25:02 PM UTC 24 557355817 ps
T866 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1112952569 Aug 28 09:25:00 PM UTC 24 Aug 28 09:25:03 PM UTC 24 546166143 ps
T867 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1107630953 Aug 28 09:25:00 PM UTC 24 Aug 28 09:25:03 PM UTC 24 2343492391 ps
T868 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.4187068288 Aug 28 09:25:00 PM UTC 24 Aug 28 09:25:03 PM UTC 24 483561040 ps
T869 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.401641725 Aug 28 09:25:01 PM UTC 24 Aug 28 09:25:03 PM UTC 24 324218502 ps
T870 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2015156137 Aug 28 09:25:01 PM UTC 24 Aug 28 09:25:03 PM UTC 24 460027705 ps
T871 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2657843345 Aug 28 09:24:50 PM UTC 24 Aug 28 09:25:03 PM UTC 24 2279059559 ps
T872 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1709139716 Aug 28 09:24:54 PM UTC 24 Aug 28 09:25:03 PM UTC 24 4446031804 ps
T873 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1830636745 Aug 28 09:25:01 PM UTC 24 Aug 28 09:25:05 PM UTC 24 2368391730 ps
T874 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.859899984 Aug 28 09:25:03 PM UTC 24 Aug 28 09:25:05 PM UTC 24 497163096 ps
T875 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2289866390 Aug 28 09:25:02 PM UTC 24 Aug 28 09:25:05 PM UTC 24 498222581 ps
T876 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3558145027 Aug 28 09:25:02 PM UTC 24 Aug 28 09:25:06 PM UTC 24 651457286 ps
T877 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.926806321 Aug 28 09:25:04 PM UTC 24 Aug 28 09:25:07 PM UTC 24 407282856 ps
T878 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.3255028661 Aug 28 09:25:04 PM UTC 24 Aug 28 09:25:07 PM UTC 24 410787976 ps
T879 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.273127309 Aug 28 09:25:04 PM UTC 24 Aug 28 09:25:07 PM UTC 24 461525754 ps
T880 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2627858104 Aug 28 09:24:52 PM UTC 24 Aug 28 09:25:08 PM UTC 24 8252689269 ps
T881 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.520144773 Aug 28 09:25:04 PM UTC 24 Aug 28 09:25:08 PM UTC 24 524059687 ps
T882 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.543887669 Aug 28 09:25:06 PM UTC 24 Aug 28 09:25:08 PM UTC 24 501571371 ps
T883 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.56251169 Aug 28 09:25:04 PM UTC 24 Aug 28 09:25:08 PM UTC 24 383915701 ps
T884 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.4048051764 Aug 28 09:25:06 PM UTC 24 Aug 28 09:25:09 PM UTC 24 502708896 ps
T885 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.384893800 Aug 28 09:25:07 PM UTC 24 Aug 28 09:25:09 PM UTC 24 510842886 ps
T886 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.1534825237 Aug 28 09:25:08 PM UTC 24 Aug 28 09:25:10 PM UTC 24 412615624 ps
T887 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.249433024 Aug 28 09:25:08 PM UTC 24 Aug 28 09:25:10 PM UTC 24 338469523 ps
T888 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/30.adc_ctrl_intr_test.2565200623 Aug 28 09:25:08 PM UTC 24 Aug 28 09:25:11 PM UTC 24 456553972 ps
T889 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.349565986 Aug 28 09:25:07 PM UTC 24 Aug 28 09:25:11 PM UTC 24 508808123 ps
T890 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1524923851 Aug 28 09:24:47 PM UTC 24 Aug 28 09:25:11 PM UTC 24 4598297055 ps
T891 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.1352704081 Aug 28 09:25:08 PM UTC 24 Aug 28 09:25:11 PM UTC 24 355118475 ps
T892 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/31.adc_ctrl_intr_test.3264981381 Aug 28 09:25:09 PM UTC 24 Aug 28 09:25:11 PM UTC 24 466023847 ps
T893 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2858234457 Aug 28 09:24:41 PM UTC 24 Aug 28 09:25:11 PM UTC 24 7455146699 ps
T894 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/35.adc_ctrl_intr_test.2296624975 Aug 28 09:25:09 PM UTC 24 Aug 28 09:25:12 PM UTC 24 556138785 ps
T895 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/32.adc_ctrl_intr_test.2189218799 Aug 28 09:25:09 PM UTC 24 Aug 28 09:25:12 PM UTC 24 483527908 ps
T896 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1756584753 Aug 28 09:24:56 PM UTC 24 Aug 28 09:25:12 PM UTC 24 4542551380 ps
T897 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/37.adc_ctrl_intr_test.3479831290 Aug 28 09:25:10 PM UTC 24 Aug 28 09:25:13 PM UTC 24 548539050 ps
T898 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/33.adc_ctrl_intr_test.4258935628 Aug 28 09:25:09 PM UTC 24 Aug 28 09:25:13 PM UTC 24 414055220 ps
T899 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/34.adc_ctrl_intr_test.2043203989 Aug 28 09:25:09 PM UTC 24 Aug 28 09:25:13 PM UTC 24 407255757 ps
T900 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/36.adc_ctrl_intr_test.3127840169 Aug 28 09:25:10 PM UTC 24 Aug 28 09:25:14 PM UTC 24 406928354 ps
T901 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/39.adc_ctrl_intr_test.830079353 Aug 28 09:25:11 PM UTC 24 Aug 28 09:25:14 PM UTC 24 565276051 ps
T902 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/40.adc_ctrl_intr_test.3301323109 Aug 28 09:25:11 PM UTC 24 Aug 28 09:25:14 PM UTC 24 504594840 ps
T903 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/38.adc_ctrl_intr_test.855372554 Aug 28 09:25:10 PM UTC 24 Aug 28 09:25:14 PM UTC 24 483450231 ps
T904 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/41.adc_ctrl_intr_test.496484469 Aug 28 09:25:13 PM UTC 24 Aug 28 09:25:15 PM UTC 24 499559829 ps
T905 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/44.adc_ctrl_intr_test.256865114 Aug 28 09:25:13 PM UTC 24 Aug 28 09:25:15 PM UTC 24 523463845 ps
T906 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/43.adc_ctrl_intr_test.4206792327 Aug 28 09:25:13 PM UTC 24 Aug 28 09:25:15 PM UTC 24 444959945 ps
T907 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/45.adc_ctrl_intr_test.1208829766 Aug 28 09:25:13 PM UTC 24 Aug 28 09:25:15 PM UTC 24 408022954 ps
T908 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/42.adc_ctrl_intr_test.350206530 Aug 28 09:25:13 PM UTC 24 Aug 28 09:25:15 PM UTC 24 389766439 ps
T909 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/48.adc_ctrl_intr_test.3962786584 Aug 28 09:25:14 PM UTC 24 Aug 28 09:25:16 PM UTC 24 429726834 ps
T910 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/49.adc_ctrl_intr_test.2929076715 Aug 28 09:25:14 PM UTC 24 Aug 28 09:25:16 PM UTC 24 346754770 ps
T911 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/46.adc_ctrl_intr_test.394747362 Aug 28 09:25:13 PM UTC 24 Aug 28 09:25:16 PM UTC 24 446563295 ps
T912 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/47.adc_ctrl_intr_test.3004913936 Aug 28 09:25:14 PM UTC 24 Aug 28 09:25:16 PM UTC 24 454033891 ps
T913 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3039972591 Aug 28 09:25:03 PM UTC 24 Aug 28 09:25:16 PM UTC 24 8382947063 ps
T914 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2197511116 Aug 28 09:25:04 PM UTC 24 Aug 28 09:25:22 PM UTC 24 2178570394 ps
T915 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.4180380605 Aug 28 09:24:07 PM UTC 24 Aug 28 09:25:32 PM UTC 24 26804769642 ps
T916 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1055618387 Aug 28 09:25:00 PM UTC 24 Aug 28 09:25:34 PM UTC 24 8792504057 ps
T917 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.734474856 Aug 28 09:24:01 PM UTC 24 Aug 28 09:26:48 PM UTC 24 52837453816 ps
T918 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1532708759 Aug 28 09:23:53 PM UTC 24 Aug 28 09:26:51 PM UTC 24 27312199829 ps
T919 /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1563116289 Aug 28 09:23:44 PM UTC 24 Aug 28 09:26:56 PM UTC 24 26990112137 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.882870214
Short name T8
Test name
Test status
Simulation time 26229715755 ps
CPU time 7.52 seconds
Started Aug 28 08:12:27 PM UTC 24
Finished Aug 28 08:12:35 PM UTC 24
Peak memory 221888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=882870214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
1.adc_ctrl_stress_all_with_rand_reset.882870214
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.110937521
Short name T14
Test name
Test status
Simulation time 37302249506 ps
CPU time 38.74 seconds
Started Aug 28 08:13:03 PM UTC 24
Finished Aug 28 08:13:43 PM UTC 24
Peak memory 222016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=110937521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
2.adc_ctrl_stress_all_with_rand_reset.110937521
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all.1368959207
Short name T56
Test name
Test status
Simulation time 415199759969 ps
CPU time 622.27 seconds
Started Aug 28 08:12:12 PM UTC 24
Finished Aug 28 08:22:41 PM UTC 24
Peak memory 212896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368959207 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.1368959207
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt.802382470
Short name T19
Test name
Test status
Simulation time 331503639653 ps
CPU time 111.7 seconds
Started Aug 28 08:13:50 PM UTC 24
Finished Aug 28 08:15:44 PM UTC 24
Peak memory 211556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802382470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.802382470
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/4.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_fsm_reset.2841161129
Short name T55
Test name
Test status
Simulation time 63154866707 ps
CPU time 483.52 seconds
Started Aug 28 08:12:11 PM UTC 24
Finished Aug 28 08:20:21 PM UTC 24
Peak memory 211760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841161129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.2841161129
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/0.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.1894260604
Short name T137
Test name
Test status
Simulation time 550716848127 ps
CPU time 483.52 seconds
Started Aug 28 08:12:20 PM UTC 24
Finished Aug 28 08:20:29 PM UTC 24
Peak memory 211812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894260604 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gating.1894260604
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/1.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.2967525396
Short name T166
Test name
Test status
Simulation time 513974766554 ps
CPU time 1343.93 seconds
Started Aug 28 08:13:35 PM UTC 24
Finished Aug 28 08:36:11 PM UTC 24
Peak memory 212820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967525396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.2967525396
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/3.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2535091286
Short name T18
Test name
Test status
Simulation time 79628749164 ps
CPU time 38.26 seconds
Started Aug 28 08:14:17 PM UTC 24
Finished Aug 28 08:14:56 PM UTC 24
Peak memory 222160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2535091286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.adc_ctrl_stress_all_with_rand_reset.2535091286
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup.4033215602
Short name T136
Test name
Test status
Simulation time 537073403848 ps
CPU time 324 seconds
Started Aug 28 08:14:55 PM UTC 24
Finished Aug 28 08:20:23 PM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033215602 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_wakeup.4033215602
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/5.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1094347849
Short name T12
Test name
Test status
Simulation time 484221777364 ps
CPU time 82.11 seconds
Started Aug 28 08:12:10 PM UTC 24
Finished Aug 28 08:13:34 PM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094347849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt_fixed.1094347849
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_both.1068260737
Short name T229
Test name
Test status
Simulation time 512305149766 ps
CPU time 455.37 seconds
Started Aug 28 08:18:51 PM UTC 24
Finished Aug 28 08:26:31 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068260737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.1068260737
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/8.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all.385475463
Short name T237
Test name
Test status
Simulation time 529547178002 ps
CPU time 285.89 seconds
Started Aug 28 08:34:05 PM UTC 24
Finished Aug 28 08:38:54 PM UTC 24
Peak memory 211680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385475463 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.385475463
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/16.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.261542441
Short name T21
Test name
Test status
Simulation time 4151541313 ps
CPU time 18.6 seconds
Started Aug 28 08:12:12 PM UTC 24
Finished Aug 28 08:12:33 PM UTC 24
Peak memory 243560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261542441 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.261542441
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/0.adc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1658727620
Short name T74
Test name
Test status
Simulation time 484391665 ps
CPU time 3.73 seconds
Started Aug 28 09:23:47 PM UTC 24
Finished Aug 28 09:23:52 PM UTC 24
Peak memory 221316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658727620 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1658727620
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/2.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_both.1724010478
Short name T153
Test name
Test status
Simulation time 331975151738 ps
CPU time 556.3 seconds
Started Aug 28 08:16:16 PM UTC 24
Finished Aug 28 08:25:38 PM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724010478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.1724010478
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/6.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_clock_gating.2358821102
Short name T107
Test name
Test status
Simulation time 540730776457 ps
CPU time 715.63 seconds
Started Aug 28 08:30:04 PM UTC 24
Finished Aug 28 08:42:07 PM UTC 24
Peak memory 211612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358821102 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gating.2358821102
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/15.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.4227129939
Short name T238
Test name
Test status
Simulation time 86055574648 ps
CPU time 46.29 seconds
Started Aug 28 08:35:14 PM UTC 24
Finished Aug 28 08:36:02 PM UTC 24
Peak memory 222024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=4227129939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.adc_ctrl_stress_all_with_rand_reset.4227129939
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt.2377243826
Short name T233
Test name
Test status
Simulation time 485746169949 ps
CPU time 485.94 seconds
Started Aug 28 08:18:16 PM UTC 24
Finished Aug 28 08:26:27 PM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377243826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2377243826
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/8.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_clock_gating.4270390387
Short name T270
Test name
Test status
Simulation time 523368381763 ps
CPU time 1355.48 seconds
Started Aug 28 08:16:11 PM UTC 24
Finished Aug 28 08:39:00 PM UTC 24
Peak memory 212496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270390387 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gating.4270390387
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/6.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all.562452818
Short name T241
Test name
Test status
Simulation time 352021327655 ps
CPU time 586.13 seconds
Started Aug 28 08:25:51 PM UTC 24
Finished Aug 28 08:35:43 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562452818 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.562452818
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/12.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2121579234
Short name T115
Test name
Test status
Simulation time 402737017 ps
CPU time 3.05 seconds
Started Aug 28 09:23:33 PM UTC 24
Finished Aug 28 09:23:37 PM UTC 24
Peak memory 211272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121579234 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2121579234
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/0.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.3216030578
Short name T234
Test name
Test status
Simulation time 321740454748 ps
CPU time 1032.69 seconds
Started Aug 28 08:12:48 PM UTC 24
Finished Aug 28 08:30:11 PM UTC 24
Peak memory 212628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216030578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3216030578
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/2.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt.4112496449
Short name T250
Test name
Test status
Simulation time 493996725697 ps
CPU time 1230.69 seconds
Started Aug 28 08:12:36 PM UTC 24
Finished Aug 28 08:33:19 PM UTC 24
Peak memory 212884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112496449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.4112496449
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/2.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_both.3553418896
Short name T224
Test name
Test status
Simulation time 334733767198 ps
CPU time 340.42 seconds
Started Aug 28 08:28:16 PM UTC 24
Finished Aug 28 08:34:01 PM UTC 24
Peak memory 211556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553418896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3553418896
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/14.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all.438928991
Short name T246
Test name
Test status
Simulation time 642507384924 ps
CPU time 1299.25 seconds
Started Aug 28 08:15:24 PM UTC 24
Finished Aug 28 08:37:16 PM UTC 24
Peak memory 212828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438928991 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.438928991
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_wakeup.1910191850
Short name T177
Test name
Test status
Simulation time 441418687545 ps
CPU time 671.36 seconds
Started Aug 28 08:41:55 PM UTC 24
Finished Aug 28 08:53:13 PM UTC 24
Peak memory 211804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910191850 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_wakeup.1910191850
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/22.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_both.2584959317
Short name T296
Test name
Test status
Simulation time 512767620336 ps
CPU time 1345.2 seconds
Started Aug 28 08:55:36 PM UTC 24
Finished Aug 28 09:18:14 PM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584959317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2584959317
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/31.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_clock_gating.567265857
Short name T262
Test name
Test status
Simulation time 333427269481 ps
CPU time 636.2 seconds
Started Aug 28 08:42:08 PM UTC 24
Finished Aug 28 08:52:51 PM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567265857 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gating.567265857
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/22.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup.2736636748
Short name T316
Test name
Test status
Simulation time 516832975753 ps
CPU time 702.08 seconds
Started Aug 28 08:34:32 PM UTC 24
Finished Aug 28 08:46:22 PM UTC 24
Peak memory 211528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736636748 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_wakeup.2736636748
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/17.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled.720886218
Short name T150
Test name
Test status
Simulation time 322289984630 ps
CPU time 256.79 seconds
Started Aug 28 08:12:15 PM UTC 24
Finished Aug 28 08:16:35 PM UTC 24
Peak memory 211620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720886218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.720886218
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/1.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_both.371266774
Short name T247
Test name
Test status
Simulation time 507928517421 ps
CPU time 1428.87 seconds
Started Aug 28 08:14:07 PM UTC 24
Finished Aug 28 08:38:10 PM UTC 24
Peak memory 212548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371266774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.371266774
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/4.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3999770745
Short name T67
Test name
Test status
Simulation time 8304014875 ps
CPU time 29.54 seconds
Started Aug 28 09:23:41 PM UTC 24
Finished Aug 28 09:24:11 PM UTC 24
Peak memory 211528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999770745 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_intg_err.3999770745
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/1.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.1687789569
Short name T1
Test name
Test status
Simulation time 480594403 ps
CPU time 1.2 seconds
Started Aug 28 08:12:13 PM UTC 24
Finished Aug 28 08:12:16 PM UTC 24
Peak memory 210696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687789569 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.1687789569
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/0.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all.326460324
Short name T265
Test name
Test status
Simulation time 444595497205 ps
CPU time 1714.13 seconds
Started Aug 28 08:18:04 PM UTC 24
Finished Aug 28 08:46:55 PM UTC 24
Peak memory 229360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326460324 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.326460324
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.4141464110
Short name T125
Test name
Test status
Simulation time 14995414595 ps
CPU time 63.1 seconds
Started Aug 28 09:23:34 PM UTC 24
Finished Aug 28 09:24:39 PM UTC 24
Peak memory 211516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141464110 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_bash.4141464110
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/0.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.1895175841
Short name T220
Test name
Test status
Simulation time 332050995480 ps
CPU time 648.85 seconds
Started Aug 28 08:12:28 PM UTC 24
Finished Aug 28 08:23:23 PM UTC 24
Peak memory 212940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895175841 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.1895175841
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_clock_gating.3443848357
Short name T242
Test name
Test status
Simulation time 164160659613 ps
CPU time 141.84 seconds
Started Aug 28 08:57:25 PM UTC 24
Finished Aug 28 08:59:49 PM UTC 24
Peak memory 211616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443848357 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gating.3443848357
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/32.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_clock_gating.1347557212
Short name T200
Test name
Test status
Simulation time 366640126167 ps
CPU time 931.98 seconds
Started Aug 28 08:33:20 PM UTC 24
Finished Aug 28 08:49:00 PM UTC 24
Peak memory 212556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347557212 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gating.1347557212
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/16.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_both.1323414069
Short name T53
Test name
Test status
Simulation time 332514747077 ps
CPU time 238.24 seconds
Started Aug 28 08:12:22 PM UTC 24
Finished Aug 28 08:16:24 PM UTC 24
Peak memory 211728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323414069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.1323414069
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/1.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_wakeup.308742742
Short name T360
Test name
Test status
Simulation time 554979247493 ps
CPU time 2121.57 seconds
Started Aug 28 09:20:04 PM UTC 24
Finished Aug 28 09:55:49 PM UTC 24
Peak memory 212612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308742742 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_wakeup.308742742
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/47.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.4096975790
Short name T157
Test name
Test status
Simulation time 160328650815 ps
CPU time 112 seconds
Started Aug 28 08:15:53 PM UTC 24
Finished Aug 28 08:17:47 PM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096975790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.4096975790
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/6.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.3895472511
Short name T171
Test name
Test status
Simulation time 191499337948 ps
CPU time 76.04 seconds
Started Aug 28 08:44:31 PM UTC 24
Finished Aug 28 08:45:49 PM UTC 24
Peak memory 223664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3895472511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 23.adc_ctrl_stress_all_with_rand_reset.3895472511
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_clock_gating.3195752565
Short name T297
Test name
Test status
Simulation time 572926424871 ps
CPU time 294.48 seconds
Started Aug 28 09:20:08 PM UTC 24
Finished Aug 28 09:25:06 PM UTC 24
Peak memory 211868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195752565 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gating.3195752565
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/47.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup.911057519
Short name T329
Test name
Test status
Simulation time 176138309945 ps
CPU time 312.23 seconds
Started Aug 28 08:32:05 PM UTC 24
Finished Aug 28 08:37:21 PM UTC 24
Peak memory 211536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911057519 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_wakeup.911057519
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/16.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2943038010
Short name T334
Test name
Test status
Simulation time 15278566096 ps
CPU time 23.46 seconds
Started Aug 28 08:50:10 PM UTC 24
Finished Aug 28 08:50:35 PM UTC 24
Peak memory 221676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2943038010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 27.adc_ctrl_stress_all_with_rand_reset.2943038010
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2479745404
Short name T135
Test name
Test status
Simulation time 620919348563 ps
CPU time 460.59 seconds
Started Aug 28 08:12:10 PM UTC 24
Finished Aug 28 08:19:56 PM UTC 24
Peak memory 212660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479745404 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_wakeup_fixed.2479745404
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.254759105
Short name T302
Test name
Test status
Simulation time 76123893419 ps
CPU time 46.6 seconds
Started Aug 28 08:53:15 PM UTC 24
Finished Aug 28 08:54:03 PM UTC 24
Peak memory 228108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=254759105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
29.adc_ctrl_stress_all_with_rand_reset.254759105
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_stress_all.2769429961
Short name T279
Test name
Test status
Simulation time 351635656536 ps
CPU time 1105.28 seconds
Started Aug 28 08:48:52 PM UTC 24
Finished Aug 28 09:07:29 PM UTC 24
Peak memory 212548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769429961 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.2769429961
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/26.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all.1017372125
Short name T348
Test name
Test status
Simulation time 446477628444 ps
CPU time 1280.1 seconds
Started Aug 28 08:28:50 PM UTC 24
Finished Aug 28 08:50:22 PM UTC 24
Peak memory 222840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017372125 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.1017372125
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/14.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all.2750798407
Short name T99
Test name
Test status
Simulation time 325702736608 ps
CPU time 583.84 seconds
Started Aug 28 08:39:43 PM UTC 24
Finished Aug 28 08:49:34 PM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750798407 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.2750798407
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/20.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_interrupt.1055708455
Short name T317
Test name
Test status
Simulation time 325150441871 ps
CPU time 115.47 seconds
Started Aug 28 08:56:45 PM UTC 24
Finished Aug 28 08:58:42 PM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055708455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.1055708455
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/32.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.4081190971
Short name T274
Test name
Test status
Simulation time 2509257346 ps
CPU time 10.93 seconds
Started Aug 28 08:28:39 PM UTC 24
Finished Aug 28 08:28:51 PM UTC 24
Peak memory 211404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=4081190971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.adc_ctrl_stress_all_with_rand_reset.4081190971
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_clock_gating.1964242751
Short name T325
Test name
Test status
Simulation time 334391801393 ps
CPU time 1033.94 seconds
Started Aug 28 08:49:34 PM UTC 24
Finished Aug 28 09:06:59 PM UTC 24
Peak memory 212688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964242751 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gating.1964242751
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/27.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_interrupt.826772388
Short name T304
Test name
Test status
Simulation time 336722655493 ps
CPU time 958.53 seconds
Started Aug 28 08:52:16 PM UTC 24
Finished Aug 28 09:08:24 PM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826772388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.826772388
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/29.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_poweron_counter.1504962768
Short name T2
Test name
Test status
Simulation time 5703901568 ps
CPU time 4.59 seconds
Started Aug 28 08:12:11 PM UTC 24
Finished Aug 28 08:12:17 PM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504962768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.1504962768
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/0.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_fsm_reset.3497927828
Short name T60
Test name
Test status
Simulation time 127276407844 ps
CPU time 462.26 seconds
Started Aug 28 08:12:26 PM UTC 24
Finished Aug 28 08:20:14 PM UTC 24
Peak memory 211760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497927828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.3497927828
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/1.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_clock_gating.63958427
Short name T301
Test name
Test status
Simulation time 363193233549 ps
CPU time 820.64 seconds
Started Aug 28 08:37:40 PM UTC 24
Finished Aug 28 08:51:29 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63958427 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gating.63958427
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/19.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_wakeup.2824421629
Short name T273
Test name
Test status
Simulation time 529696619754 ps
CPU time 687.53 seconds
Started Aug 28 08:40:36 PM UTC 24
Finished Aug 28 08:52:11 PM UTC 24
Peak memory 211544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824421629 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_wakeup.2824421629
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/21.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_both.3656299847
Short name T219
Test name
Test status
Simulation time 508492296592 ps
CPU time 1648.12 seconds
Started Aug 28 09:08:42 PM UTC 24
Finished Aug 28 09:36:28 PM UTC 24
Peak memory 212524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656299847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3656299847
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/39.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1165662148
Short name T79
Test name
Test status
Simulation time 8563630885 ps
CPU time 28.92 seconds
Started Aug 28 09:24:03 PM UTC 24
Finished Aug 28 09:24:33 PM UTC 24
Peak memory 211608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165662148 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_intg_err.1165662148
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/4.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all.877891769
Short name T305
Test name
Test status
Simulation time 453617980701 ps
CPU time 708.46 seconds
Started Aug 28 08:27:41 PM UTC 24
Finished Aug 28 08:39:35 PM UTC 24
Peak memory 223884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877891769 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.877891769
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/13.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_interrupt.1128941004
Short name T263
Test name
Test status
Simulation time 327124520882 ps
CPU time 730.77 seconds
Started Aug 28 08:43:55 PM UTC 24
Finished Aug 28 08:56:14 PM UTC 24
Peak memory 211692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128941004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.1128941004
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/23.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_wakeup.2348048208
Short name T326
Test name
Test status
Simulation time 540370027119 ps
CPU time 1773.79 seconds
Started Aug 28 08:46:42 PM UTC 24
Finished Aug 28 09:16:34 PM UTC 24
Peak memory 212872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348048208 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_wakeup.2348048208
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/25.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2199111748
Short name T362
Test name
Test status
Simulation time 15023697149 ps
CPU time 16.74 seconds
Started Aug 28 09:12:01 PM UTC 24
Finished Aug 28 09:12:19 PM UTC 24
Peak memory 228036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2199111748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 41.adc_ctrl_stress_all_with_rand_reset.2199111748
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.2260330150
Short name T189
Test name
Test status
Simulation time 166943771896 ps
CPU time 108.25 seconds
Started Aug 28 08:21:43 PM UTC 24
Finished Aug 28 08:23:33 PM UTC 24
Peak memory 211692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260330150 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gating.2260330150
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/10.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_clock_gating.3703948261
Short name T294
Test name
Test status
Simulation time 179579664633 ps
CPU time 311.54 seconds
Started Aug 28 08:46:55 PM UTC 24
Finished Aug 28 08:52:10 PM UTC 24
Peak memory 211616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703948261 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gating.3703948261
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/25.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2819299886
Short name T272
Test name
Test status
Simulation time 8924513243 ps
CPU time 10.73 seconds
Started Aug 28 08:47:24 PM UTC 24
Finished Aug 28 08:47:36 PM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2819299886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 25.adc_ctrl_stress_all_with_rand_reset.2819299886
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_clock_gating.1921394534
Short name T333
Test name
Test status
Simulation time 175414836196 ps
CPU time 170.14 seconds
Started Aug 28 08:52:52 PM UTC 24
Finished Aug 28 08:55:45 PM UTC 24
Peak memory 211560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921394534 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gating.1921394534
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/29.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.1601818202
Short name T35
Test name
Test status
Simulation time 728690460995 ps
CPU time 60.08 seconds
Started Aug 28 08:56:10 PM UTC 24
Finished Aug 28 08:57:12 PM UTC 24
Peak memory 228168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1601818202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 31.adc_ctrl_stress_all_with_rand_reset.1601818202
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_stress_all.4148301311
Short name T271
Test name
Test status
Simulation time 1347101004424 ps
CPU time 1386.57 seconds
Started Aug 28 09:02:27 PM UTC 24
Finished Aug 28 09:25:47 PM UTC 24
Peak memory 225048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148301311 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.4148301311
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/35.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_clock_gating.56451080
Short name T284
Test name
Test status
Simulation time 518079005180 ps
CPU time 611.86 seconds
Started Aug 28 09:19:01 PM UTC 24
Finished Aug 28 09:29:20 PM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56451080 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gating.56451080
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/46.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt.297449106
Short name T217
Test name
Test status
Simulation time 329766283708 ps
CPU time 860.24 seconds
Started Aug 28 09:22:37 PM UTC 24
Finished Aug 28 09:37:06 PM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297449106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.297449106
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/49.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.352085343
Short name T255
Test name
Test status
Simulation time 389395303672 ps
CPU time 953.29 seconds
Started Aug 28 08:21:25 PM UTC 24
Finished Aug 28 08:37:27 PM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352085343 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_wakeup.352085343
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/10.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_fsm_reset.1759991229
Short name T375
Test name
Test status
Simulation time 76706615946 ps
CPU time 411.35 seconds
Started Aug 28 08:23:34 PM UTC 24
Finished Aug 28 08:30:30 PM UTC 24
Peak memory 211888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759991229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.1759991229
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/11.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_both.3959534631
Short name T240
Test name
Test status
Simulation time 164307732968 ps
CPU time 167.98 seconds
Started Aug 28 08:25:18 PM UTC 24
Finished Aug 28 08:28:09 PM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959534631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3959534631
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/12.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_polled.3238102012
Short name T276
Test name
Test status
Simulation time 330525659164 ps
CPU time 216.55 seconds
Started Aug 28 09:00:15 PM UTC 24
Finished Aug 28 09:03:55 PM UTC 24
Peak memory 211560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238102012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.3238102012
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/34.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_polled.843590067
Short name T291
Test name
Test status
Simulation time 486262988855 ps
CPU time 656.11 seconds
Started Aug 28 09:02:40 PM UTC 24
Finished Aug 28 09:13:43 PM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843590067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.843590067
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/36.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_polled.1084760183
Short name T199
Test name
Test status
Simulation time 489668497405 ps
CPU time 401.98 seconds
Started Aug 28 09:04:34 PM UTC 24
Finished Aug 28 09:11:20 PM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084760183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1084760183
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/37.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1620987031
Short name T243
Test name
Test status
Simulation time 911269425537 ps
CPU time 83.39 seconds
Started Aug 28 09:09:19 PM UTC 24
Finished Aug 28 09:10:44 PM UTC 24
Peak memory 228140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1620987031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 39.adc_ctrl_stress_all_with_rand_reset.1620987031
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_polled.3102030893
Short name T88
Test name
Test status
Simulation time 497386901445 ps
CPU time 308.8 seconds
Started Aug 28 09:09:39 PM UTC 24
Finished Aug 28 09:14:51 PM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102030893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3102030893
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/40.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2415336544
Short name T826
Test name
Test status
Simulation time 512342845 ps
CPU time 2.09 seconds
Started Aug 28 09:24:32 PM UTC 24
Finished Aug 28 09:24:36 PM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415336544 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2415336544
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/10.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all.2191717228
Short name T283
Test name
Test status
Simulation time 476874548201 ps
CPU time 1842.55 seconds
Started Aug 28 08:22:16 PM UTC 24
Finished Aug 28 08:53:16 PM UTC 24
Peak memory 223116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191717228 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.2191717228
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/10.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.3185401622
Short name T225
Test name
Test status
Simulation time 158799936168 ps
CPU time 32.97 seconds
Started Aug 28 08:25:15 PM UTC 24
Finished Aug 28 08:25:50 PM UTC 24
Peak memory 211616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185401622 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gating.3185401622
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/12.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_fsm_reset.2082356345
Short name T374
Test name
Test status
Simulation time 76173669956 ps
CPU time 398.66 seconds
Started Aug 28 08:28:30 PM UTC 24
Finished Aug 28 08:35:14 PM UTC 24
Peak memory 211884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082356345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.2082356345
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/14.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_wakeup.1534862069
Short name T332
Test name
Test status
Simulation time 184955963928 ps
CPU time 479.76 seconds
Started Aug 28 08:36:03 PM UTC 24
Finished Aug 28 08:44:08 PM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534862069 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_wakeup.1534862069
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/18.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_fsm_reset.748295309
Short name T390
Test name
Test status
Simulation time 126961513905 ps
CPU time 545.52 seconds
Started Aug 28 08:38:06 PM UTC 24
Finished Aug 28 08:47:17 PM UTC 24
Peak memory 211808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748295309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.748295309
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/19.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_fsm_reset.3300648722
Short name T59
Test name
Test status
Simulation time 99453738075 ps
CPU time 727.13 seconds
Started Aug 28 08:12:59 PM UTC 24
Finished Aug 28 08:25:13 PM UTC 24
Peak memory 211764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300648722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3300648722
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/2.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_interrupt.849537607
Short name T100
Test name
Test status
Simulation time 333664307017 ps
CPU time 561.56 seconds
Started Aug 28 08:40:08 PM UTC 24
Finished Aug 28 08:49:35 PM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849537607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.849537607
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/21.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_fsm_reset.3313653821
Short name T381
Test name
Test status
Simulation time 142574132666 ps
CPU time 525.24 seconds
Started Aug 28 08:44:28 PM UTC 24
Finished Aug 28 08:53:19 PM UTC 24
Peak memory 211756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313653821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.3313653821
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/23.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_fsm_reset.3653870262
Short name T382
Test name
Test status
Simulation time 130022716666 ps
CPU time 765.88 seconds
Started Aug 28 08:49:53 PM UTC 24
Finished Aug 28 09:02:47 PM UTC 24
Peak memory 211888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653870262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3653870262
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/27.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_both.285479830
Short name T314
Test name
Test status
Simulation time 535581988450 ps
CPU time 1217.92 seconds
Started Aug 28 08:57:27 PM UTC 24
Finished Aug 28 09:17:57 PM UTC 24
Peak memory 212616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285479830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.285479830
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/32.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_clock_gating.288740534
Short name T313
Test name
Test status
Simulation time 524228048351 ps
CPU time 288.28 seconds
Started Aug 28 08:59:22 PM UTC 24
Finished Aug 28 09:04:14 PM UTC 24
Peak memory 211560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288740534 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gating.288740534
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/33.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_wakeup.3474186692
Short name T340
Test name
Test status
Simulation time 373149324094 ps
CPU time 1220.68 seconds
Started Aug 28 09:01:56 PM UTC 24
Finished Aug 28 09:22:28 PM UTC 24
Peak memory 212484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474186692 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_wakeup.3474186692
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/35.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_fsm_reset.2847737994
Short name T57
Test name
Test status
Simulation time 85042681049 ps
CPU time 494.54 seconds
Started Aug 28 08:16:33 PM UTC 24
Finished Aug 28 08:24:53 PM UTC 24
Peak memory 211776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847737994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.2847737994
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/6.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_clock_gating.2979016805
Short name T267
Test name
Test status
Simulation time 329070781480 ps
CPU time 948.71 seconds
Started Aug 28 08:18:46 PM UTC 24
Finished Aug 28 08:34:45 PM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979016805 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gating.2979016805
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/8.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.672946484
Short name T134
Test name
Test status
Simulation time 1004341218 ps
CPU time 3 seconds
Started Aug 28 09:23:35 PM UTC 24
Finished Aug 28 09:23:39 PM UTC 24
Peak memory 211368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672946484 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_aliasing.672946484
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/0.adc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2898305423
Short name T114
Test name
Test status
Simulation time 1114780184 ps
CPU time 1.45 seconds
Started Aug 28 09:23:32 PM UTC 24
Finished Aug 28 09:23:35 PM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898305423 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_reset.2898305423
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/0.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3333021528
Short name T83
Test name
Test status
Simulation time 317756840 ps
CPU time 2.57 seconds
Started Aug 28 09:23:38 PM UTC 24
Finished Aug 28 09:23:42 PM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3333021528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_cs
r_mem_rw_with_rand_reset.3333021528
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.2813120008
Short name T799
Test name
Test status
Simulation time 293894297 ps
CPU time 2.19 seconds
Started Aug 28 09:23:30 PM UTC 24
Finished Aug 28 09:23:33 PM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813120008 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.2813120008
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/0.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1836975861
Short name T129
Test name
Test status
Simulation time 2343404495 ps
CPU time 3.54 seconds
Started Aug 28 09:23:37 PM UTC 24
Finished Aug 28 09:23:42 PM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836975861 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_same_csr_outstanding.1836975861
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3538220461
Short name T72
Test name
Test status
Simulation time 681319324 ps
CPU time 2.73 seconds
Started Aug 28 09:23:28 PM UTC 24
Finished Aug 28 09:23:32 PM UTC 24
Peak memory 221372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538220461 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.3538220461
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/0.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.4223472701
Short name T66
Test name
Test status
Simulation time 4643125724 ps
CPU time 7.69 seconds
Started Aug 28 09:23:28 PM UTC 24
Finished Aug 28 09:23:37 PM UTC 24
Peak memory 211564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223472701 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_intg_err.4223472701
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/0.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3142608023
Short name T119
Test name
Test status
Simulation time 1152922778 ps
CPU time 7.3 seconds
Started Aug 28 09:23:46 PM UTC 24
Finished Aug 28 09:23:54 PM UTC 24
Peak memory 211300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142608023 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_aliasing.3142608023
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/1.adc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1563116289
Short name T919
Test name
Test status
Simulation time 26990112137 ps
CPU time 189.05 seconds
Started Aug 28 09:23:44 PM UTC 24
Finished Aug 28 09:26:56 PM UTC 24
Peak memory 211592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563116289 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_bash.1563116289
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/1.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.153168766
Short name T117
Test name
Test status
Simulation time 841891266 ps
CPU time 1.93 seconds
Started Aug 28 09:23:43 PM UTC 24
Finished Aug 28 09:23:46 PM UTC 24
Peak memory 209512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153168766 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_reset.153168766
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/1.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2362337114
Short name T84
Test name
Test status
Simulation time 529370325 ps
CPU time 1.78 seconds
Started Aug 28 09:23:47 PM UTC 24
Finished Aug 28 09:23:50 PM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2362337114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_cs
r_mem_rw_with_rand_reset.2362337114
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.4080303933
Short name T116
Test name
Test status
Simulation time 534191798 ps
CPU time 1.23 seconds
Started Aug 28 09:23:43 PM UTC 24
Finished Aug 28 09:23:45 PM UTC 24
Peak memory 210868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080303933 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.4080303933
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/1.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.2396225321
Short name T800
Test name
Test status
Simulation time 569979719 ps
CPU time 1.2 seconds
Started Aug 28 09:23:41 PM UTC 24
Finished Aug 28 09:23:43 PM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396225321 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.2396225321
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/1.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.869981617
Short name T62
Test name
Test status
Simulation time 4286112399 ps
CPU time 9.08 seconds
Started Aug 28 09:23:46 PM UTC 24
Finished Aug 28 09:23:56 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869981617 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_same_csr_outstanding.869981617
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1443751737
Short name T73
Test name
Test status
Simulation time 426594805 ps
CPU time 5.07 seconds
Started Aug 28 09:23:41 PM UTC 24
Finished Aug 28 09:23:47 PM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443751737 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.1443751737
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/1.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.4248083246
Short name T829
Test name
Test status
Simulation time 573184479 ps
CPU time 2.6 seconds
Started Aug 28 09:24:35 PM UTC 24
Finished Aug 28 09:24:40 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4248083246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_c
sr_mem_rw_with_rand_reset.4248083246
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2625153873
Short name T828
Test name
Test status
Simulation time 430472327 ps
CPU time 1.17 seconds
Started Aug 28 09:24:34 PM UTC 24
Finished Aug 28 09:24:37 PM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625153873 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.2625153873
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/10.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.4145308459
Short name T827
Test name
Test status
Simulation time 464590840 ps
CPU time 2.86 seconds
Started Aug 28 09:24:32 PM UTC 24
Finished Aug 28 09:24:36 PM UTC 24
Peak memory 211064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145308459 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.4145308459
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/10.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3518719796
Short name T842
Test name
Test status
Simulation time 2529104937 ps
CPU time 11.78 seconds
Started Aug 28 09:24:35 PM UTC 24
Finished Aug 28 09:24:49 PM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518719796 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_same_csr_outstanding.3518719796
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.4085817345
Short name T833
Test name
Test status
Simulation time 4664913173 ps
CPU time 7.77 seconds
Started Aug 28 09:24:32 PM UTC 24
Finished Aug 28 09:24:41 PM UTC 24
Peak memory 211368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085817345 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_intg_err.4085817345
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/10.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.4114820883
Short name T834
Test name
Test status
Simulation time 597616714 ps
CPU time 1.75 seconds
Started Aug 28 09:24:41 PM UTC 24
Finished Aug 28 09:24:43 PM UTC 24
Peak memory 209980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4114820883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_c
sr_mem_rw_with_rand_reset.4114820883
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3388133652
Short name T126
Test name
Test status
Simulation time 329277020 ps
CPU time 2.49 seconds
Started Aug 28 09:24:38 PM UTC 24
Finished Aug 28 09:24:41 PM UTC 24
Peak memory 211148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388133652 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.3388133652
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/11.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.653726997
Short name T830
Test name
Test status
Simulation time 390122496 ps
CPU time 1.35 seconds
Started Aug 28 09:24:38 PM UTC 24
Finished Aug 28 09:24:40 PM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653726997 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.653726997
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/11.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1413207605
Short name T838
Test name
Test status
Simulation time 2603028070 ps
CPU time 5.38 seconds
Started Aug 28 09:24:40 PM UTC 24
Finished Aug 28 09:24:46 PM UTC 24
Peak memory 211400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413207605 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_same_csr_outstanding.1413207605
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2152363593
Short name T831
Test name
Test status
Simulation time 434083415 ps
CPU time 3.92 seconds
Started Aug 28 09:24:35 PM UTC 24
Finished Aug 28 09:24:41 PM UTC 24
Peak memory 221380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152363593 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2152363593
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/11.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3293270219
Short name T845
Test name
Test status
Simulation time 4320748439 ps
CPU time 12.58 seconds
Started Aug 28 09:24:36 PM UTC 24
Finished Aug 28 09:24:51 PM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293270219 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_intg_err.3293270219
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/11.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2092577361
Short name T835
Test name
Test status
Simulation time 407108371 ps
CPU time 2.36 seconds
Started Aug 28 09:24:42 PM UTC 24
Finished Aug 28 09:24:45 PM UTC 24
Peak memory 211272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2092577361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_c
sr_mem_rw_with_rand_reset.2092577361
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1956670916
Short name T839
Test name
Test status
Simulation time 515519258 ps
CPU time 3.23 seconds
Started Aug 28 09:24:42 PM UTC 24
Finished Aug 28 09:24:46 PM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956670916 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.1956670916
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/12.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.3662392243
Short name T837
Test name
Test status
Simulation time 433969918 ps
CPU time 2.75 seconds
Started Aug 28 09:24:42 PM UTC 24
Finished Aug 28 09:24:46 PM UTC 24
Peak memory 211220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662392243 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3662392243
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/12.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.309881636
Short name T852
Test name
Test status
Simulation time 2341504535 ps
CPU time 11.6 seconds
Started Aug 28 09:24:42 PM UTC 24
Finished Aug 28 09:24:55 PM UTC 24
Peak memory 211344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309881636 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_same_csr_outstanding.309881636
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.615882053
Short name T836
Test name
Test status
Simulation time 464870271 ps
CPU time 3.67 seconds
Started Aug 28 09:24:41 PM UTC 24
Finished Aug 28 09:24:45 PM UTC 24
Peak memory 211512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615882053 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.615882053
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/12.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2858234457
Short name T893
Test name
Test status
Simulation time 7455146699 ps
CPU time 29.23 seconds
Started Aug 28 09:24:41 PM UTC 24
Finished Aug 28 09:25:11 PM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858234457 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_intg_err.2858234457
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/12.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.904655637
Short name T844
Test name
Test status
Simulation time 330573285 ps
CPU time 1.79 seconds
Started Aug 28 09:24:47 PM UTC 24
Finished Aug 28 09:24:50 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=904655637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_cs
r_mem_rw_with_rand_reset.904655637
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.636008325
Short name T127
Test name
Test status
Simulation time 304079640 ps
CPU time 2.18 seconds
Started Aug 28 09:24:46 PM UTC 24
Finished Aug 28 09:24:49 PM UTC 24
Peak memory 211140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636008325 -assert nopostproc +UVM_TESTNAME=adc_
ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.636008325
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/13.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.4014839420
Short name T843
Test name
Test status
Simulation time 430065274 ps
CPU time 1.6 seconds
Started Aug 28 09:24:46 PM UTC 24
Finished Aug 28 09:24:49 PM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014839420 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.4014839420
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/13.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1734014208
Short name T851
Test name
Test status
Simulation time 4129193722 ps
CPU time 7.05 seconds
Started Aug 28 09:24:46 PM UTC 24
Finished Aug 28 09:24:54 PM UTC 24
Peak memory 211708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734014208 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_same_csr_outstanding.1734014208
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2678150388
Short name T841
Test name
Test status
Simulation time 409806316 ps
CPU time 3.04 seconds
Started Aug 28 09:24:44 PM UTC 24
Finished Aug 28 09:24:48 PM UTC 24
Peak memory 211428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678150388 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.2678150388
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/13.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.617051841
Short name T853
Test name
Test status
Simulation time 4940108476 ps
CPU time 7.65 seconds
Started Aug 28 09:24:46 PM UTC 24
Finished Aug 28 09:24:55 PM UTC 24
Peak memory 211564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617051841 -assert nopostproc +UVM_TEST
NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_intg_err.617051841
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/13.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3988728844
Short name T849
Test name
Test status
Simulation time 506489703 ps
CPU time 1.56 seconds
Started Aug 28 09:24:51 PM UTC 24
Finished Aug 28 09:24:53 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3988728844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_c
sr_mem_rw_with_rand_reset.3988728844
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2707827203
Short name T848
Test name
Test status
Simulation time 578405200 ps
CPU time 1.77 seconds
Started Aug 28 09:24:50 PM UTC 24
Finished Aug 28 09:24:52 PM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707827203 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2707827203
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/14.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.2796894181
Short name T850
Test name
Test status
Simulation time 521092432 ps
CPU time 3.08 seconds
Started Aug 28 09:24:50 PM UTC 24
Finished Aug 28 09:24:54 PM UTC 24
Peak memory 211140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796894181 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.2796894181
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/14.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2657843345
Short name T871
Test name
Test status
Simulation time 2279059559 ps
CPU time 12.67 seconds
Started Aug 28 09:24:50 PM UTC 24
Finished Aug 28 09:25:03 PM UTC 24
Peak memory 211340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657843345 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_same_csr_outstanding.2657843345
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3725237776
Short name T846
Test name
Test status
Simulation time 573838436 ps
CPU time 2.64 seconds
Started Aug 28 09:24:47 PM UTC 24
Finished Aug 28 09:24:51 PM UTC 24
Peak memory 211436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725237776 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.3725237776
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/14.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1524923851
Short name T890
Test name
Test status
Simulation time 4598297055 ps
CPU time 22.43 seconds
Started Aug 28 09:24:47 PM UTC 24
Finished Aug 28 09:25:11 PM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524923851 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_intg_err.1524923851
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/14.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.176251375
Short name T855
Test name
Test status
Simulation time 558097895 ps
CPU time 1.71 seconds
Started Aug 28 09:24:53 PM UTC 24
Finished Aug 28 09:24:56 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=176251375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_cs
r_mem_rw_with_rand_reset.176251375
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.4168227651
Short name T856
Test name
Test status
Simulation time 484632084 ps
CPU time 3.03 seconds
Started Aug 28 09:24:52 PM UTC 24
Finished Aug 28 09:24:56 PM UTC 24
Peak memory 211344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168227651 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.4168227651
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/15.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.4115347030
Short name T857
Test name
Test status
Simulation time 501599182 ps
CPU time 3.26 seconds
Started Aug 28 09:24:52 PM UTC 24
Finished Aug 28 09:24:56 PM UTC 24
Peak memory 211140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115347030 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.4115347030
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/15.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.252216639
Short name T861
Test name
Test status
Simulation time 2467475932 ps
CPU time 6.6 seconds
Started Aug 28 09:24:52 PM UTC 24
Finished Aug 28 09:25:00 PM UTC 24
Peak memory 211336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252216639 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_same_csr_outstanding.252216639
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1009289916
Short name T854
Test name
Test status
Simulation time 330583221 ps
CPU time 3.64 seconds
Started Aug 28 09:24:51 PM UTC 24
Finished Aug 28 09:24:55 PM UTC 24
Peak memory 211380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009289916 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1009289916
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/15.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2627858104
Short name T880
Test name
Test status
Simulation time 8252689269 ps
CPU time 14.79 seconds
Started Aug 28 09:24:52 PM UTC 24
Finished Aug 28 09:25:08 PM UTC 24
Peak memory 211512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627858104 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_intg_err.2627858104
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/15.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.107162429
Short name T862
Test name
Test status
Simulation time 495336485 ps
CPU time 2.51 seconds
Started Aug 28 09:24:56 PM UTC 24
Finished Aug 28 09:25:00 PM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=107162429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_cs
r_mem_rw_with_rand_reset.107162429
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2416892649
Short name T128
Test name
Test status
Simulation time 497795690 ps
CPU time 2.53 seconds
Started Aug 28 09:24:55 PM UTC 24
Finished Aug 28 09:24:59 PM UTC 24
Peak memory 210848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416892649 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.2416892649
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/16.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.2624745299
Short name T858
Test name
Test status
Simulation time 293728434 ps
CPU time 1.19 seconds
Started Aug 28 09:24:55 PM UTC 24
Finished Aug 28 09:24:57 PM UTC 24
Peak memory 209856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624745299 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.2624745299
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/16.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1315469500
Short name T863
Test name
Test status
Simulation time 2109533824 ps
CPU time 4.03 seconds
Started Aug 28 09:24:55 PM UTC 24
Finished Aug 28 09:25:00 PM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315469500 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_same_csr_outstanding.1315469500
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3593798828
Short name T859
Test name
Test status
Simulation time 504532631 ps
CPU time 3.85 seconds
Started Aug 28 09:24:54 PM UTC 24
Finished Aug 28 09:24:59 PM UTC 24
Peak memory 211432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593798828 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.3593798828
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/16.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1709139716
Short name T872
Test name
Test status
Simulation time 4446031804 ps
CPU time 8.28 seconds
Started Aug 28 09:24:54 PM UTC 24
Finished Aug 28 09:25:03 PM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709139716 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_intg_err.1709139716
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/16.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1112952569
Short name T866
Test name
Test status
Simulation time 546166143 ps
CPU time 1.89 seconds
Started Aug 28 09:25:00 PM UTC 24
Finished Aug 28 09:25:03 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1112952569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_c
sr_mem_rw_with_rand_reset.1112952569
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2382996212
Short name T865
Test name
Test status
Simulation time 557355817 ps
CPU time 2.27 seconds
Started Aug 28 09:24:59 PM UTC 24
Finished Aug 28 09:25:02 PM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382996212 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2382996212
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/17.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.488731297
Short name T864
Test name
Test status
Simulation time 541631762 ps
CPU time 2.1 seconds
Started Aug 28 09:24:58 PM UTC 24
Finished Aug 28 09:25:01 PM UTC 24
Peak memory 211228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488731297 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.488731297
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/17.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1107630953
Short name T867
Test name
Test status
Simulation time 2343492391 ps
CPU time 2.3 seconds
Started Aug 28 09:25:00 PM UTC 24
Finished Aug 28 09:25:03 PM UTC 24
Peak memory 211332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107630953 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_same_csr_outstanding.1107630953
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2057965993
Short name T860
Test name
Test status
Simulation time 311939364 ps
CPU time 1.94 seconds
Started Aug 28 09:24:56 PM UTC 24
Finished Aug 28 09:24:59 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057965993 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2057965993
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/17.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1756584753
Short name T896
Test name
Test status
Simulation time 4542551380 ps
CPU time 14.76 seconds
Started Aug 28 09:24:56 PM UTC 24
Finished Aug 28 09:25:12 PM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756584753 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_intg_err.1756584753
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/17.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2289866390
Short name T875
Test name
Test status
Simulation time 498222581 ps
CPU time 2.4 seconds
Started Aug 28 09:25:02 PM UTC 24
Finished Aug 28 09:25:05 PM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2289866390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_c
sr_mem_rw_with_rand_reset.2289866390
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2015156137
Short name T870
Test name
Test status
Simulation time 460027705 ps
CPU time 1.45 seconds
Started Aug 28 09:25:01 PM UTC 24
Finished Aug 28 09:25:03 PM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015156137 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.2015156137
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/18.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.401641725
Short name T869
Test name
Test status
Simulation time 324218502 ps
CPU time 1.24 seconds
Started Aug 28 09:25:01 PM UTC 24
Finished Aug 28 09:25:03 PM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401641725 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.401641725
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/18.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1830636745
Short name T873
Test name
Test status
Simulation time 2368391730 ps
CPU time 3.2 seconds
Started Aug 28 09:25:01 PM UTC 24
Finished Aug 28 09:25:05 PM UTC 24
Peak memory 211332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830636745 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_same_csr_outstanding.1830636745
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.4187068288
Short name T868
Test name
Test status
Simulation time 483561040 ps
CPU time 2.34 seconds
Started Aug 28 09:25:00 PM UTC 24
Finished Aug 28 09:25:03 PM UTC 24
Peak memory 211328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187068288 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.4187068288
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/18.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1055618387
Short name T916
Test name
Test status
Simulation time 8792504057 ps
CPU time 32.77 seconds
Started Aug 28 09:25:00 PM UTC 24
Finished Aug 28 09:25:34 PM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055618387 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_intg_err.1055618387
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/18.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.520144773
Short name T881
Test name
Test status
Simulation time 524059687 ps
CPU time 2.85 seconds
Started Aug 28 09:25:04 PM UTC 24
Finished Aug 28 09:25:08 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=520144773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_cs
r_mem_rw_with_rand_reset.520144773
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.926806321
Short name T877
Test name
Test status
Simulation time 407282856 ps
CPU time 1.57 seconds
Started Aug 28 09:25:04 PM UTC 24
Finished Aug 28 09:25:07 PM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926806321 -assert nopostproc +UVM_TESTNAME=adc_
ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.926806321
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/19.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.859899984
Short name T874
Test name
Test status
Simulation time 497163096 ps
CPU time 0.99 seconds
Started Aug 28 09:25:03 PM UTC 24
Finished Aug 28 09:25:05 PM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859899984 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.859899984
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/19.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2197511116
Short name T914
Test name
Test status
Simulation time 2178570394 ps
CPU time 16.56 seconds
Started Aug 28 09:25:04 PM UTC 24
Finished Aug 28 09:25:22 PM UTC 24
Peak memory 211340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197511116 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_same_csr_outstanding.2197511116
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3558145027
Short name T876
Test name
Test status
Simulation time 651457286 ps
CPU time 2.77 seconds
Started Aug 28 09:25:02 PM UTC 24
Finished Aug 28 09:25:06 PM UTC 24
Peak memory 211324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558145027 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3558145027
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/19.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3039972591
Short name T913
Test name
Test status
Simulation time 8382947063 ps
CPU time 12.31 seconds
Started Aug 28 09:25:03 PM UTC 24
Finished Aug 28 09:25:16 PM UTC 24
Peak memory 211584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039972591 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_intg_err.3039972591
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/19.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3759303708
Short name T802
Test name
Test status
Simulation time 1221050825 ps
CPU time 3.62 seconds
Started Aug 28 09:23:53 PM UTC 24
Finished Aug 28 09:23:58 PM UTC 24
Peak memory 211352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759303708 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_aliasing.3759303708
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/2.adc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1532708759
Short name T918
Test name
Test status
Simulation time 27312199829 ps
CPU time 175.29 seconds
Started Aug 28 09:23:53 PM UTC 24
Finished Aug 28 09:26:51 PM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532708759 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_bash.1532708759
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/2.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3483242442
Short name T118
Test name
Test status
Simulation time 698162163 ps
CPU time 1.8 seconds
Started Aug 28 09:23:50 PM UTC 24
Finished Aug 28 09:23:53 PM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483242442 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_reset.3483242442
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/2.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3079210841
Short name T85
Test name
Test status
Simulation time 522378251 ps
CPU time 3.71 seconds
Started Aug 28 09:23:56 PM UTC 24
Finished Aug 28 09:24:00 PM UTC 24
Peak memory 211268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3079210841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_cs
r_mem_rw_with_rand_reset.3079210841
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.4062560653
Short name T63
Test name
Test status
Simulation time 454520666 ps
CPU time 2.97 seconds
Started Aug 28 09:23:52 PM UTC 24
Finished Aug 28 09:23:56 PM UTC 24
Peak memory 211200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062560653 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.4062560653
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/2.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.3645591550
Short name T801
Test name
Test status
Simulation time 394736924 ps
CPU time 2.63 seconds
Started Aug 28 09:23:49 PM UTC 24
Finished Aug 28 09:23:53 PM UTC 24
Peak memory 211136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645591550 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.3645591550
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/2.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3951207098
Short name T64
Test name
Test status
Simulation time 4304625145 ps
CPU time 6.03 seconds
Started Aug 28 09:23:55 PM UTC 24
Finished Aug 28 09:24:03 PM UTC 24
Peak memory 211560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951207098 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_same_csr_outstanding.3951207098
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.854344966
Short name T68
Test name
Test status
Simulation time 9203925101 ps
CPU time 22.46 seconds
Started Aug 28 09:23:48 PM UTC 24
Finished Aug 28 09:24:12 PM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854344966 -assert nopostproc +UVM_TEST
NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_intg_err.854344966
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/2.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.3255028661
Short name T878
Test name
Test status
Simulation time 410787976 ps
CPU time 1.82 seconds
Started Aug 28 09:25:04 PM UTC 24
Finished Aug 28 09:25:07 PM UTC 24
Peak memory 209856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255028661 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.3255028661
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/20.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.273127309
Short name T879
Test name
Test status
Simulation time 461525754 ps
CPU time 1.89 seconds
Started Aug 28 09:25:04 PM UTC 24
Finished Aug 28 09:25:07 PM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273127309 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.273127309
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/21.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.56251169
Short name T883
Test name
Test status
Simulation time 383915701 ps
CPU time 2.7 seconds
Started Aug 28 09:25:04 PM UTC 24
Finished Aug 28 09:25:08 PM UTC 24
Peak memory 211096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56251169 -assert nopostproc +UVM_TESTNAME=adc_ctrl
_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.56251169
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/22.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.4048051764
Short name T884
Test name
Test status
Simulation time 502708896 ps
CPU time 2.1 seconds
Started Aug 28 09:25:06 PM UTC 24
Finished Aug 28 09:25:09 PM UTC 24
Peak memory 211240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048051764 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.4048051764
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/23.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.543887669
Short name T882
Test name
Test status
Simulation time 501571371 ps
CPU time 1.63 seconds
Started Aug 28 09:25:06 PM UTC 24
Finished Aug 28 09:25:08 PM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543887669 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.543887669
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/24.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.349565986
Short name T889
Test name
Test status
Simulation time 508808123 ps
CPU time 3.32 seconds
Started Aug 28 09:25:07 PM UTC 24
Finished Aug 28 09:25:11 PM UTC 24
Peak memory 211272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349565986 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.349565986
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/25.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.384893800
Short name T885
Test name
Test status
Simulation time 510842886 ps
CPU time 1.78 seconds
Started Aug 28 09:25:07 PM UTC 24
Finished Aug 28 09:25:09 PM UTC 24
Peak memory 209916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384893800 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.384893800
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/26.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.249433024
Short name T887
Test name
Test status
Simulation time 338469523 ps
CPU time 1.15 seconds
Started Aug 28 09:25:08 PM UTC 24
Finished Aug 28 09:25:10 PM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249433024 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.249433024
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/27.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.1534825237
Short name T886
Test name
Test status
Simulation time 412615624 ps
CPU time 1.1 seconds
Started Aug 28 09:25:08 PM UTC 24
Finished Aug 28 09:25:10 PM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534825237 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.1534825237
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/28.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.1352704081
Short name T891
Test name
Test status
Simulation time 355118475 ps
CPU time 2.37 seconds
Started Aug 28 09:25:08 PM UTC 24
Finished Aug 28 09:25:11 PM UTC 24
Peak memory 211180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352704081 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1352704081
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/29.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3506931208
Short name T122
Test name
Test status
Simulation time 901220368 ps
CPU time 6.88 seconds
Started Aug 28 09:24:01 PM UTC 24
Finished Aug 28 09:24:09 PM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506931208 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_aliasing.3506931208
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/3.adc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.734474856
Short name T917
Test name
Test status
Simulation time 52837453816 ps
CPU time 164.17 seconds
Started Aug 28 09:24:01 PM UTC 24
Finished Aug 28 09:26:48 PM UTC 24
Peak memory 211396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734474856 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_bash.734474856
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/3.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3203212233
Short name T121
Test name
Test status
Simulation time 791814251 ps
CPU time 1.38 seconds
Started Aug 28 09:23:59 PM UTC 24
Finished Aug 28 09:24:01 PM UTC 24
Peak memory 209980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203212233 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_reset.3203212233
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/3.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2290603649
Short name T78
Test name
Test status
Simulation time 474926908 ps
CPU time 3.19 seconds
Started Aug 28 09:24:02 PM UTC 24
Finished Aug 28 09:24:06 PM UTC 24
Peak memory 211348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2290603649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_cs
r_mem_rw_with_rand_reset.2290603649
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2997190562
Short name T120
Test name
Test status
Simulation time 402349112 ps
CPU time 1.44 seconds
Started Aug 28 09:23:59 PM UTC 24
Finished Aug 28 09:24:01 PM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997190562 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.2997190562
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/3.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.1362713455
Short name T803
Test name
Test status
Simulation time 346387058 ps
CPU time 1.23 seconds
Started Aug 28 09:23:58 PM UTC 24
Finished Aug 28 09:24:00 PM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362713455 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.1362713455
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/3.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3224591386
Short name T65
Test name
Test status
Simulation time 4353937338 ps
CPU time 3.24 seconds
Started Aug 28 09:24:02 PM UTC 24
Finished Aug 28 09:24:06 PM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224591386 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_same_csr_outstanding.3224591386
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1499587393
Short name T75
Test name
Test status
Simulation time 483325433 ps
CPU time 3.05 seconds
Started Aug 28 09:23:57 PM UTC 24
Finished Aug 28 09:24:01 PM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499587393 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.1499587393
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/3.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.419962733
Short name T369
Test name
Test status
Simulation time 8650415155 ps
CPU time 21.14 seconds
Started Aug 28 09:23:57 PM UTC 24
Finished Aug 28 09:24:19 PM UTC 24
Peak memory 211568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419962733 -assert nopostproc +UVM_TEST
NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_intg_err.419962733
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/3.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/30.adc_ctrl_intr_test.2565200623
Short name T888
Test name
Test status
Simulation time 456553972 ps
CPU time 1.82 seconds
Started Aug 28 09:25:08 PM UTC 24
Finished Aug 28 09:25:11 PM UTC 24
Peak memory 210392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565200623 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.2565200623
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/30.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/31.adc_ctrl_intr_test.3264981381
Short name T892
Test name
Test status
Simulation time 466023847 ps
CPU time 1.4 seconds
Started Aug 28 09:25:09 PM UTC 24
Finished Aug 28 09:25:11 PM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264981381 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3264981381
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/31.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/32.adc_ctrl_intr_test.2189218799
Short name T895
Test name
Test status
Simulation time 483527908 ps
CPU time 2.2 seconds
Started Aug 28 09:25:09 PM UTC 24
Finished Aug 28 09:25:12 PM UTC 24
Peak memory 211096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189218799 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.2189218799
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/32.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/33.adc_ctrl_intr_test.4258935628
Short name T898
Test name
Test status
Simulation time 414055220 ps
CPU time 2.73 seconds
Started Aug 28 09:25:09 PM UTC 24
Finished Aug 28 09:25:13 PM UTC 24
Peak memory 211140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258935628 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.4258935628
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/33.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/34.adc_ctrl_intr_test.2043203989
Short name T899
Test name
Test status
Simulation time 407255757 ps
CPU time 2.73 seconds
Started Aug 28 09:25:09 PM UTC 24
Finished Aug 28 09:25:13 PM UTC 24
Peak memory 211180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043203989 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2043203989
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/34.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/35.adc_ctrl_intr_test.2296624975
Short name T894
Test name
Test status
Simulation time 556138785 ps
CPU time 1.47 seconds
Started Aug 28 09:25:09 PM UTC 24
Finished Aug 28 09:25:12 PM UTC 24
Peak memory 209856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296624975 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.2296624975
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/35.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/36.adc_ctrl_intr_test.3127840169
Short name T900
Test name
Test status
Simulation time 406928354 ps
CPU time 2.01 seconds
Started Aug 28 09:25:10 PM UTC 24
Finished Aug 28 09:25:14 PM UTC 24
Peak memory 211100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127840169 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3127840169
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/36.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/37.adc_ctrl_intr_test.3479831290
Short name T897
Test name
Test status
Simulation time 548539050 ps
CPU time 1.23 seconds
Started Aug 28 09:25:10 PM UTC 24
Finished Aug 28 09:25:13 PM UTC 24
Peak memory 209804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479831290 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3479831290
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/37.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/38.adc_ctrl_intr_test.855372554
Short name T903
Test name
Test status
Simulation time 483450231 ps
CPU time 2.51 seconds
Started Aug 28 09:25:10 PM UTC 24
Finished Aug 28 09:25:14 PM UTC 24
Peak memory 211164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855372554 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.855372554
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/38.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/39.adc_ctrl_intr_test.830079353
Short name T901
Test name
Test status
Simulation time 565276051 ps
CPU time 1.13 seconds
Started Aug 28 09:25:11 PM UTC 24
Finished Aug 28 09:25:14 PM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830079353 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.830079353
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/39.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2549212501
Short name T123
Test name
Test status
Simulation time 886802476 ps
CPU time 3.72 seconds
Started Aug 28 09:24:07 PM UTC 24
Finished Aug 28 09:24:12 PM UTC 24
Peak memory 211372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549212501 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_aliasing.2549212501
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/4.adc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.4180380605
Short name T915
Test name
Test status
Simulation time 26804769642 ps
CPU time 83 seconds
Started Aug 28 09:24:07 PM UTC 24
Finished Aug 28 09:25:32 PM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180380605 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_bash.4180380605
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/4.adc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3670334815
Short name T124
Test name
Test status
Simulation time 1206036673 ps
CPU time 6.79 seconds
Started Aug 28 09:24:07 PM UTC 24
Finished Aug 28 09:24:15 PM UTC 24
Peak memory 211228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670334815 -assert nopostproc +UVM_TESTNA
ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_reset.3670334815
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/4.adc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1417120409
Short name T104
Test name
Test status
Simulation time 323654854 ps
CPU time 1.84 seconds
Started Aug 28 09:24:08 PM UTC 24
Finished Aug 28 09:24:11 PM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1417120409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_cs
r_mem_rw_with_rand_reset.1417120409
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3751656777
Short name T130
Test name
Test status
Simulation time 537115942 ps
CPU time 3.42 seconds
Started Aug 28 09:24:07 PM UTC 24
Finished Aug 28 09:24:12 PM UTC 24
Peak memory 211120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751656777 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3751656777
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/4.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_intr_test.3308482993
Short name T804
Test name
Test status
Simulation time 529005979 ps
CPU time 1.63 seconds
Started Aug 28 09:24:04 PM UTC 24
Finished Aug 28 09:24:07 PM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308482993 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3308482993
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/4.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2333152280
Short name T132
Test name
Test status
Simulation time 2176773779 ps
CPU time 9.41 seconds
Started Aug 28 09:24:08 PM UTC 24
Finished Aug 28 09:24:19 PM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333152280 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_same_csr_outstanding.2333152280
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_errors.632415706
Short name T76
Test name
Test status
Simulation time 966188144 ps
CPU time 3.76 seconds
Started Aug 28 09:24:02 PM UTC 24
Finished Aug 28 09:24:07 PM UTC 24
Peak memory 211304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632415706 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.632415706
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/4.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/40.adc_ctrl_intr_test.3301323109
Short name T902
Test name
Test status
Simulation time 504594840 ps
CPU time 1.32 seconds
Started Aug 28 09:25:11 PM UTC 24
Finished Aug 28 09:25:14 PM UTC 24
Peak memory 209856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301323109 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3301323109
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/40.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/41.adc_ctrl_intr_test.496484469
Short name T904
Test name
Test status
Simulation time 499559829 ps
CPU time 1.07 seconds
Started Aug 28 09:25:13 PM UTC 24
Finished Aug 28 09:25:15 PM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496484469 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.496484469
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/41.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/42.adc_ctrl_intr_test.350206530
Short name T908
Test name
Test status
Simulation time 389766439 ps
CPU time 1.69 seconds
Started Aug 28 09:25:13 PM UTC 24
Finished Aug 28 09:25:15 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350206530 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.350206530
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/42.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/43.adc_ctrl_intr_test.4206792327
Short name T906
Test name
Test status
Simulation time 444959945 ps
CPU time 1.31 seconds
Started Aug 28 09:25:13 PM UTC 24
Finished Aug 28 09:25:15 PM UTC 24
Peak memory 210392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206792327 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.4206792327
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/43.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/44.adc_ctrl_intr_test.256865114
Short name T905
Test name
Test status
Simulation time 523463845 ps
CPU time 1.11 seconds
Started Aug 28 09:25:13 PM UTC 24
Finished Aug 28 09:25:15 PM UTC 24
Peak memory 210392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256865114 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.256865114
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/44.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/45.adc_ctrl_intr_test.1208829766
Short name T907
Test name
Test status
Simulation time 408022954 ps
CPU time 1.3 seconds
Started Aug 28 09:25:13 PM UTC 24
Finished Aug 28 09:25:15 PM UTC 24
Peak memory 210392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208829766 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.1208829766
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/45.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/46.adc_ctrl_intr_test.394747362
Short name T911
Test name
Test status
Simulation time 446563295 ps
CPU time 2.56 seconds
Started Aug 28 09:25:13 PM UTC 24
Finished Aug 28 09:25:16 PM UTC 24
Peak memory 211096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394747362 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.394747362
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/46.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/47.adc_ctrl_intr_test.3004913936
Short name T912
Test name
Test status
Simulation time 454033891 ps
CPU time 1.66 seconds
Started Aug 28 09:25:14 PM UTC 24
Finished Aug 28 09:25:16 PM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004913936 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.3004913936
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/47.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/48.adc_ctrl_intr_test.3962786584
Short name T909
Test name
Test status
Simulation time 429726834 ps
CPU time 1.04 seconds
Started Aug 28 09:25:14 PM UTC 24
Finished Aug 28 09:25:16 PM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962786584 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.3962786584
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/48.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/49.adc_ctrl_intr_test.2929076715
Short name T910
Test name
Test status
Simulation time 346754770 ps
CPU time 1.22 seconds
Started Aug 28 09:25:14 PM UTC 24
Finished Aug 28 09:25:16 PM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929076715 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2929076715
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/49.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3827134428
Short name T805
Test name
Test status
Simulation time 445133340 ps
CPU time 1.69 seconds
Started Aug 28 09:24:13 PM UTC 24
Finished Aug 28 09:24:15 PM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3827134428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_cs
r_mem_rw_with_rand_reset.3827134428
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3455355992
Short name T131
Test name
Test status
Simulation time 431201810 ps
CPU time 1.42 seconds
Started Aug 28 09:24:13 PM UTC 24
Finished Aug 28 09:24:15 PM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455355992 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.3455355992
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/5.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_intr_test.2088475612
Short name T806
Test name
Test status
Simulation time 437623832 ps
CPU time 2.81 seconds
Started Aug 28 09:24:13 PM UTC 24
Finished Aug 28 09:24:17 PM UTC 24
Peak memory 211228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088475612 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.2088475612
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/5.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3594383256
Short name T133
Test name
Test status
Simulation time 4023491176 ps
CPU time 6.69 seconds
Started Aug 28 09:24:13 PM UTC 24
Finished Aug 28 09:24:20 PM UTC 24
Peak memory 211584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594383256 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_same_csr_outstanding.3594383256
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3184915184
Short name T77
Test name
Test status
Simulation time 549038935 ps
CPU time 5.02 seconds
Started Aug 28 09:24:09 PM UTC 24
Finished Aug 28 09:24:16 PM UTC 24
Peak memory 227648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184915184 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3184915184
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/5.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3112668896
Short name T810
Test name
Test status
Simulation time 4584963447 ps
CPU time 9.58 seconds
Started Aug 28 09:24:12 PM UTC 24
Finished Aug 28 09:24:22 PM UTC 24
Peak memory 211504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112668896 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_intg_err.3112668896
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/5.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.994919348
Short name T811
Test name
Test status
Simulation time 390191332 ps
CPU time 1.92 seconds
Started Aug 28 09:24:19 PM UTC 24
Finished Aug 28 09:24:23 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=994919348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr
_mem_rw_with_rand_reset.994919348
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1926376953
Short name T809
Test name
Test status
Simulation time 366339103 ps
CPU time 2.67 seconds
Started Aug 28 09:24:17 PM UTC 24
Finished Aug 28 09:24:21 PM UTC 24
Peak memory 211360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926376953 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.1926376953
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/6.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_intr_test.3121272075
Short name T807
Test name
Test status
Simulation time 499712538 ps
CPU time 1.41 seconds
Started Aug 28 09:24:16 PM UTC 24
Finished Aug 28 09:24:18 PM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121272075 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.3121272075
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/6.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3402980279
Short name T819
Test name
Test status
Simulation time 2649228320 ps
CPU time 11.8 seconds
Started Aug 28 09:24:17 PM UTC 24
Finished Aug 28 09:24:30 PM UTC 24
Peak memory 211176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402980279 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_same_csr_outstanding.3402980279
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_errors.905571118
Short name T808
Test name
Test status
Simulation time 494180075 ps
CPU time 3.47 seconds
Started Aug 28 09:24:16 PM UTC 24
Finished Aug 28 09:24:20 PM UTC 24
Peak memory 211328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905571118 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.905571118
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/6.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.795374278
Short name T371
Test name
Test status
Simulation time 4500102220 ps
CPU time 7.47 seconds
Started Aug 28 09:24:16 PM UTC 24
Finished Aug 28 09:24:24 PM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795374278 -assert nopostproc +UVM_TEST
NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_intg_err.795374278
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/6.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3780257108
Short name T814
Test name
Test status
Simulation time 520500612 ps
CPU time 1.37 seconds
Started Aug 28 09:24:23 PM UTC 24
Finished Aug 28 09:24:26 PM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3780257108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_cs
r_mem_rw_with_rand_reset.3780257108
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_rw.492953055
Short name T813
Test name
Test status
Simulation time 548094792 ps
CPU time 2.58 seconds
Started Aug 28 09:24:21 PM UTC 24
Finished Aug 28 09:24:25 PM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492953055 -assert nopostproc +UVM_TESTNAME=adc_
ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.492953055
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/7.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_intr_test.2847529448
Short name T812
Test name
Test status
Simulation time 348577813 ps
CPU time 1.26 seconds
Started Aug 28 09:24:21 PM UTC 24
Finished Aug 28 09:24:24 PM UTC 24
Peak memory 210392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847529448 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.2847529448
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/7.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.235222215
Short name T822
Test name
Test status
Simulation time 2466092957 ps
CPU time 8.71 seconds
Started Aug 28 09:24:21 PM UTC 24
Finished Aug 28 09:24:31 PM UTC 24
Peak memory 211584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235222215 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_same_csr_outstanding.235222215
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2117914967
Short name T815
Test name
Test status
Simulation time 561443746 ps
CPU time 4.27 seconds
Started Aug 28 09:24:20 PM UTC 24
Finished Aug 28 09:24:26 PM UTC 24
Peak memory 211512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117914967 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2117914967
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/7.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2620402421
Short name T370
Test name
Test status
Simulation time 4196152424 ps
CPU time 9.42 seconds
Started Aug 28 09:24:20 PM UTC 24
Finished Aug 28 09:24:31 PM UTC 24
Peak memory 211612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620402421 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_intg_err.2620402421
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/7.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1194494741
Short name T820
Test name
Test status
Simulation time 482258604 ps
CPU time 2.39 seconds
Started Aug 28 09:24:27 PM UTC 24
Finished Aug 28 09:24:30 PM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1194494741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_cs
r_mem_rw_with_rand_reset.1194494741
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_rw.582992581
Short name T817
Test name
Test status
Simulation time 487208372 ps
CPU time 2.96 seconds
Started Aug 28 09:24:26 PM UTC 24
Finished Aug 28 09:24:30 PM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582992581 -assert nopostproc +UVM_TESTNAME=adc_
ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.582992581
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/8.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_intr_test.2829721323
Short name T816
Test name
Test status
Simulation time 625104904 ps
CPU time 1.02 seconds
Started Aug 28 09:24:24 PM UTC 24
Finished Aug 28 09:24:27 PM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829721323 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.2829721323
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/8.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3631433318
Short name T840
Test name
Test status
Simulation time 5127626981 ps
CPU time 18.58 seconds
Started Aug 28 09:24:27 PM UTC 24
Finished Aug 28 09:24:46 PM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631433318 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_same_csr_outstanding.3631433318
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_errors.514432503
Short name T818
Test name
Test status
Simulation time 437655729 ps
CPU time 5.31 seconds
Started Aug 28 09:24:23 PM UTC 24
Finished Aug 28 09:24:30 PM UTC 24
Peak memory 211348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514432503 -assert nopostproc +UVM_TESTNAME=adc_ctr
l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.514432503
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/8.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3257760133
Short name T372
Test name
Test status
Simulation time 4159906643 ps
CPU time 20.89 seconds
Started Aug 28 09:24:23 PM UTC 24
Finished Aug 28 09:24:46 PM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257760133 -assert nopostproc +UVM_TES
TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_intg_err.3257760133
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/8.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.274143268
Short name T824
Test name
Test status
Simulation time 617463895 ps
CPU time 1.92 seconds
Started Aug 28 09:24:31 PM UTC 24
Finished Aug 28 09:24:34 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=274143268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr
_mem_rw_with_rand_reset.274143268
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3130629761
Short name T825
Test name
Test status
Simulation time 490194249 ps
CPU time 2.25 seconds
Started Aug 28 09:24:31 PM UTC 24
Finished Aug 28 09:24:34 PM UTC 24
Peak memory 211136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130629761 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.3130629761
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/9.adc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_intr_test.2311848038
Short name T823
Test name
Test status
Simulation time 287496982 ps
CPU time 2.13 seconds
Started Aug 28 09:24:31 PM UTC 24
Finished Aug 28 09:24:34 PM UTC 24
Peak memory 211096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311848038 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.2311848038
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/9.adc_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.476348826
Short name T847
Test name
Test status
Simulation time 2744735786 ps
CPU time 18.92 seconds
Started Aug 28 09:24:31 PM UTC 24
Finished Aug 28 09:24:51 PM UTC 24
Peak memory 211268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476348826 -assert nopostproc
+UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_same_csr_outstanding.476348826
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1790011705
Short name T821
Test name
Test status
Simulation time 593083879 ps
CPU time 3.48 seconds
Started Aug 28 09:24:27 PM UTC 24
Finished Aug 28 09:24:31 PM UTC 24
Peak memory 211376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790011705 -assert nopostproc +UVM_TESTNAME=adc_ct
rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1790011705
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/9.adc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.533820784
Short name T832
Test name
Test status
Simulation time 4425907858 ps
CPU time 12.01 seconds
Started Aug 28 09:24:28 PM UTC 24
Finished Aug 28 09:24:41 PM UTC 24
Peak memory 211512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533820784 -assert nopostproc +UVM_TEST
NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_intg_err.533820784
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/9.adc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_clock_gating.2294333758
Short name T164
Test name
Test status
Simulation time 163658414759 ps
CPU time 333.79 seconds
Started Aug 28 08:12:10 PM UTC 24
Finished Aug 28 08:17:48 PM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294333758 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gating.2294333758
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_both.52866837
Short name T13
Test name
Test status
Simulation time 176119408177 ps
CPU time 88.64 seconds
Started Aug 28 08:12:10 PM UTC 24
Finished Aug 28 08:13:41 PM UTC 24
Peak memory 211432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52866837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_
SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.52866837
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/0.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt.4002865262
Short name T140
Test name
Test status
Simulation time 162352399020 ps
CPU time 528.3 seconds
Started Aug 28 08:12:09 PM UTC 24
Finished Aug 28 08:21:03 PM UTC 24
Peak memory 212568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002865262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.4002865262
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/0.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled.2272004094
Short name T47
Test name
Test status
Simulation time 331086070932 ps
CPU time 228.44 seconds
Started Aug 28 08:12:07 PM UTC 24
Finished Aug 28 08:15:59 PM UTC 24
Peak memory 211692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272004094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2272004094
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/0.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled_fixed.2340647382
Short name T187
Test name
Test status
Simulation time 167610733543 ps
CPU time 361.39 seconds
Started Aug 28 08:12:09 PM UTC 24
Finished Aug 28 08:18:14 PM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340647382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixed.2340647382
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup.2625747779
Short name T52
Test name
Test status
Simulation time 165118748736 ps
CPU time 236.42 seconds
Started Aug 28 08:12:10 PM UTC 24
Finished Aug 28 08:16:10 PM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625747779 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_wakeup.2625747779
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/0.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_lowpower_counter.1743275783
Short name T7
Test name
Test status
Simulation time 36281631855 ps
CPU time 18.49 seconds
Started Aug 28 08:12:11 PM UTC 24
Finished Aug 28 08:12:31 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743275783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.1743275783
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/0.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_smoke.3491688762
Short name T5
Test name
Test status
Simulation time 5541124473 ps
CPU time 19.21 seconds
Started Aug 28 08:12:07 PM UTC 24
Finished Aug 28 08:12:28 PM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491688762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3491688762
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/0.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.3936049292
Short name T3
Test name
Test status
Simulation time 3526027893 ps
CPU time 7.47 seconds
Started Aug 28 08:12:12 PM UTC 24
Finished Aug 28 08:12:21 PM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3936049292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.adc_ctrl_stress_all_with_rand_reset.3936049292
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_alert_test.947717143
Short name T22
Test name
Test status
Simulation time 509738009 ps
CPU time 1.28 seconds
Started Aug 28 08:12:31 PM UTC 24
Finished Aug 28 08:12:33 PM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947717143 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.947717143
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/1.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt.3500336381
Short name T156
Test name
Test status
Simulation time 324606470788 ps
CPU time 285.89 seconds
Started Aug 28 08:12:17 PM UTC 24
Finished Aug 28 08:17:07 PM UTC 24
Peak memory 211540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500336381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.3500336381
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/1.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt_fixed.4256944918
Short name T403
Test name
Test status
Simulation time 164405703475 ps
CPU time 571 seconds
Started Aug 28 08:12:17 PM UTC 24
Finished Aug 28 08:21:55 PM UTC 24
Peak memory 212676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256944918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt_fixed.4256944918
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled_fixed.2360216037
Short name T209
Test name
Test status
Simulation time 164218945591 ps
CPU time 521.87 seconds
Started Aug 28 08:12:16 PM UTC 24
Finished Aug 28 08:21:04 PM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360216037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixed.2360216037
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup.1131960305
Short name T154
Test name
Test status
Simulation time 282090320970 ps
CPU time 814.68 seconds
Started Aug 28 08:12:18 PM UTC 24
Finished Aug 28 08:26:02 PM UTC 24
Peak memory 212624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131960305 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_wakeup.1131960305
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/1.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup_fixed.2206387486
Short name T252
Test name
Test status
Simulation time 402308252239 ps
CPU time 544.63 seconds
Started Aug 28 08:12:18 PM UTC 24
Finished Aug 28 08:21:28 PM UTC 24
Peak memory 211460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206387486 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_wakeup_fixed.2206387486
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_lowpower_counter.3483751680
Short name T38
Test name
Test status
Simulation time 30750141684 ps
CPU time 81.81 seconds
Started Aug 28 08:12:25 PM UTC 24
Finished Aug 28 08:13:49 PM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483751680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.3483751680
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/1.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_poweron_counter.3388921658
Short name T4
Test name
Test status
Simulation time 3755356457 ps
CPU time 3.51 seconds
Started Aug 28 08:12:22 PM UTC 24
Finished Aug 28 08:12:27 PM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388921658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.3388921658
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/1.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_sec_cm.2158179728
Short name T23
Test name
Test status
Simulation time 7902656032 ps
CPU time 31.55 seconds
Started Aug 28 08:12:29 PM UTC 24
Finished Aug 28 08:13:02 PM UTC 24
Peak memory 243480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158179728 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.2158179728
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/1.adc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_smoke.1469406767
Short name T6
Test name
Test status
Simulation time 6139693779 ps
CPU time 13.75 seconds
Started Aug 28 08:12:15 PM UTC 24
Finished Aug 28 08:12:30 PM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469406767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.1469406767
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/1.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_alert_test.267120126
Short name T406
Test name
Test status
Simulation time 473422273 ps
CPU time 1.41 seconds
Started Aug 28 08:22:37 PM UTC 24
Finished Aug 28 08:22:39 PM UTC 24
Peak memory 210340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267120126 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.267120126
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/10.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_both.132362228
Short name T227
Test name
Test status
Simulation time 196724449358 ps
CPU time 612.05 seconds
Started Aug 28 08:21:55 PM UTC 24
Finished Aug 28 08:32:14 PM UTC 24
Peak memory 211604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132362228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.132362228
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/10.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt.313542026
Short name T321
Test name
Test status
Simulation time 329074671480 ps
CPU time 1064.15 seconds
Started Aug 28 08:21:21 PM UTC 24
Finished Aug 28 08:39:16 PM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313542026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.313542026
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/10.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt_fixed.4080295212
Short name T414
Test name
Test status
Simulation time 490210134800 ps
CPU time 229.16 seconds
Started Aug 28 08:21:22 PM UTC 24
Finished Aug 28 08:25:14 PM UTC 24
Peak memory 211852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080295212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt_fixed.4080295212
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled.1247355074
Short name T517
Test name
Test status
Simulation time 484826364230 ps
CPU time 1630.02 seconds
Started Aug 28 08:21:15 PM UTC 24
Finished Aug 28 08:48:42 PM UTC 24
Peak memory 212628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247355074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.1247355074
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/10.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled_fixed.4257163092
Short name T145
Test name
Test status
Simulation time 327603425616 ps
CPU time 110.54 seconds
Started Aug 28 08:21:15 PM UTC 24
Finished Aug 28 08:23:08 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257163092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixed.4257163092
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1137978395
Short name T424
Test name
Test status
Simulation time 581481862946 ps
CPU time 370.81 seconds
Started Aug 28 08:21:29 PM UTC 24
Finished Aug 28 08:27:44 PM UTC 24
Peak memory 211676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137978395 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_wakeup_fixed.1137978395
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_fsm_reset.1549728811
Short name T378
Test name
Test status
Simulation time 126570994027 ps
CPU time 867.17 seconds
Started Aug 28 08:22:08 PM UTC 24
Finished Aug 28 08:36:44 PM UTC 24
Peak memory 211772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549728811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1549728811
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/10.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_lowpower_counter.3379519410
Short name T413
Test name
Test status
Simulation time 37663190788 ps
CPU time 153.94 seconds
Started Aug 28 08:22:03 PM UTC 24
Finished Aug 28 08:24:40 PM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379519410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.3379519410
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/10.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_poweron_counter.4192047695
Short name T404
Test name
Test status
Simulation time 2856481103 ps
CPU time 3.65 seconds
Started Aug 28 08:21:57 PM UTC 24
Finished Aug 28 08:22:02 PM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192047695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.4192047695
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/10.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_smoke.1833645207
Short name T401
Test name
Test status
Simulation time 5820274715 ps
CPU time 4.57 seconds
Started Aug 28 08:21:09 PM UTC 24
Finished Aug 28 08:21:15 PM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833645207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.1833645207
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/10.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.486307072
Short name T28
Test name
Test status
Simulation time 244228177562 ps
CPU time 70.97 seconds
Started Aug 28 08:22:11 PM UTC 24
Finished Aug 28 08:23:24 PM UTC 24
Peak memory 221884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=486307072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
10.adc_ctrl_stress_all_with_rand_reset.486307072
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_alert_test.430211959
Short name T409
Test name
Test status
Simulation time 510753091 ps
CPU time 3.06 seconds
Started Aug 28 08:24:07 PM UTC 24
Finished Aug 28 08:24:11 PM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430211959 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.430211959
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/11.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_clock_gating.3531349195
Short name T331
Test name
Test status
Simulation time 530974706802 ps
CPU time 1279.61 seconds
Started Aug 28 08:23:23 PM UTC 24
Finished Aug 28 08:44:55 PM UTC 24
Peak memory 212496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531349195 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gating.3531349195
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/11.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_both.2916268109
Short name T152
Test name
Test status
Simulation time 337186309775 ps
CPU time 111.7 seconds
Started Aug 28 08:23:24 PM UTC 24
Finished Aug 28 08:25:18 PM UTC 24
Peak memory 211452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916268109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2916268109
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/11.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt.479654664
Short name T328
Test name
Test status
Simulation time 320877590191 ps
CPU time 996.89 seconds
Started Aug 28 08:22:56 PM UTC 24
Finished Aug 28 08:39:43 PM UTC 24
Peak memory 211748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479654664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.479654664
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/11.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3752143241
Short name T421
Test name
Test status
Simulation time 324893338452 ps
CPU time 220.41 seconds
Started Aug 28 08:23:07 PM UTC 24
Finished Aug 28 08:26:50 PM UTC 24
Peak memory 211536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752143241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt_fixed.3752143241
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled.277565680
Short name T195
Test name
Test status
Simulation time 329326300382 ps
CPU time 232.22 seconds
Started Aug 28 08:22:43 PM UTC 24
Finished Aug 28 08:26:38 PM UTC 24
Peak memory 211612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277565680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.277565680
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/11.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled_fixed.4195650166
Short name T466
Test name
Test status
Simulation time 317938839957 ps
CPU time 912.74 seconds
Started Aug 28 08:22:50 PM UTC 24
Finished Aug 28 08:38:12 PM UTC 24
Peak memory 211732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195650166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixed.4195650166
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup.2434662876
Short name T251
Test name
Test status
Simulation time 173111224594 ps
CPU time 337.3 seconds
Started Aug 28 08:23:09 PM UTC 24
Finished Aug 28 08:28:50 PM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434662876 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_wakeup.2434662876
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/11.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3576517084
Short name T453
Test name
Test status
Simulation time 609111031704 ps
CPU time 768.08 seconds
Started Aug 28 08:23:09 PM UTC 24
Finished Aug 28 08:36:05 PM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576517084 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_wakeup_fixed.3576517084
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_lowpower_counter.4267342449
Short name T411
Test name
Test status
Simulation time 30924779673 ps
CPU time 47.34 seconds
Started Aug 28 08:23:29 PM UTC 24
Finished Aug 28 08:24:18 PM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267342449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.4267342449
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/11.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_poweron_counter.2551446193
Short name T408
Test name
Test status
Simulation time 3411945203 ps
CPU time 1.86 seconds
Started Aug 28 08:23:25 PM UTC 24
Finished Aug 28 08:23:28 PM UTC 24
Peak memory 209864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551446193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.2551446193
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/11.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_smoke.2465908489
Short name T407
Test name
Test status
Simulation time 5799720272 ps
CPU time 13.31 seconds
Started Aug 28 08:22:41 PM UTC 24
Finished Aug 28 08:22:55 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465908489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.2465908489
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/11.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all.1209349444
Short name T155
Test name
Test status
Simulation time 349612649812 ps
CPU time 169.21 seconds
Started Aug 28 08:24:05 PM UTC 24
Finished Aug 28 08:26:56 PM UTC 24
Peak memory 211560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209349444 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.1209349444
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/11.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2219747612
Short name T216
Test name
Test status
Simulation time 15171017219 ps
CPU time 11.93 seconds
Started Aug 28 08:23:52 PM UTC 24
Finished Aug 28 08:24:06 PM UTC 24
Peak memory 221728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2219747612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.adc_ctrl_stress_all_with_rand_reset.2219747612
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_alert_test.3588178718
Short name T418
Test name
Test status
Simulation time 396557639 ps
CPU time 2.45 seconds
Started Aug 28 08:25:52 PM UTC 24
Finished Aug 28 08:25:55 PM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588178718 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3588178718
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/12.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt.1463098671
Short name T261
Test name
Test status
Simulation time 332712804174 ps
CPU time 873.42 seconds
Started Aug 28 08:24:39 PM UTC 24
Finished Aug 28 08:39:21 PM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463098671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.1463098671
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/12.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt_fixed.4042282362
Short name T420
Test name
Test status
Simulation time 161342684303 ps
CPU time 91.86 seconds
Started Aug 28 08:24:41 PM UTC 24
Finished Aug 28 08:26:15 PM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042282362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt_fixed.4042282362
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled.224299465
Short name T282
Test name
Test status
Simulation time 165970129614 ps
CPU time 204.39 seconds
Started Aug 28 08:24:13 PM UTC 24
Finished Aug 28 08:27:40 PM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224299465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.224299465
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/12.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled_fixed.2889082925
Short name T422
Test name
Test status
Simulation time 160594556348 ps
CPU time 156.38 seconds
Started Aug 28 08:24:19 PM UTC 24
Finished Aug 28 08:26:58 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889082925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fixed.2889082925
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup.1025822317
Short name T269
Test name
Test status
Simulation time 611890203188 ps
CPU time 2030.17 seconds
Started Aug 28 08:24:54 PM UTC 24
Finished Aug 28 08:59:03 PM UTC 24
Peak memory 212600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025822317 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_wakeup.1025822317
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/12.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup_fixed.2403321145
Short name T451
Test name
Test status
Simulation time 391152327196 ps
CPU time 623.5 seconds
Started Aug 28 08:25:14 PM UTC 24
Finished Aug 28 08:35:44 PM UTC 24
Peak memory 211736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403321145 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_wakeup_fixed.2403321145
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_fsm_reset.3198025972
Short name T379
Test name
Test status
Simulation time 105122499164 ps
CPU time 492.85 seconds
Started Aug 28 08:25:40 PM UTC 24
Finished Aug 28 08:33:57 PM UTC 24
Peak memory 212024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198025972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.3198025972
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/12.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_lowpower_counter.1901976879
Short name T417
Test name
Test status
Simulation time 37883473653 ps
CPU time 10.14 seconds
Started Aug 28 08:25:40 PM UTC 24
Finished Aug 28 08:25:51 PM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901976879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.1901976879
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/12.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_poweron_counter.2983989200
Short name T416
Test name
Test status
Simulation time 2991447829 ps
CPU time 13.74 seconds
Started Aug 28 08:25:23 PM UTC 24
Finished Aug 28 08:25:38 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983989200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2983989200
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/12.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_smoke.1460730833
Short name T412
Test name
Test status
Simulation time 5845964737 ps
CPU time 25.23 seconds
Started Aug 28 08:24:12 PM UTC 24
Finished Aug 28 08:24:38 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460730833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.1460730833
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/12.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1486062163
Short name T29
Test name
Test status
Simulation time 1626725210 ps
CPU time 8.13 seconds
Started Aug 28 08:25:48 PM UTC 24
Finished Aug 28 08:25:57 PM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1486062163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.adc_ctrl_stress_all_with_rand_reset.1486062163
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_alert_test.3814072123
Short name T425
Test name
Test status
Simulation time 496539714 ps
CPU time 2.86 seconds
Started Aug 28 08:27:42 PM UTC 24
Finished Aug 28 08:27:46 PM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814072123 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.3814072123
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/13.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_clock_gating.1999445435
Short name T191
Test name
Test status
Simulation time 520276376108 ps
CPU time 1248.45 seconds
Started Aug 28 08:26:38 PM UTC 24
Finished Aug 28 08:47:38 PM UTC 24
Peak memory 212560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999445435 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gating.1999445435
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/13.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_both.826966669
Short name T105
Test name
Test status
Simulation time 322119846767 ps
CPU time 893.69 seconds
Started Aug 28 08:26:51 PM UTC 24
Finished Aug 28 08:41:54 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826966669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.826966669
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/13.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt.1234812573
Short name T169
Test name
Test status
Simulation time 337286408439 ps
CPU time 1068.99 seconds
Started Aug 28 08:26:03 PM UTC 24
Finished Aug 28 08:44:03 PM UTC 24
Peak memory 212504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234812573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1234812573
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/13.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2199790541
Short name T434
Test name
Test status
Simulation time 163669987493 ps
CPU time 213.21 seconds
Started Aug 28 08:26:15 PM UTC 24
Finished Aug 28 08:29:52 PM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199790541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt_fixed.2199790541
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled.3419194619
Short name T527
Test name
Test status
Simulation time 486522509556 ps
CPU time 1492.54 seconds
Started Aug 28 08:25:58 PM UTC 24
Finished Aug 28 08:51:04 PM UTC 24
Peak memory 212500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419194619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.3419194619
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/13.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled_fixed.133917281
Short name T435
Test name
Test status
Simulation time 336064562613 ps
CPU time 242.32 seconds
Started Aug 28 08:26:00 PM UTC 24
Finished Aug 28 08:30:06 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133917281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixed.133917281
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup.4049468051
Short name T280
Test name
Test status
Simulation time 544136625119 ps
CPU time 840.1 seconds
Started Aug 28 08:26:28 PM UTC 24
Finished Aug 28 08:40:37 PM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049468051 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_wakeup.4049468051
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/13.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2461514753
Short name T486
Test name
Test status
Simulation time 397191459755 ps
CPU time 1033.75 seconds
Started Aug 28 08:26:32 PM UTC 24
Finished Aug 28 08:43:56 PM UTC 24
Peak memory 212616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461514753 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_wakeup_fixed.2461514753
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_fsm_reset.3771957792
Short name T108
Test name
Test status
Simulation time 102427948309 ps
CPU time 933.62 seconds
Started Aug 28 08:27:14 PM UTC 24
Finished Aug 28 08:42:58 PM UTC 24
Peak memory 211964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771957792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.3771957792
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/13.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_lowpower_counter.1177457846
Short name T427
Test name
Test status
Simulation time 34730973167 ps
CPU time 74.46 seconds
Started Aug 28 08:26:59 PM UTC 24
Finished Aug 28 08:28:15 PM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177457846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.1177457846
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/13.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_poweron_counter.2419700386
Short name T423
Test name
Test status
Simulation time 2973129305 ps
CPU time 14.17 seconds
Started Aug 28 08:26:58 PM UTC 24
Finished Aug 28 08:27:13 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419700386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2419700386
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/13.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_smoke.3885823875
Short name T419
Test name
Test status
Simulation time 6076351224 ps
CPU time 2.47 seconds
Started Aug 28 08:25:56 PM UTC 24
Finished Aug 28 08:25:59 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885823875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.3885823875
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/13.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.4120618834
Short name T30
Test name
Test status
Simulation time 3612674322 ps
CPU time 9.13 seconds
Started Aug 28 08:27:32 PM UTC 24
Finished Aug 28 08:27:42 PM UTC 24
Peak memory 211616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=4120618834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.adc_ctrl_stress_all_with_rand_reset.4120618834
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_alert_test.3604653724
Short name T431
Test name
Test status
Simulation time 386666727 ps
CPU time 1.37 seconds
Started Aug 28 08:28:51 PM UTC 24
Finished Aug 28 08:28:53 PM UTC 24
Peak memory 209796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604653724 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.3604653724
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/14.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_clock_gating.1002052933
Short name T232
Test name
Test status
Simulation time 594366225550 ps
CPU time 318.55 seconds
Started Aug 28 08:28:11 PM UTC 24
Finished Aug 28 08:33:34 PM UTC 24
Peak memory 211692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002052933 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gating.1002052933
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/14.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt.1126225918
Short name T167
Test name
Test status
Simulation time 486119908152 ps
CPU time 730.65 seconds
Started Aug 28 08:27:48 PM UTC 24
Finished Aug 28 08:40:07 PM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126225918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.1126225918
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/14.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2051495345
Short name T537
Test name
Test status
Simulation time 491159495257 ps
CPU time 1479.7 seconds
Started Aug 28 08:28:05 PM UTC 24
Finished Aug 28 08:52:59 PM UTC 24
Peak memory 212596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051495345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt_fixed.2051495345
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled.4291553929
Short name T287
Test name
Test status
Simulation time 160914719187 ps
CPU time 352.5 seconds
Started Aug 28 08:27:44 PM UTC 24
Finished Aug 28 08:33:41 PM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291553929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.4291553929
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/14.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled_fixed.427106205
Short name T545
Test name
Test status
Simulation time 486098071579 ps
CPU time 1537.68 seconds
Started Aug 28 08:27:46 PM UTC 24
Finished Aug 28 08:53:39 PM UTC 24
Peak memory 212796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427106205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixed.427106205
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup.2324605571
Short name T258
Test name
Test status
Simulation time 169807777472 ps
CPU time 403.63 seconds
Started Aug 28 08:28:06 PM UTC 24
Finished Aug 28 08:34:55 PM UTC 24
Peak memory 211544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324605571 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_wakeup.2324605571
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/14.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup_fixed.3928132886
Short name T443
Test name
Test status
Simulation time 600429399191 ps
CPU time 350.28 seconds
Started Aug 28 08:28:10 PM UTC 24
Finished Aug 28 08:34:04 PM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928132886 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_wakeup_fixed.3928132886
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_lowpower_counter.1423132694
Short name T430
Test name
Test status
Simulation time 31531226191 ps
CPU time 11.64 seconds
Started Aug 28 08:28:26 PM UTC 24
Finished Aug 28 08:28:39 PM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423132694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.1423132694
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/14.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_poweron_counter.3090601382
Short name T429
Test name
Test status
Simulation time 3344026257 ps
CPU time 2.85 seconds
Started Aug 28 08:28:25 PM UTC 24
Finished Aug 28 08:28:29 PM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090601382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.3090601382
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/14.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_smoke.2487287980
Short name T426
Test name
Test status
Simulation time 5998899366 ps
CPU time 3.15 seconds
Started Aug 28 08:27:43 PM UTC 24
Finished Aug 28 08:27:47 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487287980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2487287980
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/14.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_alert_test.665714543
Short name T438
Test name
Test status
Simulation time 418543842 ps
CPU time 1.27 seconds
Started Aug 28 08:30:39 PM UTC 24
Finished Aug 28 08:30:42 PM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665714543 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.665714543
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/15.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_both.2987346569
Short name T268
Test name
Test status
Simulation time 337216261276 ps
CPU time 819.92 seconds
Started Aug 28 08:30:07 PM UTC 24
Finished Aug 28 08:43:55 PM UTC 24
Peak memory 211712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987346569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2987346569
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/15.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt.908678921
Short name T310
Test name
Test status
Simulation time 167647827832 ps
CPU time 343.21 seconds
Started Aug 28 08:29:36 PM UTC 24
Finished Aug 28 08:35:24 PM UTC 24
Peak memory 211620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908678921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.908678921
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/15.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt_fixed.392689428
Short name T506
Test name
Test status
Simulation time 327688384346 ps
CPU time 1012.02 seconds
Started Aug 28 08:29:38 PM UTC 24
Finished Aug 28 08:46:41 PM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392689428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt_fixed.392689428
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled.274947651
Short name T175
Test name
Test status
Simulation time 325567037956 ps
CPU time 98.32 seconds
Started Aug 28 08:28:54 PM UTC 24
Finished Aug 28 08:30:34 PM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274947651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.274947651
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/15.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled_fixed.3175190778
Short name T447
Test name
Test status
Simulation time 320697272625 ps
CPU time 306.44 seconds
Started Aug 28 08:29:20 PM UTC 24
Finished Aug 28 08:34:31 PM UTC 24
Peak memory 211672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175190778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixed.3175190778
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup.2761377451
Short name T176
Test name
Test status
Simulation time 628089875578 ps
CPU time 330.05 seconds
Started Aug 28 08:29:48 PM UTC 24
Finished Aug 28 08:35:22 PM UTC 24
Peak memory 211392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761377451 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_wakeup.2761377451
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/15.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup_fixed.539458943
Short name T473
Test name
Test status
Simulation time 396102524377 ps
CPU time 620.44 seconds
Started Aug 28 08:29:53 PM UTC 24
Finished Aug 28 08:40:20 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539458943 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_wakeup_fixed.539458943
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_fsm_reset.3029147309
Short name T464
Test name
Test status
Simulation time 74723339662 ps
CPU time 439.57 seconds
Started Aug 28 08:30:26 PM UTC 24
Finished Aug 28 08:37:51 PM UTC 24
Peak memory 211772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029147309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3029147309
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/15.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_lowpower_counter.4091962162
Short name T437
Test name
Test status
Simulation time 41231595391 ps
CPU time 20.34 seconds
Started Aug 28 08:30:19 PM UTC 24
Finished Aug 28 08:30:41 PM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091962162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.4091962162
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/15.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_poweron_counter.3170601345
Short name T436
Test name
Test status
Simulation time 3234880466 ps
CPU time 5.59 seconds
Started Aug 28 08:30:12 PM UTC 24
Finished Aug 28 08:30:18 PM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170601345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3170601345
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/15.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_smoke.395901525
Short name T432
Test name
Test status
Simulation time 6067065123 ps
CPU time 26.06 seconds
Started Aug 28 08:28:52 PM UTC 24
Finished Aug 28 08:29:19 PM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395901525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.395901525
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/15.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all.1800252701
Short name T266
Test name
Test status
Simulation time 331641166304 ps
CPU time 1043.19 seconds
Started Aug 28 08:30:35 PM UTC 24
Finished Aug 28 08:48:08 PM UTC 24
Peak memory 212548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800252701 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.1800252701
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1340738491
Short name T245
Test name
Test status
Simulation time 2607852594 ps
CPU time 5.76 seconds
Started Aug 28 08:30:31 PM UTC 24
Finished Aug 28 08:30:38 PM UTC 24
Peak memory 211332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1340738491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.adc_ctrl_stress_all_with_rand_reset.1340738491
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_alert_test.3602900250
Short name T444
Test name
Test status
Simulation time 410810687 ps
CPU time 1.9 seconds
Started Aug 28 08:34:05 PM UTC 24
Finished Aug 28 08:34:08 PM UTC 24
Peak memory 209796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602900250 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.3602900250
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/16.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_both.3477954585
Short name T213
Test name
Test status
Simulation time 547002341487 ps
CPU time 1593.71 seconds
Started Aug 28 08:33:35 PM UTC 24
Finished Aug 28 09:00:24 PM UTC 24
Peak memory 212524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477954585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3477954585
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/16.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt.3189358946
Short name T249
Test name
Test status
Simulation time 490942662977 ps
CPU time 339.47 seconds
Started Aug 28 08:31:32 PM UTC 24
Finished Aug 28 08:37:15 PM UTC 24
Peak memory 211428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189358946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.3189358946
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/16.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt_fixed.889788962
Short name T507
Test name
Test status
Simulation time 327858065625 ps
CPU time 900.24 seconds
Started Aug 28 08:31:36 PM UTC 24
Finished Aug 28 08:46:45 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889788962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt_fixed.889788962
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled.1072977887
Short name T275
Test name
Test status
Simulation time 161648527410 ps
CPU time 421.07 seconds
Started Aug 28 08:30:42 PM UTC 24
Finished Aug 28 08:37:48 PM UTC 24
Peak memory 211428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072977887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.1072977887
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/16.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled_fixed.1635358545
Short name T455
Test name
Test status
Simulation time 328442647044 ps
CPU time 325.26 seconds
Started Aug 28 08:30:57 PM UTC 24
Finished Aug 28 08:36:27 PM UTC 24
Peak memory 211388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635358545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixed.1635358545
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1388840391
Short name T448
Test name
Test status
Simulation time 199480098884 ps
CPU time 142.1 seconds
Started Aug 28 08:32:14 PM UTC 24
Finished Aug 28 08:34:39 PM UTC 24
Peak memory 211736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388840391 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_wakeup_fixed.1388840391
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_fsm_reset.542044241
Short name T95
Test name
Test status
Simulation time 133129271886 ps
CPU time 914.82 seconds
Started Aug 28 08:33:58 PM UTC 24
Finished Aug 28 08:49:22 PM UTC 24
Peak memory 212028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542044241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.542044241
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/16.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_lowpower_counter.1195961786
Short name T442
Test name
Test status
Simulation time 36885013254 ps
CPU time 12.48 seconds
Started Aug 28 08:33:51 PM UTC 24
Finished Aug 28 08:34:04 PM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195961786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1195961786
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/16.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_poweron_counter.347723545
Short name T441
Test name
Test status
Simulation time 5373951892 ps
CPU time 6.8 seconds
Started Aug 28 08:33:42 PM UTC 24
Finished Aug 28 08:33:50 PM UTC 24
Peak memory 211196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347723545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.347723545
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/16.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_smoke.3057593746
Short name T439
Test name
Test status
Simulation time 5871637102 ps
CPU time 13.87 seconds
Started Aug 28 08:30:41 PM UTC 24
Finished Aug 28 08:30:56 PM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057593746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3057593746
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/16.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.290228815
Short name T254
Test name
Test status
Simulation time 20005321704 ps
CPU time 18.69 seconds
Started Aug 28 08:34:02 PM UTC 24
Finished Aug 28 08:34:22 PM UTC 24
Peak memory 222080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=290228815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
16.adc_ctrl_stress_all_with_rand_reset.290228815
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_alert_test.2056102290
Short name T450
Test name
Test status
Simulation time 375593451 ps
CPU time 1.27 seconds
Started Aug 28 08:35:24 PM UTC 24
Finished Aug 28 08:35:26 PM UTC 24
Peak memory 209796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056102290 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2056102290
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/17.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_clock_gating.189186987
Short name T201
Test name
Test status
Simulation time 563199772136 ps
CPU time 1182.93 seconds
Started Aug 28 08:34:46 PM UTC 24
Finished Aug 28 08:54:40 PM UTC 24
Peak memory 212688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189186987 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gating.189186987
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/17.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_both.2690607245
Short name T281
Test name
Test status
Simulation time 504197704164 ps
CPU time 1157.83 seconds
Started Aug 28 08:34:56 PM UTC 24
Finished Aug 28 08:54:24 PM UTC 24
Peak memory 212556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690607245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.2690607245
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/17.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt.813884970
Short name T190
Test name
Test status
Simulation time 328536173385 ps
CPU time 70.48 seconds
Started Aug 28 08:34:22 PM UTC 24
Finished Aug 28 08:35:34 PM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813884970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.813884970
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/17.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1177403349
Short name T454
Test name
Test status
Simulation time 164354297015 ps
CPU time 111.32 seconds
Started Aug 28 08:34:31 PM UTC 24
Finished Aug 28 08:36:25 PM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177403349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt_fixed.1177403349
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled.2792347089
Short name T197
Test name
Test status
Simulation time 322461932411 ps
CPU time 238.64 seconds
Started Aug 28 08:34:15 PM UTC 24
Finished Aug 28 08:38:17 PM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792347089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2792347089
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/17.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled_fixed.2204302707
Short name T539
Test name
Test status
Simulation time 324381796577 ps
CPU time 1119.81 seconds
Started Aug 28 08:34:18 PM UTC 24
Finished Aug 28 08:53:09 PM UTC 24
Peak memory 212556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204302707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixed.2204302707
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup_fixed.988887221
Short name T475
Test name
Test status
Simulation time 197590083599 ps
CPU time 362.57 seconds
Started Aug 28 08:34:39 PM UTC 24
Finished Aug 28 08:40:46 PM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988887221 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_wakeup_fixed.988887221
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_fsm_reset.3633796566
Short name T529
Test name
Test status
Simulation time 136698278276 ps
CPU time 983.21 seconds
Started Aug 28 08:35:07 PM UTC 24
Finished Aug 28 08:51:40 PM UTC 24
Peak memory 211812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633796566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.3633796566
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/17.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_lowpower_counter.1172729456
Short name T461
Test name
Test status
Simulation time 41031720678 ps
CPU time 151.73 seconds
Started Aug 28 08:35:04 PM UTC 24
Finished Aug 28 08:37:38 PM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172729456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.1172729456
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/17.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_poweron_counter.3678008205
Short name T449
Test name
Test status
Simulation time 5440513135 ps
CPU time 4.38 seconds
Started Aug 28 08:35:01 PM UTC 24
Finished Aug 28 08:35:06 PM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678008205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.3678008205
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/17.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_smoke.3573794879
Short name T446
Test name
Test status
Simulation time 5952435735 ps
CPU time 7.11 seconds
Started Aug 28 08:34:09 PM UTC 24
Finished Aug 28 08:34:17 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573794879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3573794879
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/17.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all.1490832521
Short name T355
Test name
Test status
Simulation time 238098373780 ps
CPU time 552.76 seconds
Started Aug 28 08:35:23 PM UTC 24
Finished Aug 28 08:44:42 PM UTC 24
Peak memory 211604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490832521 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.1490832521
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_alert_test.1508534948
Short name T459
Test name
Test status
Simulation time 371795202 ps
CPU time 2.39 seconds
Started Aug 28 08:37:16 PM UTC 24
Finished Aug 28 08:37:20 PM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508534948 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.1508534948
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/18.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_clock_gating.3403888957
Short name T306
Test name
Test status
Simulation time 489750264749 ps
CPU time 945.96 seconds
Started Aug 28 08:36:12 PM UTC 24
Finished Aug 28 08:52:07 PM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403888957 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gating.3403888957
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/18.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_both.2971772204
Short name T288
Test name
Test status
Simulation time 175564309084 ps
CPU time 511.33 seconds
Started Aug 28 08:36:26 PM UTC 24
Finished Aug 28 08:45:03 PM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971772204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2971772204
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/18.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt.364513298
Short name T493
Test name
Test status
Simulation time 165978636078 ps
CPU time 524.03 seconds
Started Aug 28 08:35:45 PM UTC 24
Finished Aug 28 08:44:35 PM UTC 24
Peak memory 211428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364513298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.364513298
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/18.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1962486402
Short name T543
Test name
Test status
Simulation time 329841102852 ps
CPU time 1055.49 seconds
Started Aug 28 08:35:46 PM UTC 24
Finished Aug 28 08:53:33 PM UTC 24
Peak memory 212480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962486402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt_fixed.1962486402
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled.194571936
Short name T196
Test name
Test status
Simulation time 165892810699 ps
CPU time 144.06 seconds
Started Aug 28 08:35:35 PM UTC 24
Finished Aug 28 08:38:02 PM UTC 24
Peak memory 211680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194571936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.194571936
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/18.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled_fixed.2873615588
Short name T500
Test name
Test status
Simulation time 325416262066 ps
CPU time 610.09 seconds
Started Aug 28 08:35:43 PM UTC 24
Finished Aug 28 08:46:01 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873615588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixed.2873615588
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_wakeup_fixed.261806290
Short name T470
Test name
Test status
Simulation time 586599730819 ps
CPU time 218.14 seconds
Started Aug 28 08:36:07 PM UTC 24
Finished Aug 28 08:39:48 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261806290 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_wakeup_fixed.261806290
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_fsm_reset.451816711
Short name T502
Test name
Test status
Simulation time 107783039010 ps
CPU time 567.9 seconds
Started Aug 28 08:36:45 PM UTC 24
Finished Aug 28 08:46:18 PM UTC 24
Peak memory 212076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451816711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.451816711
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/18.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_lowpower_counter.1668140957
Short name T457
Test name
Test status
Simulation time 29979349557 ps
CPU time 30.04 seconds
Started Aug 28 08:36:38 PM UTC 24
Finished Aug 28 08:37:09 PM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668140957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.1668140957
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/18.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_poweron_counter.1370266051
Short name T456
Test name
Test status
Simulation time 3756486387 ps
CPU time 8.37 seconds
Started Aug 28 08:36:28 PM UTC 24
Finished Aug 28 08:36:37 PM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370266051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1370266051
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/18.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_smoke.3852412114
Short name T452
Test name
Test status
Simulation time 5496043885 ps
CPU time 16.86 seconds
Started Aug 28 08:35:27 PM UTC 24
Finished Aug 28 08:35:45 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852412114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.3852412114
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/18.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all.4090471721
Short name T364
Test name
Test status
Simulation time 166661877011 ps
CPU time 604.02 seconds
Started Aug 28 08:37:11 PM UTC 24
Finished Aug 28 08:47:22 PM UTC 24
Peak memory 211464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090471721 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.4090471721
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/18.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3333363870
Short name T31
Test name
Test status
Simulation time 6409790163 ps
CPU time 7.32 seconds
Started Aug 28 08:37:10 PM UTC 24
Finished Aug 28 08:37:19 PM UTC 24
Peak memory 222156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3333363870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.adc_ctrl_stress_all_with_rand_reset.3333363870
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_alert_test.2808020517
Short name T468
Test name
Test status
Simulation time 344748478 ps
CPU time 2.2 seconds
Started Aug 28 08:38:13 PM UTC 24
Finished Aug 28 08:38:17 PM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808020517 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2808020517
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/19.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_both.949590895
Short name T230
Test name
Test status
Simulation time 162230380843 ps
CPU time 84.82 seconds
Started Aug 28 08:37:49 PM UTC 24
Finished Aug 28 08:39:16 PM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949590895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.949590895
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/19.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_interrupt.3578164931
Short name T259
Test name
Test status
Simulation time 162860146514 ps
CPU time 191.66 seconds
Started Aug 28 08:37:22 PM UTC 24
Finished Aug 28 08:40:36 PM UTC 24
Peak memory 211692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578164931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3578164931
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/19.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3160197035
Short name T476
Test name
Test status
Simulation time 328018185731 ps
CPU time 196.33 seconds
Started Aug 28 08:37:28 PM UTC 24
Finished Aug 28 08:40:47 PM UTC 24
Peak memory 211536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160197035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt_fixed.3160197035
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled.71883431
Short name T483
Test name
Test status
Simulation time 165022801946 ps
CPU time 249.92 seconds
Started Aug 28 08:37:19 PM UTC 24
Finished Aug 28 08:41:33 PM UTC 24
Peak memory 211680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71883431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_
SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.71883431
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/19.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled_fixed.2956668353
Short name T467
Test name
Test status
Simulation time 166833254675 ps
CPU time 50.65 seconds
Started Aug 28 08:37:21 PM UTC 24
Finished Aug 28 08:38:13 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956668353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixed.2956668353
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup.2438808260
Short name T489
Test name
Test status
Simulation time 171925021019 ps
CPU time 401.51 seconds
Started Aug 28 08:37:32 PM UTC 24
Finished Aug 28 08:44:18 PM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438808260 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_wakeup.2438808260
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/19.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup_fixed.1385766227
Short name T655
Test name
Test status
Simulation time 598092375106 ps
CPU time 1977.64 seconds
Started Aug 28 08:37:39 PM UTC 24
Finished Aug 28 09:10:55 PM UTC 24
Peak memory 212484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385766227 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_wakeup_fixed.1385766227
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_lowpower_counter.2164752967
Short name T474
Test name
Test status
Simulation time 32326351144 ps
CPU time 150.59 seconds
Started Aug 28 08:38:02 PM UTC 24
Finished Aug 28 08:40:35 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164752967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2164752967
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/19.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_poweron_counter.3405073631
Short name T465
Test name
Test status
Simulation time 5229622159 ps
CPU time 12.7 seconds
Started Aug 28 08:37:52 PM UTC 24
Finished Aug 28 08:38:06 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405073631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.3405073631
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/19.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_smoke.1368239123
Short name T460
Test name
Test status
Simulation time 5993440994 ps
CPU time 13.49 seconds
Started Aug 28 08:37:16 PM UTC 24
Finished Aug 28 08:37:31 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368239123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1368239123
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/19.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all.3158207999
Short name T386
Test name
Test status
Simulation time 426865152067 ps
CPU time 1453.5 seconds
Started Aug 28 08:38:13 PM UTC 24
Finished Aug 28 09:02:40 PM UTC 24
Peak memory 212876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158207999 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.3158207999
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/19.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.2478307724
Short name T32
Test name
Test status
Simulation time 617099386 ps
CPU time 3.65 seconds
Started Aug 28 08:38:11 PM UTC 24
Finished Aug 28 08:38:16 PM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2478307724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.adc_ctrl_stress_all_with_rand_reset.2478307724
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_alert_test.168619147
Short name T24
Test name
Test status
Simulation time 430963781 ps
CPU time 1.36 seconds
Started Aug 28 08:13:10 PM UTC 24
Finished Aug 28 08:13:12 PM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168619147 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.168619147
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/2.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.3556648386
Short name T236
Test name
Test status
Simulation time 645364121706 ps
CPU time 1319.13 seconds
Started Aug 28 08:12:47 PM UTC 24
Finished Aug 28 08:35:00 PM UTC 24
Peak memory 212496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556648386 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gating.3556648386
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/2.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3116619407
Short name T393
Test name
Test status
Simulation time 164512247894 ps
CPU time 366.45 seconds
Started Aug 28 08:12:39 PM UTC 24
Finished Aug 28 08:18:50 PM UTC 24
Peak memory 211604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116619407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt_fixed.3116619407
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled.4056358286
Short name T17
Test name
Test status
Simulation time 161565649642 ps
CPU time 138.82 seconds
Started Aug 28 08:12:34 PM UTC 24
Finished Aug 28 08:14:55 PM UTC 24
Peak memory 211564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056358286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.4056358286
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/2.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled_fixed.3354304556
Short name T402
Test name
Test status
Simulation time 328970712480 ps
CPU time 520.28 seconds
Started Aug 28 08:12:34 PM UTC 24
Finished Aug 28 08:21:20 PM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354304556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed.3354304556
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup.829383338
Short name T15
Test name
Test status
Simulation time 179926049724 ps
CPU time 101.13 seconds
Started Aug 28 08:12:39 PM UTC 24
Finished Aug 28 08:14:22 PM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829383338 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_wakeup.829383338
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/2.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup_fixed.1640202378
Short name T109
Test name
Test status
Simulation time 593066940573 ps
CPU time 1803.5 seconds
Started Aug 28 08:12:44 PM UTC 24
Finished Aug 28 08:43:05 PM UTC 24
Peak memory 212468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640202378 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_wakeup_fixed.1640202378
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_lowpower_counter.2449114790
Short name T39
Test name
Test status
Simulation time 27897267575 ps
CPU time 51.81 seconds
Started Aug 28 08:12:58 PM UTC 24
Finished Aug 28 08:13:51 PM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449114790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2449114790
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/2.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_poweron_counter.1278528939
Short name T10
Test name
Test status
Simulation time 2904502740 ps
CPU time 6.68 seconds
Started Aug 28 08:12:49 PM UTC 24
Finished Aug 28 08:12:57 PM UTC 24
Peak memory 211200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278528939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.1278528939
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/2.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_sec_cm.3291427233
Short name T25
Test name
Test status
Simulation time 4045192035 ps
CPU time 5.81 seconds
Started Aug 28 08:13:08 PM UTC 24
Finished Aug 28 08:13:15 PM UTC 24
Peak memory 243556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291427233 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3291427233
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/2.adc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_smoke.3262022700
Short name T9
Test name
Test status
Simulation time 5653513449 ps
CPU time 4.27 seconds
Started Aug 28 08:12:33 PM UTC 24
Finished Aug 28 08:12:38 PM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262022700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3262022700
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/2.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all.3364614012
Short name T11
Test name
Test status
Simulation time 6442271639 ps
CPU time 6.01 seconds
Started Aug 28 08:13:05 PM UTC 24
Finished Aug 28 08:13:12 PM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364614012 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.3364614012
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_alert_test.274907217
Short name T471
Test name
Test status
Simulation time 367188139 ps
CPU time 1.29 seconds
Started Aug 28 08:39:49 PM UTC 24
Finished Aug 28 08:39:51 PM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274907217 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.274907217
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/20.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_clock_gating.1899985576
Short name T211
Test name
Test status
Simulation time 509519745091 ps
CPU time 298 seconds
Started Aug 28 08:39:01 PM UTC 24
Finished Aug 28 08:44:02 PM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899985576 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gating.1899985576
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/20.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_both.637882351
Short name T260
Test name
Test status
Simulation time 174486379057 ps
CPU time 114.25 seconds
Started Aug 28 08:39:16 PM UTC 24
Finished Aug 28 08:41:12 PM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637882351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.637882351
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/20.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_interrupt.2897001063
Short name T338
Test name
Test status
Simulation time 169013810052 ps
CPU time 169.34 seconds
Started Aug 28 08:38:33 PM UTC 24
Finished Aug 28 08:41:25 PM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897001063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.2897001063
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/20.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2268296346
Short name T496
Test name
Test status
Simulation time 327274395861 ps
CPU time 355.15 seconds
Started Aug 28 08:38:55 PM UTC 24
Finished Aug 28 08:44:54 PM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268296346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt_fixed.2268296346
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_polled.3793805652
Short name T106
Test name
Test status
Simulation time 164397099544 ps
CPU time 219.89 seconds
Started Aug 28 08:38:18 PM UTC 24
Finished Aug 28 08:42:00 PM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793805652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3793805652
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/20.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_polled_fixed.81657528
Short name T511
Test name
Test status
Simulation time 490275827464 ps
CPU time 550.25 seconds
Started Aug 28 08:38:18 PM UTC 24
Finished Aug 28 08:47:34 PM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81657528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixed.81657528
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_wakeup.3673525011
Short name T567
Test name
Test status
Simulation time 407905003003 ps
CPU time 1146.38 seconds
Started Aug 28 08:38:55 PM UTC 24
Finished Aug 28 08:58:12 PM UTC 24
Peak memory 212484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673525011 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_wakeup.3673525011
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/20.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_wakeup_fixed.67291340
Short name T638
Test name
Test status
Simulation time 603617357034 ps
CPU time 1748.92 seconds
Started Aug 28 08:38:58 PM UTC 24
Finished Aug 28 09:08:23 PM UTC 24
Peak memory 212872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67291340 -assert nopostpro
c +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_wakeup_fixed.67291340
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_fsm_reset.265139970
Short name T387
Test name
Test status
Simulation time 97831835516 ps
CPU time 473.72 seconds
Started Aug 28 08:39:23 PM UTC 24
Finished Aug 28 08:47:22 PM UTC 24
Peak memory 211744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265139970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.265139970
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/20.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_lowpower_counter.1833625146
Short name T478
Test name
Test status
Simulation time 28033063931 ps
CPU time 96.8 seconds
Started Aug 28 08:39:21 PM UTC 24
Finished Aug 28 08:41:00 PM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833625146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1833625146
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/20.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_poweron_counter.3694348451
Short name T469
Test name
Test status
Simulation time 4031668202 ps
CPU time 4.66 seconds
Started Aug 28 08:39:17 PM UTC 24
Finished Aug 28 08:39:23 PM UTC 24
Peak memory 211220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694348451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.3694348451
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/20.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_smoke.3430696280
Short name T463
Test name
Test status
Simulation time 5935686257 ps
CPU time 14.38 seconds
Started Aug 28 08:38:16 PM UTC 24
Finished Aug 28 08:38:32 PM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430696280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3430696280
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/20.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2658924262
Short name T69
Test name
Test status
Simulation time 3820233339 ps
CPU time 24.47 seconds
Started Aug 28 08:39:36 PM UTC 24
Finished Aug 28 08:40:02 PM UTC 24
Peak memory 222024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2658924262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 20.adc_ctrl_stress_all_with_rand_reset.2658924262
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_alert_test.2511622917
Short name T481
Test name
Test status
Simulation time 499462962 ps
CPU time 2.93 seconds
Started Aug 28 08:41:25 PM UTC 24
Finished Aug 28 08:41:29 PM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511622917 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.2511622917
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/21.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_clock_gating.4289041764
Short name T285
Test name
Test status
Simulation time 486257083358 ps
CPU time 1217.26 seconds
Started Aug 28 08:40:38 PM UTC 24
Finished Aug 28 09:01:07 PM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289041764 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gating.4289041764
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/21.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_both.1356670463
Short name T521
Test name
Test status
Simulation time 166558726674 ps
CPU time 491.11 seconds
Started Aug 28 08:40:47 PM UTC 24
Finished Aug 28 08:49:04 PM UTC 24
Peak memory 211448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356670463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.1356670463
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/21.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_interrupt_fixed.4134064951
Short name T492
Test name
Test status
Simulation time 331264785793 ps
CPU time 249.7 seconds
Started Aug 28 08:40:21 PM UTC 24
Finished Aug 28 08:44:34 PM UTC 24
Peak memory 211544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134064951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt_fixed.4134064951
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_polled.3996196851
Short name T308
Test name
Test status
Simulation time 165085668364 ps
CPU time 226.9 seconds
Started Aug 28 08:40:01 PM UTC 24
Finished Aug 28 08:43:51 PM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996196851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.3996196851
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/21.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_polled_fixed.3898303257
Short name T635
Test name
Test status
Simulation time 486185202270 ps
CPU time 1653.52 seconds
Started Aug 28 08:40:03 PM UTC 24
Finished Aug 28 09:07:53 PM UTC 24
Peak memory 212596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898303257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fixed.3898303257
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_wakeup_fixed.325018505
Short name T111
Test name
Test status
Simulation time 593866830971 ps
CPU time 163.8 seconds
Started Aug 28 08:40:37 PM UTC 24
Finished Aug 28 08:43:23 PM UTC 24
Peak memory 211796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325018505 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_wakeup_fixed.325018505
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_fsm_reset.2881997834
Short name T544
Test name
Test status
Simulation time 101387395490 ps
CPU time 744.86 seconds
Started Aug 28 08:41:00 PM UTC 24
Finished Aug 28 08:53:33 PM UTC 24
Peak memory 212028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881997834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.2881997834
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/21.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_lowpower_counter.3679794155
Short name T479
Test name
Test status
Simulation time 34591016363 ps
CPU time 16.2 seconds
Started Aug 28 08:40:52 PM UTC 24
Finished Aug 28 08:41:10 PM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679794155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.3679794155
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/21.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_poweron_counter.729192569
Short name T477
Test name
Test status
Simulation time 4642871777 ps
CPU time 3.41 seconds
Started Aug 28 08:40:47 PM UTC 24
Finished Aug 28 08:40:52 PM UTC 24
Peak memory 211296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729192569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.729192569
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/21.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_smoke.3047507354
Short name T472
Test name
Test status
Simulation time 6025453146 ps
CPU time 7.1 seconds
Started Aug 28 08:39:52 PM UTC 24
Finished Aug 28 08:40:00 PM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047507354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.3047507354
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/21.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_stress_all.3430964003
Short name T113
Test name
Test status
Simulation time 164839472901 ps
CPU time 140.46 seconds
Started Aug 28 08:41:14 PM UTC 24
Finished Aug 28 08:43:36 PM UTC 24
Peak memory 211664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430964003 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.3430964003
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/21.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.677986568
Short name T70
Test name
Test status
Simulation time 25344340333 ps
CPU time 37.84 seconds
Started Aug 28 08:41:11 PM UTC 24
Finished Aug 28 08:41:50 PM UTC 24
Peak memory 228080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=677986568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
21.adc_ctrl_stress_all_with_rand_reset.677986568
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_alert_test.2813949865
Short name T484
Test name
Test status
Simulation time 507952315 ps
CPU time 1.41 seconds
Started Aug 28 08:43:39 PM UTC 24
Finished Aug 28 08:43:42 PM UTC 24
Peak memory 209796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813949865 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.2813949865
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/22.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_both.3536656730
Short name T170
Test name
Test status
Simulation time 330557407567 ps
CPU time 131.34 seconds
Started Aug 28 08:42:59 PM UTC 24
Finished Aug 28 08:45:12 PM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536656730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.3536656730
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/22.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_interrupt.3305401661
Short name T292
Test name
Test status
Simulation time 166007854282 ps
CPU time 174.26 seconds
Started Aug 28 08:41:33 PM UTC 24
Finished Aug 28 08:44:30 PM UTC 24
Peak memory 211560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305401661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3305401661
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/22.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_interrupt_fixed.223773292
Short name T501
Test name
Test status
Simulation time 322738101309 ps
CPU time 258.57 seconds
Started Aug 28 08:41:51 PM UTC 24
Finished Aug 28 08:46:13 PM UTC 24
Peak memory 211604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223773292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt_fixed.223773292
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_polled.1830167153
Short name T495
Test name
Test status
Simulation time 168918674307 ps
CPU time 197.11 seconds
Started Aug 28 08:41:30 PM UTC 24
Finished Aug 28 08:44:49 PM UTC 24
Peak memory 211688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830167153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.1830167153
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/22.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_polled_fixed.2092950839
Short name T523
Test name
Test status
Simulation time 326377861410 ps
CPU time 524.15 seconds
Started Aug 28 08:41:31 PM UTC 24
Finished Aug 28 08:50:21 PM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092950839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixed.2092950839
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_wakeup_fixed.2400289492
Short name T485
Test name
Test status
Simulation time 190318934781 ps
CPU time 108 seconds
Started Aug 28 08:42:01 PM UTC 24
Finished Aug 28 08:43:51 PM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400289492 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_wakeup_fixed.2400289492
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_fsm_reset.255364531
Short name T564
Test name
Test status
Simulation time 139292745419 ps
CPU time 833.02 seconds
Started Aug 28 08:43:24 PM UTC 24
Finished Aug 28 08:57:26 PM UTC 24
Peak memory 211720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255364531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.255364531
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/22.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_lowpower_counter.1516034809
Short name T490
Test name
Test status
Simulation time 38666999722 ps
CPU time 72.51 seconds
Started Aug 28 08:43:13 PM UTC 24
Finished Aug 28 08:44:27 PM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516034809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1516034809
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/22.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_poweron_counter.1317519678
Short name T112
Test name
Test status
Simulation time 4364693186 ps
CPU time 18.96 seconds
Started Aug 28 08:43:06 PM UTC 24
Finished Aug 28 08:43:26 PM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317519678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.1317519678
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/22.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_smoke.2472428770
Short name T482
Test name
Test status
Simulation time 5895827771 ps
CPU time 3.21 seconds
Started Aug 28 08:41:26 PM UTC 24
Finished Aug 28 08:41:30 PM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472428770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.2472428770
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/22.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_stress_all.3166296748
Short name T625
Test name
Test status
Simulation time 520591719535 ps
CPU time 1375.36 seconds
Started Aug 28 08:43:37 PM UTC 24
Finished Aug 28 09:06:46 PM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166296748 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.3166296748
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/22.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.680194184
Short name T168
Test name
Test status
Simulation time 6973168499 ps
CPU time 10.09 seconds
Started Aug 28 08:43:27 PM UTC 24
Finished Aug 28 08:43:38 PM UTC 24
Peak memory 211344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=680194184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
22.adc_ctrl_stress_all_with_rand_reset.680194184
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_alert_test.3986556343
Short name T494
Test name
Test status
Simulation time 348423922 ps
CPU time 1.23 seconds
Started Aug 28 08:44:35 PM UTC 24
Finished Aug 28 08:44:37 PM UTC 24
Peak memory 209796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986556343 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.3986556343
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/23.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_clock_gating.211657954
Short name T358
Test name
Test status
Simulation time 170258811838 ps
CPU time 397.77 seconds
Started Aug 28 08:44:09 PM UTC 24
Finished Aug 28 08:50:51 PM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211657954 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gating.211657954
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/23.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_both.1469697744
Short name T368
Test name
Test status
Simulation time 207025747887 ps
CPU time 734.4 seconds
Started Aug 28 08:44:09 PM UTC 24
Finished Aug 28 08:56:31 PM UTC 24
Peak memory 211716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469697744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.1469697744
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/23.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_interrupt_fixed.3100308499
Short name T650
Test name
Test status
Simulation time 500639957250 ps
CPU time 1559.56 seconds
Started Aug 28 08:43:57 PM UTC 24
Finished Aug 28 09:10:11 PM UTC 24
Peak memory 212668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100308499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt_fixed.3100308499
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_polled.1996155637
Short name T555
Test name
Test status
Simulation time 324870046075 ps
CPU time 695.65 seconds
Started Aug 28 08:43:52 PM UTC 24
Finished Aug 28 08:55:35 PM UTC 24
Peak memory 211688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996155637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.1996155637
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/23.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_polled_fixed.1581981693
Short name T538
Test name
Test status
Simulation time 325785929322 ps
CPU time 550.79 seconds
Started Aug 28 08:43:52 PM UTC 24
Finished Aug 28 08:53:09 PM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581981693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixed.1581981693
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_wakeup.1792910826
Short name T289
Test name
Test status
Simulation time 198232028479 ps
CPU time 717.52 seconds
Started Aug 28 08:44:04 PM UTC 24
Finished Aug 28 08:56:09 PM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792910826 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_wakeup.1792910826
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/23.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_wakeup_fixed.724065351
Short name T516
Test name
Test status
Simulation time 392505724801 ps
CPU time 261.13 seconds
Started Aug 28 08:44:04 PM UTC 24
Finished Aug 28 08:48:28 PM UTC 24
Peak memory 211652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724065351 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_wakeup_fixed.724065351
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_lowpower_counter.2842760209
Short name T497
Test name
Test status
Simulation time 38985846122 ps
CPU time 38.69 seconds
Started Aug 28 08:44:19 PM UTC 24
Finished Aug 28 08:44:59 PM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842760209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2842760209
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/23.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_poweron_counter.828924562
Short name T491
Test name
Test status
Simulation time 3452713769 ps
CPU time 14.87 seconds
Started Aug 28 08:44:18 PM UTC 24
Finished Aug 28 08:44:34 PM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828924562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.828924562
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/23.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_smoke.456553050
Short name T487
Test name
Test status
Simulation time 6084695359 ps
CPU time 24.23 seconds
Started Aug 28 08:43:42 PM UTC 24
Finished Aug 28 08:44:08 PM UTC 24
Peak memory 211224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456553050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.456553050
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/23.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all.1952184514
Short name T505
Test name
Test status
Simulation time 186608634139 ps
CPU time 118.07 seconds
Started Aug 28 08:44:35 PM UTC 24
Finished Aug 28 08:46:35 PM UTC 24
Peak memory 211612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952184514 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.1952184514
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/23.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_alert_test.1634876905
Short name T503
Test name
Test status
Simulation time 496004827 ps
CPU time 2.2 seconds
Started Aug 28 08:46:17 PM UTC 24
Finished Aug 28 08:46:21 PM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634876905 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.1634876905
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/24.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_clock_gating.1528822482
Short name T330
Test name
Test status
Simulation time 507734031926 ps
CPU time 343.33 seconds
Started Aug 28 08:45:02 PM UTC 24
Finished Aug 28 08:50:49 PM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528822482 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gating.1528822482
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/24.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_both.3978282594
Short name T339
Test name
Test status
Simulation time 169258255561 ps
CPU time 163.39 seconds
Started Aug 28 08:45:04 PM UTC 24
Finished Aug 28 08:47:50 PM UTC 24
Peak memory 211672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978282594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3978282594
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/24.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_interrupt.26170403
Short name T349
Test name
Test status
Simulation time 329536439023 ps
CPU time 190.39 seconds
Started Aug 28 08:44:50 PM UTC 24
Finished Aug 28 08:48:03 PM UTC 24
Peak memory 211528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26170403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_
SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.26170403
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/24.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_interrupt_fixed.4013831518
Short name T536
Test name
Test status
Simulation time 495827298636 ps
CPU time 446.91 seconds
Started Aug 28 08:44:55 PM UTC 24
Finished Aug 28 08:52:27 PM UTC 24
Peak memory 211796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013831518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt_fixed.4013831518
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_polled.765314101
Short name T103
Test name
Test status
Simulation time 329838646796 ps
CPU time 327.26 seconds
Started Aug 28 08:44:38 PM UTC 24
Finished Aug 28 08:50:10 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765314101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.765314101
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/24.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_polled_fixed.1100097608
Short name T510
Test name
Test status
Simulation time 166994031109 ps
CPU time 162.59 seconds
Started Aug 28 08:44:42 PM UTC 24
Finished Aug 28 08:47:28 PM UTC 24
Peak memory 211672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100097608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixed.1100097608
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_wakeup.1014398280
Short name T307
Test name
Test status
Simulation time 585429953467 ps
CPU time 1677.51 seconds
Started Aug 28 08:44:56 PM UTC 24
Finished Aug 28 09:13:10 PM UTC 24
Peak memory 212556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014398280 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_wakeup.1014398280
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/24.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_wakeup_fixed.456376522
Short name T552
Test name
Test status
Simulation time 402766948153 ps
CPU time 598.84 seconds
Started Aug 28 08:45:00 PM UTC 24
Finished Aug 28 08:55:05 PM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456376522 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_wakeup_fixed.456376522
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_fsm_reset.1835770054
Short name T563
Test name
Test status
Simulation time 86364714888 ps
CPU time 686.79 seconds
Started Aug 28 08:45:50 PM UTC 24
Finished Aug 28 08:57:25 PM UTC 24
Peak memory 211692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835770054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1835770054
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/24.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_lowpower_counter.3096538116
Short name T508
Test name
Test status
Simulation time 26016738622 ps
CPU time 101.91 seconds
Started Aug 28 08:45:19 PM UTC 24
Finished Aug 28 08:47:03 PM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096538116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.3096538116
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/24.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_poweron_counter.2924531724
Short name T499
Test name
Test status
Simulation time 3348288551 ps
CPU time 4.39 seconds
Started Aug 28 08:45:13 PM UTC 24
Finished Aug 28 08:45:18 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924531724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2924531724
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/24.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_smoke.2757665162
Short name T498
Test name
Test status
Simulation time 5516728253 ps
CPU time 23.77 seconds
Started Aug 28 08:44:36 PM UTC 24
Finished Aug 28 08:45:01 PM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757665162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2757665162
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/24.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_stress_all.1724081892
Short name T595
Test name
Test status
Simulation time 145473427803 ps
CPU time 948.06 seconds
Started Aug 28 08:46:13 PM UTC 24
Finished Aug 28 09:02:11 PM UTC 24
Peak memory 223388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724081892 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.1724081892
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/24.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3275807485
Short name T33
Test name
Test status
Simulation time 2665709160 ps
CPU time 13.9 seconds
Started Aug 28 08:46:01 PM UTC 24
Finished Aug 28 08:46:16 PM UTC 24
Peak memory 221748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3275807485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 24.adc_ctrl_stress_all_with_rand_reset.3275807485
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_alert_test.2448533459
Short name T512
Test name
Test status
Simulation time 292425121 ps
CPU time 2.14 seconds
Started Aug 28 08:47:34 PM UTC 24
Finished Aug 28 08:47:38 PM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448533459 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2448533459
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/25.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_both.679810780
Short name T299
Test name
Test status
Simulation time 494852830718 ps
CPU time 382.3 seconds
Started Aug 28 08:47:04 PM UTC 24
Finished Aug 28 08:53:31 PM UTC 24
Peak memory 211432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679810780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.679810780
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/25.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_interrupt.1582070041
Short name T556
Test name
Test status
Simulation time 158410896998 ps
CPU time 550.58 seconds
Started Aug 28 08:46:29 PM UTC 24
Finished Aug 28 08:55:45 PM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582070041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.1582070041
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/25.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3392279321
Short name T522
Test name
Test status
Simulation time 327970254853 ps
CPU time 216.84 seconds
Started Aug 28 08:46:36 PM UTC 24
Finished Aug 28 08:50:15 PM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392279321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt_fixed.3392279321
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_polled.1551286739
Short name T309
Test name
Test status
Simulation time 167621317243 ps
CPU time 101.28 seconds
Started Aug 28 08:46:22 PM UTC 24
Finished Aug 28 08:48:05 PM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551286739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1551286739
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/25.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_polled_fixed.1563941697
Short name T98
Test name
Test status
Simulation time 491278889920 ps
CPU time 187.91 seconds
Started Aug 28 08:46:23 PM UTC 24
Finished Aug 28 08:49:33 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563941697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixed.1563941697
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_wakeup_fixed.2616050799
Short name T513
Test name
Test status
Simulation time 199038282884 ps
CPU time 57.94 seconds
Started Aug 28 08:46:46 PM UTC 24
Finished Aug 28 08:47:45 PM UTC 24
Peak memory 211612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616050799 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_wakeup_fixed.2616050799
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_fsm_reset.3646403789
Short name T553
Test name
Test status
Simulation time 65540681166 ps
CPU time 466.11 seconds
Started Aug 28 08:47:23 PM UTC 24
Finished Aug 28 08:55:14 PM UTC 24
Peak memory 211772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646403789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.3646403789
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/25.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_lowpower_counter.2362026995
Short name T515
Test name
Test status
Simulation time 40584434742 ps
CPU time 52.41 seconds
Started Aug 28 08:47:23 PM UTC 24
Finished Aug 28 08:48:17 PM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362026995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.2362026995
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/25.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_poweron_counter.1242835959
Short name T509
Test name
Test status
Simulation time 3089776246 ps
CPU time 4.27 seconds
Started Aug 28 08:47:18 PM UTC 24
Finished Aug 28 08:47:23 PM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242835959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1242835959
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/25.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_smoke.4079158628
Short name T504
Test name
Test status
Simulation time 5678425987 ps
CPU time 7.04 seconds
Started Aug 28 08:46:19 PM UTC 24
Finished Aug 28 08:46:27 PM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079158628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.4079158628
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/25.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_stress_all.2595457513
Short name T295
Test name
Test status
Simulation time 505017047577 ps
CPU time 1507.75 seconds
Started Aug 28 08:47:28 PM UTC 24
Finished Aug 28 09:12:51 PM UTC 24
Peak memory 212488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595457513 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.2595457513
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/25.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_alert_test.2412726840
Short name T520
Test name
Test status
Simulation time 476294954 ps
CPU time 1.41 seconds
Started Aug 28 08:48:58 PM UTC 24
Finished Aug 28 08:49:00 PM UTC 24
Peak memory 209796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412726840 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.2412726840
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/26.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_clock_gating.2508872343
Short name T300
Test name
Test status
Simulation time 358168044142 ps
CPU time 134.19 seconds
Started Aug 28 08:48:05 PM UTC 24
Finished Aug 28 08:50:22 PM UTC 24
Peak memory 211868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508872343 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gating.2508872343
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/26.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_interrupt.2311158163
Short name T97
Test name
Test status
Simulation time 162652046907 ps
CPU time 103.71 seconds
Started Aug 28 08:47:46 PM UTC 24
Finished Aug 28 08:49:31 PM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311158163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2311158163
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/26.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3486281568
Short name T526
Test name
Test status
Simulation time 166208454035 ps
CPU time 162.78 seconds
Started Aug 28 08:47:51 PM UTC 24
Finished Aug 28 08:50:36 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486281568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt_fixed.3486281568
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_polled.1645116423
Short name T605
Test name
Test status
Simulation time 499652327959 ps
CPU time 995.78 seconds
Started Aug 28 08:47:39 PM UTC 24
Finished Aug 28 09:04:25 PM UTC 24
Peak memory 212496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645116423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.1645116423
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/26.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_polled_fixed.1636412898
Short name T534
Test name
Test status
Simulation time 493505058225 ps
CPU time 275.63 seconds
Started Aug 28 08:47:39 PM UTC 24
Finished Aug 28 08:52:18 PM UTC 24
Peak memory 211796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636412898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fixed.1636412898
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_wakeup.279459168
Short name T344
Test name
Test status
Simulation time 362022440988 ps
CPU time 419.79 seconds
Started Aug 28 08:47:52 PM UTC 24
Finished Aug 28 08:54:56 PM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279459168 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_wakeup.279459168
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/26.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3079055945
Short name T562
Test name
Test status
Simulation time 598318308049 ps
CPU time 543.24 seconds
Started Aug 28 08:48:04 PM UTC 24
Finished Aug 28 08:57:13 PM UTC 24
Peak memory 211676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079055945 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_wakeup_fixed.3079055945
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_fsm_reset.4018339133
Short name T576
Test name
Test status
Simulation time 109925253396 ps
CPU time 656.65 seconds
Started Aug 28 08:48:42 PM UTC 24
Finished Aug 28 08:59:46 PM UTC 24
Peak memory 212024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018339133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.4018339133
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/26.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_lowpower_counter.3734568337
Short name T519
Test name
Test status
Simulation time 25817615896 ps
CPU time 21.63 seconds
Started Aug 28 08:48:29 PM UTC 24
Finished Aug 28 08:48:52 PM UTC 24
Peak memory 211536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734568337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.3734568337
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/26.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_poweron_counter.3415220321
Short name T518
Test name
Test status
Simulation time 4903672128 ps
CPU time 22.23 seconds
Started Aug 28 08:48:18 PM UTC 24
Finished Aug 28 08:48:42 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415220321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.3415220321
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/26.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_smoke.1816657918
Short name T514
Test name
Test status
Simulation time 5875912126 ps
CPU time 13.17 seconds
Started Aug 28 08:47:37 PM UTC 24
Finished Aug 28 08:47:51 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816657918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.1816657918
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/26.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.3117182804
Short name T71
Test name
Test status
Simulation time 7552150951 ps
CPU time 22.63 seconds
Started Aug 28 08:48:42 PM UTC 24
Finished Aug 28 08:49:06 PM UTC 24
Peak memory 221732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3117182804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 26.adc_ctrl_stress_all_with_rand_reset.3117182804
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_alert_test.470338563
Short name T524
Test name
Test status
Simulation time 351515966 ps
CPU time 1.18 seconds
Started Aug 28 08:50:22 PM UTC 24
Finished Aug 28 08:50:24 PM UTC 24
Peak memory 210340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470338563 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.470338563
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/27.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_both.4007289418
Short name T278
Test name
Test status
Simulation time 496459154836 ps
CPU time 1333.11 seconds
Started Aug 28 08:49:34 PM UTC 24
Finished Aug 28 09:12:00 PM UTC 24
Peak memory 212520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007289418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.4007289418
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/27.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_interrupt.1252154191
Short name T606
Test name
Test status
Simulation time 332472365300 ps
CPU time 909.87 seconds
Started Aug 28 08:49:07 PM UTC 24
Finished Aug 28 09:04:26 PM UTC 24
Peak memory 211564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252154191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.1252154191
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/27.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_interrupt_fixed.4023010039
Short name T546
Test name
Test status
Simulation time 172159949696 ps
CPU time 257.54 seconds
Started Aug 28 08:49:22 PM UTC 24
Finished Aug 28 08:53:43 PM UTC 24
Peak memory 211540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023010039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt_fixed.4023010039
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_polled.2276515974
Short name T613
Test name
Test status
Simulation time 323572191850 ps
CPU time 958.42 seconds
Started Aug 28 08:49:01 PM UTC 24
Finished Aug 28 09:05:09 PM UTC 24
Peak memory 212760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276515974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.2276515974
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/27.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_polled_fixed.715798866
Short name T530
Test name
Test status
Simulation time 166986198966 ps
CPU time 176.16 seconds
Started Aug 28 08:49:05 PM UTC 24
Finished Aug 28 08:52:04 PM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715798866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixed.715798866
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_wakeup.880216890
Short name T198
Test name
Test status
Simulation time 342760225666 ps
CPU time 297.27 seconds
Started Aug 28 08:49:27 PM UTC 24
Finished Aug 28 08:54:28 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880216890 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_wakeup.880216890
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/27.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_wakeup_fixed.3105441474
Short name T704
Test name
Test status
Simulation time 617355694762 ps
CPU time 1753.52 seconds
Started Aug 28 08:49:32 PM UTC 24
Finished Aug 28 09:19:04 PM UTC 24
Peak memory 212672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105441474 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_wakeup_fixed.3105441474
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_lowpower_counter.804094695
Short name T102
Test name
Test status
Simulation time 28513667702 ps
CPU time 10.09 seconds
Started Aug 28 08:49:41 PM UTC 24
Finished Aug 28 08:49:53 PM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804094695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.804094695
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/27.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_poweron_counter.2599867452
Short name T101
Test name
Test status
Simulation time 2800615894 ps
CPU time 3.58 seconds
Started Aug 28 08:49:36 PM UTC 24
Finished Aug 28 08:49:41 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599867452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2599867452
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/27.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_smoke.64780308
Short name T96
Test name
Test status
Simulation time 6001360828 ps
CPU time 23.92 seconds
Started Aug 28 08:49:01 PM UTC 24
Finished Aug 28 08:49:26 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64780308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_
SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.64780308
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/27.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_stress_all.464830382
Short name T327
Test name
Test status
Simulation time 353102410641 ps
CPU time 1146.04 seconds
Started Aug 28 08:50:17 PM UTC 24
Finished Aug 28 09:09:34 PM UTC 24
Peak memory 212620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464830382 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all.464830382
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/27.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_alert_test.1904368953
Short name T533
Test name
Test status
Simulation time 504244683 ps
CPU time 2.76 seconds
Started Aug 28 08:52:11 PM UTC 24
Finished Aug 28 08:52:15 PM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904368953 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.1904368953
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/28.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_clock_gating.1218992251
Short name T311
Test name
Test status
Simulation time 495296140024 ps
CPU time 504.16 seconds
Started Aug 28 08:50:52 PM UTC 24
Finished Aug 28 08:59:22 PM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218992251 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gating.1218992251
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/28.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_both.3827926880
Short name T578
Test name
Test status
Simulation time 341708152866 ps
CPU time 542.44 seconds
Started Aug 28 08:51:05 PM UTC 24
Finished Aug 28 09:00:14 PM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827926880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3827926880
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/28.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_interrupt.135901491
Short name T361
Test name
Test status
Simulation time 326654773753 ps
CPU time 1095.88 seconds
Started Aug 28 08:50:31 PM UTC 24
Finished Aug 28 09:08:58 PM UTC 24
Peak memory 212564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135901491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.135901491
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/28.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_interrupt_fixed.723367664
Short name T642
Test name
Test status
Simulation time 486535850875 ps
CPU time 1121.61 seconds
Started Aug 28 08:50:36 PM UTC 24
Finished Aug 28 09:09:27 PM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723367664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt_fixed.723367664
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_polled.2501578287
Short name T353
Test name
Test status
Simulation time 492494684475 ps
CPU time 520.2 seconds
Started Aug 28 08:50:23 PM UTC 24
Finished Aug 28 08:59:09 PM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501578287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.2501578287
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/28.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_polled_fixed.1285464683
Short name T664
Test name
Test status
Simulation time 494627165140 ps
CPU time 1309.15 seconds
Started Aug 28 08:50:25 PM UTC 24
Finished Aug 28 09:12:26 PM UTC 24
Peak memory 212744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285464683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixed.1285464683
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_wakeup.4160752001
Short name T212
Test name
Test status
Simulation time 547628675424 ps
CPU time 417.2 seconds
Started Aug 28 08:50:37 PM UTC 24
Finished Aug 28 08:57:39 PM UTC 24
Peak memory 211676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160752001 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_wakeup.4160752001
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/28.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_wakeup_fixed.961260978
Short name T559
Test name
Test status
Simulation time 197875446485 ps
CPU time 331.8 seconds
Started Aug 28 08:50:50 PM UTC 24
Finished Aug 28 08:56:26 PM UTC 24
Peak memory 211672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961260978 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_wakeup_fixed.961260978
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_fsm_reset.2660778625
Short name T385
Test name
Test status
Simulation time 121412670733 ps
CPU time 497.92 seconds
Started Aug 28 08:51:41 PM UTC 24
Finished Aug 28 09:00:03 PM UTC 24
Peak memory 211760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660778625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2660778625
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/28.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_lowpower_counter.3742297764
Short name T531
Test name
Test status
Simulation time 33632176173 ps
CPU time 36.26 seconds
Started Aug 28 08:51:35 PM UTC 24
Finished Aug 28 08:52:12 PM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742297764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3742297764
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/28.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_poweron_counter.4222366760
Short name T528
Test name
Test status
Simulation time 4598823684 ps
CPU time 3.14 seconds
Started Aug 28 08:51:29 PM UTC 24
Finished Aug 28 08:51:34 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222366760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.4222366760
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/28.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_smoke.2486534312
Short name T525
Test name
Test status
Simulation time 5896064074 ps
CPU time 6.31 seconds
Started Aug 28 08:50:23 PM UTC 24
Finished Aug 28 08:50:30 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486534312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2486534312
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/28.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_stress_all.447612977
Short name T611
Test name
Test status
Simulation time 203345128451 ps
CPU time 759.85 seconds
Started Aug 28 08:52:08 PM UTC 24
Finished Aug 28 09:04:56 PM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447612977 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.447612977
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/28.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.4214080678
Short name T532
Test name
Test status
Simulation time 3628719414 ps
CPU time 8.23 seconds
Started Aug 28 08:52:05 PM UTC 24
Finished Aug 28 08:52:14 PM UTC 24
Peak memory 221672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=4214080678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 28.adc_ctrl_stress_all_with_rand_reset.4214080678
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_alert_test.3097801037
Short name T541
Test name
Test status
Simulation time 373249821 ps
CPU time 2.41 seconds
Started Aug 28 08:53:19 PM UTC 24
Finished Aug 28 08:53:22 PM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097801037 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.3097801037
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/29.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_both.4035789287
Short name T346
Test name
Test status
Simulation time 177194029336 ps
CPU time 685.91 seconds
Started Aug 28 08:52:59 PM UTC 24
Finished Aug 28 09:04:33 PM UTC 24
Peak memory 211556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035789287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.4035789287
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/29.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_interrupt_fixed.3572010507
Short name T649
Test name
Test status
Simulation time 331483172409 ps
CPU time 1057.26 seconds
Started Aug 28 08:52:18 PM UTC 24
Finished Aug 28 09:10:06 PM UTC 24
Peak memory 211672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572010507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt_fixed.3572010507
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_polled.3673694511
Short name T694
Test name
Test status
Simulation time 497299926812 ps
CPU time 1520.98 seconds
Started Aug 28 08:52:13 PM UTC 24
Finished Aug 28 09:17:49 PM UTC 24
Peak memory 212496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673694511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3673694511
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/29.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_polled_fixed.1589981268
Short name T582
Test name
Test status
Simulation time 166999181772 ps
CPU time 526.85 seconds
Started Aug 28 08:52:15 PM UTC 24
Finished Aug 28 09:01:08 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589981268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixed.1589981268
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_wakeup.3985660953
Short name T335
Test name
Test status
Simulation time 587272046125 ps
CPU time 449.29 seconds
Started Aug 28 08:52:21 PM UTC 24
Finished Aug 28 08:59:56 PM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985660953 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_wakeup.3985660953
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/29.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_wakeup_fixed.603325139
Short name T571
Test name
Test status
Simulation time 626099058240 ps
CPU time 375.34 seconds
Started Aug 28 08:52:27 PM UTC 24
Finished Aug 28 08:58:47 PM UTC 24
Peak memory 211388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603325139 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_wakeup_fixed.603325139
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_fsm_reset.1446973414
Short name T597
Test name
Test status
Simulation time 126021478886 ps
CPU time 540.27 seconds
Started Aug 28 08:53:14 PM UTC 24
Finished Aug 28 09:02:19 PM UTC 24
Peak memory 211836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446973414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.1446973414
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/29.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_lowpower_counter.401781502
Short name T547
Test name
Test status
Simulation time 44181099748 ps
CPU time 35.85 seconds
Started Aug 28 08:53:10 PM UTC 24
Finished Aug 28 08:53:47 PM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401781502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.401781502
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/29.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_poweron_counter.2528908991
Short name T540
Test name
Test status
Simulation time 5388137225 ps
CPU time 3.34 seconds
Started Aug 28 08:53:10 PM UTC 24
Finished Aug 28 08:53:14 PM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528908991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.2528908991
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/29.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_smoke.4218937439
Short name T535
Test name
Test status
Simulation time 6036514636 ps
CPU time 7.23 seconds
Started Aug 28 08:52:12 PM UTC 24
Finished Aug 28 08:52:20 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218937439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.4218937439
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/29.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all.3830243886
Short name T202
Test name
Test status
Simulation time 333938621783 ps
CPU time 379.91 seconds
Started Aug 28 08:53:17 PM UTC 24
Finished Aug 28 08:59:41 PM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830243886 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.3830243886
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/29.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_alert_test.2357633132
Short name T37
Test name
Test status
Simulation time 562857720 ps
CPU time 1.29 seconds
Started Aug 28 08:13:43 PM UTC 24
Finished Aug 28 08:13:46 PM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357633132 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2357633132
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/3.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_clock_gating.1226840675
Short name T174
Test name
Test status
Simulation time 342112198007 ps
CPU time 571.49 seconds
Started Aug 28 08:13:29 PM UTC 24
Finished Aug 28 08:23:06 PM UTC 24
Peak memory 211616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226840675 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gating.1226840675
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/3.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt.3533550890
Short name T16
Test name
Test status
Simulation time 162066207695 ps
CPU time 71.15 seconds
Started Aug 28 08:13:15 PM UTC 24
Finished Aug 28 08:14:28 PM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533550890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.3533550890
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/3.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3885392010
Short name T428
Test name
Test status
Simulation time 484953597516 ps
CPU time 897.9 seconds
Started Aug 28 08:13:15 PM UTC 24
Finished Aug 28 08:28:24 PM UTC 24
Peak memory 212812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885392010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt_fixed.3885392010
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled.32846371
Short name T163
Test name
Test status
Simulation time 160366167416 ps
CPU time 217.44 seconds
Started Aug 28 08:13:13 PM UTC 24
Finished Aug 28 08:16:54 PM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32846371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_
SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.32846371
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/3.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled_fixed.115350115
Short name T81
Test name
Test status
Simulation time 165896667416 ps
CPU time 196.86 seconds
Started Aug 28 08:13:13 PM UTC 24
Finished Aug 28 08:16:33 PM UTC 24
Peak memory 211464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115350115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed.115350115
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup.2568829755
Short name T206
Test name
Test status
Simulation time 167414093202 ps
CPU time 426.79 seconds
Started Aug 28 08:13:16 PM UTC 24
Finished Aug 28 08:20:28 PM UTC 24
Peak memory 211748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568829755 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_wakeup.2568829755
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/3.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup_fixed.721469657
Short name T110
Test name
Test status
Simulation time 580232433263 ps
CPU time 1777.56 seconds
Started Aug 28 08:13:17 PM UTC 24
Finished Aug 28 08:43:12 PM UTC 24
Peak memory 212536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721469657 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_wakeup_fixed.721469657
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.2311261589
Short name T61
Test name
Test status
Simulation time 77815125793 ps
CPU time 717.86 seconds
Started Aug 28 08:13:40 PM UTC 24
Finished Aug 28 08:25:47 PM UTC 24
Peak memory 211756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311261589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.2311261589
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/3.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_lowpower_counter.1612282996
Short name T42
Test name
Test status
Simulation time 40564865273 ps
CPU time 31.35 seconds
Started Aug 28 08:13:37 PM UTC 24
Finished Aug 28 08:14:10 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612282996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.1612282996
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/3.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_poweron_counter.730637805
Short name T27
Test name
Test status
Simulation time 5185314483 ps
CPU time 4.8 seconds
Started Aug 28 08:13:35 PM UTC 24
Finished Aug 28 08:13:41 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730637805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.730637805
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/3.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_sec_cm.3678839916
Short name T43
Test name
Test status
Simulation time 8145812147 ps
CPU time 32.63 seconds
Started Aug 28 08:13:41 PM UTC 24
Finished Aug 28 08:14:16 PM UTC 24
Peak memory 243552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678839916 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3678839916
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/3.adc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_smoke.2650649902
Short name T26
Test name
Test status
Simulation time 6052944224 ps
CPU time 2.73 seconds
Started Aug 28 08:13:12 PM UTC 24
Finished Aug 28 08:13:16 PM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650649902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.2650649902
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/3.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all.2275135904
Short name T244
Test name
Test status
Simulation time 328071291740 ps
CPU time 1500.58 seconds
Started Aug 28 08:13:41 PM UTC 24
Finished Aug 28 08:38:57 PM UTC 24
Peak memory 212768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275135904 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.2275135904
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1229258336
Short name T40
Test name
Test status
Simulation time 2534359918 ps
CPU time 19.65 seconds
Started Aug 28 08:13:41 PM UTC 24
Finished Aug 28 08:14:02 PM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1229258336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.adc_ctrl_stress_all_with_rand_reset.1229258336
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_alert_test.3469467217
Short name T550
Test name
Test status
Simulation time 353617874 ps
CPU time 2.33 seconds
Started Aug 28 08:54:29 PM UTC 24
Finished Aug 28 08:54:32 PM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469467217 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.3469467217
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/30.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_clock_gating.2052119303
Short name T356
Test name
Test status
Simulation time 330652177766 ps
CPU time 954.7 seconds
Started Aug 28 08:53:43 PM UTC 24
Finished Aug 28 09:09:48 PM UTC 24
Peak memory 211808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052119303 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gating.2052119303
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/30.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_both.258390795
Short name T667
Test name
Test status
Simulation time 356155768538 ps
CPU time 1123.97 seconds
Started Aug 28 08:53:47 PM UTC 24
Finished Aug 28 09:12:42 PM UTC 24
Peak memory 211804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258390795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.258390795
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/30.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_interrupt.1973937281
Short name T178
Test name
Test status
Simulation time 322034527442 ps
CPU time 156.13 seconds
Started Aug 28 08:53:34 PM UTC 24
Finished Aug 28 08:56:13 PM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973937281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.1973937281
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/30.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_interrupt_fixed.1508249921
Short name T549
Test name
Test status
Simulation time 161154762559 ps
CPU time 52.18 seconds
Started Aug 28 08:53:34 PM UTC 24
Finished Aug 28 08:54:28 PM UTC 24
Peak memory 211592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508249921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt_fixed.1508249921
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_polled.1870578689
Short name T719
Test name
Test status
Simulation time 491397912669 ps
CPU time 1610.06 seconds
Started Aug 28 08:53:31 PM UTC 24
Finished Aug 28 09:20:37 PM UTC 24
Peak memory 212496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870578689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.1870578689
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/30.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_polled_fixed.1426881066
Short name T573
Test name
Test status
Simulation time 164909674153 ps
CPU time 329.62 seconds
Started Aug 28 08:53:32 PM UTC 24
Finished Aug 28 08:59:06 PM UTC 24
Peak memory 211536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426881066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixed.1426881066
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_wakeup.3131718605
Short name T745
Test name
Test status
Simulation time 602453221277 ps
CPU time 1767.1 seconds
Started Aug 28 08:53:37 PM UTC 24
Finished Aug 28 09:23:21 PM UTC 24
Peak memory 212544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131718605 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_wakeup.3131718605
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/30.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_wakeup_fixed.494743902
Short name T724
Test name
Test status
Simulation time 413757939225 ps
CPU time 1639.3 seconds
Started Aug 28 08:53:39 PM UTC 24
Finished Aug 28 09:21:14 PM UTC 24
Peak memory 212480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494743902 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_wakeup_fixed.494743902
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_fsm_reset.1991390764
Short name T376
Test name
Test status
Simulation time 120853103020 ps
CPU time 992 seconds
Started Aug 28 08:54:19 PM UTC 24
Finished Aug 28 09:11:02 PM UTC 24
Peak memory 212028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991390764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.1991390764
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/30.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_lowpower_counter.2765204959
Short name T554
Test name
Test status
Simulation time 36027171386 ps
CPU time 70.47 seconds
Started Aug 28 08:54:15 PM UTC 24
Finished Aug 28 08:55:27 PM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765204959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2765204959
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/30.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_poweron_counter.645439756
Short name T548
Test name
Test status
Simulation time 3956901921 ps
CPU time 9.28 seconds
Started Aug 28 08:54:04 PM UTC 24
Finished Aug 28 08:54:14 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645439756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.645439756
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/30.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_smoke.3363318366
Short name T542
Test name
Test status
Simulation time 5506804090 ps
CPU time 6.06 seconds
Started Aug 28 08:53:23 PM UTC 24
Finished Aug 28 08:53:30 PM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363318366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.3363318366
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/30.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all.229239445
Short name T574
Test name
Test status
Simulation time 324689424711 ps
CPU time 295.17 seconds
Started Aug 28 08:54:29 PM UTC 24
Finished Aug 28 08:59:28 PM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229239445 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all.229239445
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/30.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2928908379
Short name T34
Test name
Test status
Simulation time 1526550092 ps
CPU time 4.67 seconds
Started Aug 28 08:54:25 PM UTC 24
Finished Aug 28 08:54:31 PM UTC 24
Peak memory 211272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2928908379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 30.adc_ctrl_stress_all_with_rand_reset.2928908379
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_alert_test.1371719751
Short name T558
Test name
Test status
Simulation time 317733475 ps
CPU time 2.1 seconds
Started Aug 28 08:56:15 PM UTC 24
Finished Aug 28 08:56:18 PM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371719751 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.1371719751
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/31.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_clock_gating.2692267511
Short name T312
Test name
Test status
Simulation time 557626578789 ps
CPU time 1501.49 seconds
Started Aug 28 08:55:28 PM UTC 24
Finished Aug 28 09:20:43 PM UTC 24
Peak memory 212612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692267511 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gating.2692267511
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/31.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_interrupt.3142884097
Short name T601
Test name
Test status
Simulation time 167780963158 ps
CPU time 476.8 seconds
Started Aug 28 08:54:41 PM UTC 24
Finished Aug 28 09:02:43 PM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142884097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.3142884097
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/31.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_interrupt_fixed.1462312284
Short name T590
Test name
Test status
Simulation time 324360830867 ps
CPU time 410.17 seconds
Started Aug 28 08:54:57 PM UTC 24
Finished Aug 28 09:01:51 PM UTC 24
Peak memory 211596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462312284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt_fixed.1462312284
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_polled.249698177
Short name T586
Test name
Test status
Simulation time 164226280573 ps
CPU time 422.95 seconds
Started Aug 28 08:54:33 PM UTC 24
Finished Aug 28 09:01:41 PM UTC 24
Peak memory 211740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249698177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.249698177
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/31.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_polled_fixed.2193939361
Short name T623
Test name
Test status
Simulation time 485277952680 ps
CPU time 688.22 seconds
Started Aug 28 08:54:40 PM UTC 24
Finished Aug 28 09:06:16 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193939361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixed.2193939361
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_wakeup.1066801709
Short name T93
Test name
Test status
Simulation time 397233302011 ps
CPU time 1216.46 seconds
Started Aug 28 08:55:06 PM UTC 24
Finished Aug 28 09:15:34 PM UTC 24
Peak memory 212568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066801709 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_wakeup.1066801709
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/31.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_wakeup_fixed.700424905
Short name T561
Test name
Test status
Simulation time 189023770917 ps
CPU time 92.71 seconds
Started Aug 28 08:55:15 PM UTC 24
Finished Aug 28 08:56:50 PM UTC 24
Peak memory 211672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700424905 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_wakeup_fixed.700424905
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_fsm_reset.827940420
Short name T647
Test name
Test status
Simulation time 105447385092 ps
CPU time 825.71 seconds
Started Aug 28 08:55:59 PM UTC 24
Finished Aug 28 09:09:53 PM UTC 24
Peak memory 211824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827940420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.827940420
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/31.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_lowpower_counter.3153373393
Short name T570
Test name
Test status
Simulation time 44134120087 ps
CPU time 177.44 seconds
Started Aug 28 08:55:46 PM UTC 24
Finished Aug 28 08:58:46 PM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153373393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.3153373393
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/31.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_poweron_counter.2008200120
Short name T557
Test name
Test status
Simulation time 5213974728 ps
CPU time 11.74 seconds
Started Aug 28 08:55:46 PM UTC 24
Finished Aug 28 08:55:59 PM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008200120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.2008200120
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/31.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_smoke.255536431
Short name T551
Test name
Test status
Simulation time 5969564426 ps
CPU time 7.08 seconds
Started Aug 28 08:54:31 PM UTC 24
Finished Aug 28 08:54:39 PM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255536431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.255536431
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/31.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_stress_all.1046146957
Short name T343
Test name
Test status
Simulation time 512384345942 ps
CPU time 474 seconds
Started Aug 28 08:56:13 PM UTC 24
Finished Aug 28 09:04:12 PM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046146957 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.1046146957
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/31.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_alert_test.1309599925
Short name T569
Test name
Test status
Simulation time 346314983 ps
CPU time 1.21 seconds
Started Aug 28 08:58:43 PM UTC 24
Finished Aug 28 08:58:45 PM UTC 24
Peak memory 210336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309599925 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1309599925
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/32.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2971810164
Short name T592
Test name
Test status
Simulation time 163746639886 ps
CPU time 309.51 seconds
Started Aug 28 08:56:51 PM UTC 24
Finished Aug 28 09:02:04 PM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971810164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt_fixed.2971810164
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_polled.1402515763
Short name T365
Test name
Test status
Simulation time 165870701047 ps
CPU time 438.49 seconds
Started Aug 28 08:56:26 PM UTC 24
Finished Aug 28 09:03:50 PM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402515763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.1402515763
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/32.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_polled_fixed.1578732712
Short name T615
Test name
Test status
Simulation time 161049683758 ps
CPU time 517.02 seconds
Started Aug 28 08:56:32 PM UTC 24
Finished Aug 28 09:05:15 PM UTC 24
Peak memory 211540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578732712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixed.1578732712
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_wakeup.1897748416
Short name T692
Test name
Test status
Simulation time 374846193771 ps
CPU time 1203.16 seconds
Started Aug 28 08:57:13 PM UTC 24
Finished Aug 28 09:17:28 PM UTC 24
Peak memory 212548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897748416 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_wakeup.1897748416
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/32.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3230680336
Short name T600
Test name
Test status
Simulation time 195119418892 ps
CPU time 321.21 seconds
Started Aug 28 08:57:14 PM UTC 24
Finished Aug 28 09:02:39 PM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230680336 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_wakeup_fixed.3230680336
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_fsm_reset.3920992315
Short name T628
Test name
Test status
Simulation time 102397086715 ps
CPU time 551.5 seconds
Started Aug 28 08:58:02 PM UTC 24
Finished Aug 28 09:07:19 PM UTC 24
Peak memory 212080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920992315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.3920992315
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/32.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_lowpower_counter.3766069256
Short name T566
Test name
Test status
Simulation time 43923401716 ps
CPU time 12.88 seconds
Started Aug 28 08:57:47 PM UTC 24
Finished Aug 28 08:58:01 PM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766069256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.3766069256
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/32.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_poweron_counter.748267460
Short name T565
Test name
Test status
Simulation time 5295037078 ps
CPU time 6.24 seconds
Started Aug 28 08:57:39 PM UTC 24
Finished Aug 28 08:57:46 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748267460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.748267460
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/32.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_smoke.1942072599
Short name T560
Test name
Test status
Simulation time 5798412199 ps
CPU time 23.36 seconds
Started Aug 28 08:56:19 PM UTC 24
Finished Aug 28 08:56:44 PM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942072599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.1942072599
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/32.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_stress_all.3029895650
Short name T320
Test name
Test status
Simulation time 1848138435016 ps
CPU time 5680.15 seconds
Started Aug 28 08:58:29 PM UTC 24
Finished Aug 28 10:34:06 PM UTC 24
Peak memory 223104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029895650 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all.3029895650
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/32.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.2435509095
Short name T568
Test name
Test status
Simulation time 3055319923 ps
CPU time 13.29 seconds
Started Aug 28 08:58:13 PM UTC 24
Finished Aug 28 08:58:28 PM UTC 24
Peak memory 211544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2435509095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 32.adc_ctrl_stress_all_with_rand_reset.2435509095
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_alert_test.3934200576
Short name T577
Test name
Test status
Simulation time 535449358 ps
CPU time 1.31 seconds
Started Aug 28 09:00:07 PM UTC 24
Finished Aug 28 09:00:09 PM UTC 24
Peak memory 209796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934200576 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.3934200576
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/33.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_both.3034124204
Short name T583
Test name
Test status
Simulation time 171838196143 ps
CPU time 110.64 seconds
Started Aug 28 08:59:29 PM UTC 24
Finished Aug 28 09:01:22 PM UTC 24
Peak memory 211744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034124204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.3034124204
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/33.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_interrupt.640100620
Short name T653
Test name
Test status
Simulation time 489621392337 ps
CPU time 698.59 seconds
Started Aug 28 08:58:54 PM UTC 24
Finished Aug 28 09:10:40 PM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640100620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.640100620
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/33.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_interrupt_fixed.904038588
Short name T594
Test name
Test status
Simulation time 163092523341 ps
CPU time 181.12 seconds
Started Aug 28 08:59:04 PM UTC 24
Finished Aug 28 09:02:08 PM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904038588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt_fixed.904038588
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_polled.3086521181
Short name T666
Test name
Test status
Simulation time 329739105793 ps
CPU time 819.53 seconds
Started Aug 28 08:58:47 PM UTC 24
Finished Aug 28 09:12:35 PM UTC 24
Peak memory 211748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086521181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.3086521181
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/33.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_polled_fixed.606659401
Short name T91
Test name
Test status
Simulation time 327701765198 ps
CPU time 977.5 seconds
Started Aug 28 08:58:48 PM UTC 24
Finished Aug 28 09:15:15 PM UTC 24
Peak memory 211676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606659401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixed.606659401
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_wakeup.1053205142
Short name T179
Test name
Test status
Simulation time 346601615282 ps
CPU time 165.38 seconds
Started Aug 28 08:59:07 PM UTC 24
Finished Aug 28 09:01:55 PM UTC 24
Peak memory 211676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053205142 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_wakeup.1053205142
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/33.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_wakeup_fixed.778389917
Short name T584
Test name
Test status
Simulation time 392321808144 ps
CPU time 139.06 seconds
Started Aug 28 08:59:10 PM UTC 24
Finished Aug 28 09:01:31 PM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778389917 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_wakeup_fixed.778389917
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_fsm_reset.3412864620
Short name T679
Test name
Test status
Simulation time 113651479812 ps
CPU time 838.95 seconds
Started Aug 28 08:59:47 PM UTC 24
Finished Aug 28 09:13:56 PM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412864620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.3412864620
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/33.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_lowpower_counter.547411773
Short name T581
Test name
Test status
Simulation time 24949828786 ps
CPU time 62.08 seconds
Started Aug 28 08:59:46 PM UTC 24
Finished Aug 28 09:00:50 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547411773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.547411773
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/33.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_poweron_counter.1563440880
Short name T575
Test name
Test status
Simulation time 5050569065 ps
CPU time 2.81 seconds
Started Aug 28 08:59:41 PM UTC 24
Finished Aug 28 08:59:45 PM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563440880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1563440880
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/33.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_smoke.2150952365
Short name T572
Test name
Test status
Simulation time 5929504796 ps
CPU time 6.39 seconds
Started Aug 28 08:58:46 PM UTC 24
Finished Aug 28 08:58:53 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150952365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.2150952365
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/33.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_stress_all.3371556939
Short name T717
Test name
Test status
Simulation time 287949729153 ps
CPU time 1206.37 seconds
Started Aug 28 08:59:57 PM UTC 24
Finished Aug 28 09:20:15 PM UTC 24
Peak memory 212760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371556939 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.3371556939
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/33.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.3915137127
Short name T579
Test name
Test status
Simulation time 68976282694 ps
CPU time 28.64 seconds
Started Aug 28 08:59:49 PM UTC 24
Finished Aug 28 09:00:19 PM UTC 24
Peak memory 222004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3915137127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 33.adc_ctrl_stress_all_with_rand_reset.3915137127
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_alert_test.1618648043
Short name T588
Test name
Test status
Simulation time 495695716 ps
CPU time 1.96 seconds
Started Aug 28 09:01:42 PM UTC 24
Finished Aug 28 09:01:45 PM UTC 24
Peak memory 210592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618648043 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1618648043
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/34.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_clock_gating.640577370
Short name T318
Test name
Test status
Simulation time 166141035032 ps
CPU time 6.42 seconds
Started Aug 28 09:01:08 PM UTC 24
Finished Aug 28 09:01:16 PM UTC 24
Peak memory 211428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640577370 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gating.640577370
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/34.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_both.2706067044
Short name T315
Test name
Test status
Simulation time 506953777431 ps
CPU time 506.38 seconds
Started Aug 28 09:01:09 PM UTC 24
Finished Aug 28 09:09:41 PM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706067044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.2706067044
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/34.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_interrupt.396097133
Short name T286
Test name
Test status
Simulation time 330272742461 ps
CPU time 64.57 seconds
Started Aug 28 09:00:25 PM UTC 24
Finished Aug 28 09:01:32 PM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396097133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.396097133
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/34.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1564636512
Short name T591
Test name
Test status
Simulation time 169822576952 ps
CPU time 78.14 seconds
Started Aug 28 09:00:32 PM UTC 24
Finished Aug 28 09:01:52 PM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564636512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt_fixed.1564636512
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_polled_fixed.3850655052
Short name T618
Test name
Test status
Simulation time 329390379050 ps
CPU time 301.76 seconds
Started Aug 28 09:00:21 PM UTC 24
Finished Aug 28 09:05:27 PM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850655052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixed.3850655052
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_wakeup.2951070853
Short name T607
Test name
Test status
Simulation time 363538124662 ps
CPU time 227.14 seconds
Started Aug 28 09:00:39 PM UTC 24
Finished Aug 28 09:04:29 PM UTC 24
Peak memory 211544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951070853 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_wakeup.2951070853
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/34.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_wakeup_fixed.1341528381
Short name T598
Test name
Test status
Simulation time 199654151496 ps
CPU time 93.48 seconds
Started Aug 28 09:00:51 PM UTC 24
Finished Aug 28 09:02:26 PM UTC 24
Peak memory 211528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341528381 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_wakeup_fixed.1341528381
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_fsm_reset.3491586532
Short name T678
Test name
Test status
Simulation time 131401409368 ps
CPU time 732.03 seconds
Started Aug 28 09:01:32 PM UTC 24
Finished Aug 28 09:13:52 PM UTC 24
Peak memory 211692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491586532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3491586532
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/34.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_lowpower_counter.2433490846
Short name T589
Test name
Test status
Simulation time 21793128822 ps
CPU time 23.09 seconds
Started Aug 28 09:01:22 PM UTC 24
Finished Aug 28 09:01:47 PM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433490846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.2433490846
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/34.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_poweron_counter.370923387
Short name T585
Test name
Test status
Simulation time 5296727153 ps
CPU time 23.73 seconds
Started Aug 28 09:01:16 PM UTC 24
Finished Aug 28 09:01:41 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370923387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.370923387
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/34.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_smoke.3366951805
Short name T580
Test name
Test status
Simulation time 5824028654 ps
CPU time 25.25 seconds
Started Aug 28 09:00:11 PM UTC 24
Finished Aug 28 09:00:38 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366951805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.3366951805
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/34.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_stress_all.3972336589
Short name T603
Test name
Test status
Simulation time 172224135967 ps
CPU time 131.55 seconds
Started Aug 28 09:01:42 PM UTC 24
Finished Aug 28 09:03:56 PM UTC 24
Peak memory 210816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972336589 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.3972336589
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/34.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.990083807
Short name T587
Test name
Test status
Simulation time 2943546825 ps
CPU time 8.08 seconds
Started Aug 28 09:01:32 PM UTC 24
Finished Aug 28 09:01:42 PM UTC 24
Peak memory 211348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=990083807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
34.adc_ctrl_stress_all_with_rand_reset.990083807
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_alert_test.2920792365
Short name T599
Test name
Test status
Simulation time 442101663 ps
CPU time 2.6 seconds
Started Aug 28 09:02:33 PM UTC 24
Finished Aug 28 09:02:37 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920792365 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2920792365
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/35.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_clock_gating.780483346
Short name T612
Test name
Test status
Simulation time 177321013199 ps
CPU time 177.45 seconds
Started Aug 28 09:02:07 PM UTC 24
Finished Aug 28 09:05:07 PM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780483346 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gating.780483346
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/35.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_both.1777728856
Short name T656
Test name
Test status
Simulation time 161864252759 ps
CPU time 525.57 seconds
Started Aug 28 09:02:08 PM UTC 24
Finished Aug 28 09:10:59 PM UTC 24
Peak memory 211784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777728856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1777728856
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/35.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_interrupt.1043263459
Short name T336
Test name
Test status
Simulation time 167327724837 ps
CPU time 483.88 seconds
Started Aug 28 09:01:52 PM UTC 24
Finished Aug 28 09:10:01 PM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043263459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.1043263459
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/35.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_interrupt_fixed.2880718736
Short name T648
Test name
Test status
Simulation time 330932302040 ps
CPU time 488.08 seconds
Started Aug 28 09:01:53 PM UTC 24
Finished Aug 28 09:10:06 PM UTC 24
Peak memory 211732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880718736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt_fixed.2880718736
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_polled.472345345
Short name T350
Test name
Test status
Simulation time 488848184892 ps
CPU time 186.34 seconds
Started Aug 28 09:01:46 PM UTC 24
Finished Aug 28 09:04:56 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472345345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.472345345
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/35.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_polled_fixed.1960899393
Short name T617
Test name
Test status
Simulation time 321672887417 ps
CPU time 211.61 seconds
Started Aug 28 09:01:48 PM UTC 24
Finished Aug 28 09:05:22 PM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960899393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixed.1960899393
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_wakeup_fixed.1792319222
Short name T633
Test name
Test status
Simulation time 398311455768 ps
CPU time 337.35 seconds
Started Aug 28 09:02:05 PM UTC 24
Finished Aug 28 09:07:46 PM UTC 24
Peak memory 211392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792319222 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_wakeup_fixed.1792319222
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_fsm_reset.1604088027
Short name T677
Test name
Test status
Simulation time 99946625910 ps
CPU time 689.27 seconds
Started Aug 28 09:02:13 PM UTC 24
Finished Aug 28 09:13:49 PM UTC 24
Peak memory 211808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604088027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.1604088027
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/35.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_lowpower_counter.1621780746
Short name T610
Test name
Test status
Simulation time 37705196841 ps
CPU time 159.14 seconds
Started Aug 28 09:02:12 PM UTC 24
Finished Aug 28 09:04:54 PM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621780746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.1621780746
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/35.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_poweron_counter.3961938014
Short name T596
Test name
Test status
Simulation time 4367593974 ps
CPU time 2.57 seconds
Started Aug 28 09:02:09 PM UTC 24
Finished Aug 28 09:02:13 PM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961938014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3961938014
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/35.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_smoke.655771298
Short name T593
Test name
Test status
Simulation time 5659716235 ps
CPU time 22.93 seconds
Started Aug 28 09:01:42 PM UTC 24
Finished Aug 28 09:02:06 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655771298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.655771298
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/35.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2220580253
Short name T215
Test name
Test status
Simulation time 15846476863 ps
CPU time 11.36 seconds
Started Aug 28 09:02:20 PM UTC 24
Finished Aug 28 09:02:33 PM UTC 24
Peak memory 221800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2220580253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 35.adc_ctrl_stress_all_with_rand_reset.2220580253
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_alert_test.3994991012
Short name T608
Test name
Test status
Simulation time 321874469 ps
CPU time 2.22 seconds
Started Aug 28 09:04:30 PM UTC 24
Finished Aug 28 09:04:33 PM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994991012 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.3994991012
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/36.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_clock_gating.1008014085
Short name T652
Test name
Test status
Simulation time 161920912608 ps
CPU time 386.93 seconds
Started Aug 28 09:03:55 PM UTC 24
Finished Aug 28 09:10:27 PM UTC 24
Peak memory 211540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008014085 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gating.1008014085
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/36.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_both.3879389894
Short name T671
Test name
Test status
Simulation time 174888782582 ps
CPU time 542.32 seconds
Started Aug 28 09:03:57 PM UTC 24
Finished Aug 28 09:13:05 PM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879389894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3879389894
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/36.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_interrupt.4172322339
Short name T637
Test name
Test status
Simulation time 322915488127 ps
CPU time 324.25 seconds
Started Aug 28 09:02:45 PM UTC 24
Finished Aug 28 09:08:13 PM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172322339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.4172322339
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/36.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_interrupt_fixed.3536061126
Short name T646
Test name
Test status
Simulation time 166147689616 ps
CPU time 411.22 seconds
Started Aug 28 09:02:47 PM UTC 24
Finished Aug 28 09:09:43 PM UTC 24
Peak memory 211400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536061126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt_fixed.3536061126
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_polled_fixed.2375613144
Short name T624
Test name
Test status
Simulation time 161378775841 ps
CPU time 228.26 seconds
Started Aug 28 09:02:41 PM UTC 24
Finished Aug 28 09:06:32 PM UTC 24
Peak memory 211540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375613144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixed.2375613144
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_wakeup.222077059
Short name T180
Test name
Test status
Simulation time 383718924181 ps
CPU time 173.84 seconds
Started Aug 28 09:02:48 PM UTC 24
Finished Aug 28 09:05:44 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222077059 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_wakeup.222077059
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/36.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_wakeup_fixed.1220488755
Short name T630
Test name
Test status
Simulation time 613443047869 ps
CPU time 221.3 seconds
Started Aug 28 09:03:50 PM UTC 24
Finished Aug 28 09:07:34 PM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220488755 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_wakeup_fixed.1220488755
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_fsm_reset.621733238
Short name T676
Test name
Test status
Simulation time 73091153571 ps
CPU time 561.04 seconds
Started Aug 28 09:04:20 PM UTC 24
Finished Aug 28 09:13:47 PM UTC 24
Peak memory 211760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621733238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.621733238
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/36.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_lowpower_counter.2587611100
Short name T619
Test name
Test status
Simulation time 25639386230 ps
CPU time 78.89 seconds
Started Aug 28 09:04:14 PM UTC 24
Finished Aug 28 09:05:35 PM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587611100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2587611100
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/36.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_poweron_counter.3220348824
Short name T604
Test name
Test status
Simulation time 3997156999 ps
CPU time 3.74 seconds
Started Aug 28 09:04:13 PM UTC 24
Finished Aug 28 09:04:18 PM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220348824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.3220348824
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/36.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_smoke.500484081
Short name T602
Test name
Test status
Simulation time 6207668687 ps
CPU time 7.58 seconds
Started Aug 28 09:02:37 PM UTC 24
Finished Aug 28 09:02:46 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500484081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.500484081
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/36.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_stress_all.3604991901
Short name T46
Test name
Test status
Simulation time 175134840572 ps
CPU time 93.28 seconds
Started Aug 28 09:04:27 PM UTC 24
Finished Aug 28 09:06:02 PM UTC 24
Peak memory 211744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604991901 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.3604991901
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/36.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2116350823
Short name T614
Test name
Test status
Simulation time 5629806996 ps
CPU time 43.71 seconds
Started Aug 28 09:04:26 PM UTC 24
Finished Aug 28 09:05:11 PM UTC 24
Peak memory 222008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2116350823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 36.adc_ctrl_stress_all_with_rand_reset.2116350823
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_alert_test.346176863
Short name T621
Test name
Test status
Simulation time 494986497 ps
CPU time 1.35 seconds
Started Aug 28 09:05:42 PM UTC 24
Finished Aug 28 09:05:44 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346176863 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.346176863
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/37.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_clock_gating.2758939706
Short name T322
Test name
Test status
Simulation time 363834627633 ps
CPU time 209.43 seconds
Started Aug 28 09:05:09 PM UTC 24
Finished Aug 28 09:08:42 PM UTC 24
Peak memory 211808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758939706 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gating.2758939706
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/37.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_both.2994663151
Short name T182
Test name
Test status
Simulation time 335064799113 ps
CPU time 437.56 seconds
Started Aug 28 09:05:11 PM UTC 24
Finished Aug 28 09:12:34 PM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994663151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.2994663151
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/37.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_interrupt.3245478636
Short name T639
Test name
Test status
Simulation time 322353678712 ps
CPU time 224.65 seconds
Started Aug 28 09:04:55 PM UTC 24
Finished Aug 28 09:08:43 PM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245478636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.3245478636
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/37.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_interrupt_fixed.1104526331
Short name T663
Test name
Test status
Simulation time 163732693230 ps
CPU time 439.94 seconds
Started Aug 28 09:04:56 PM UTC 24
Finished Aug 28 09:12:21 PM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104526331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt_fixed.1104526331
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_polled_fixed.4051854904
Short name T766
Test name
Test status
Simulation time 479656100232 ps
CPU time 1244.81 seconds
Started Aug 28 09:04:42 PM UTC 24
Finished Aug 28 09:25:39 PM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051854904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixed.4051854904
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_wakeup.229506453
Short name T687
Test name
Test status
Simulation time 535648583233 ps
CPU time 684.55 seconds
Started Aug 28 09:04:57 PM UTC 24
Finished Aug 28 09:16:29 PM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229506453 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_wakeup.229506453
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/37.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_wakeup_fixed.790990835
Short name T791
Test name
Test status
Simulation time 585164637087 ps
CPU time 1830.55 seconds
Started Aug 28 09:05:07 PM UTC 24
Finished Aug 28 09:35:55 PM UTC 24
Peak memory 212728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790990835 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_wakeup_fixed.790990835
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_fsm_reset.4054518076
Short name T681
Test name
Test status
Simulation time 70969027940 ps
CPU time 535.46 seconds
Started Aug 28 09:05:22 PM UTC 24
Finished Aug 28 09:14:24 PM UTC 24
Peak memory 211692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054518076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.4054518076
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/37.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_lowpower_counter.2764391558
Short name T627
Test name
Test status
Simulation time 30347518258 ps
CPU time 109.95 seconds
Started Aug 28 09:05:20 PM UTC 24
Finished Aug 28 09:07:12 PM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764391558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2764391558
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/37.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_poweron_counter.402544421
Short name T616
Test name
Test status
Simulation time 5649484165 ps
CPU time 3.51 seconds
Started Aug 28 09:05:15 PM UTC 24
Finished Aug 28 09:05:20 PM UTC 24
Peak memory 211224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402544421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.402544421
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/37.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_smoke.1533533246
Short name T609
Test name
Test status
Simulation time 6220173228 ps
CPU time 6.19 seconds
Started Aug 28 09:04:34 PM UTC 24
Finished Aug 28 09:04:41 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533533246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.1533533246
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/37.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_stress_all.4261157198
Short name T277
Test name
Test status
Simulation time 372164115488 ps
CPU time 392.04 seconds
Started Aug 28 09:05:36 PM UTC 24
Finished Aug 28 09:12:13 PM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261157198 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.4261157198
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/37.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.3457360682
Short name T620
Test name
Test status
Simulation time 3977882492 ps
CPU time 11.01 seconds
Started Aug 28 09:05:29 PM UTC 24
Finished Aug 28 09:05:41 PM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3457360682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 37.adc_ctrl_stress_all_with_rand_reset.3457360682
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_alert_test.891209971
Short name T632
Test name
Test status
Simulation time 361632514 ps
CPU time 2.43 seconds
Started Aug 28 09:07:39 PM UTC 24
Finished Aug 28 09:07:42 PM UTC 24
Peak memory 211148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891209971 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.891209971
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/38.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_clock_gating.3694660703
Short name T357
Test name
Test status
Simulation time 330135274869 ps
CPU time 688.94 seconds
Started Aug 28 09:06:59 PM UTC 24
Finished Aug 28 09:18:36 PM UTC 24
Peak memory 211612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694660703 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gating.3694660703
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/38.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_both.3668575632
Short name T741
Test name
Test status
Simulation time 373974296153 ps
CPU time 940.6 seconds
Started Aug 28 09:07:04 PM UTC 24
Finished Aug 28 09:22:55 PM UTC 24
Peak memory 212556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668575632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.3668575632
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/38.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_interrupt.3398123691
Short name T672
Test name
Test status
Simulation time 160666806320 ps
CPU time 413.69 seconds
Started Aug 28 09:06:11 PM UTC 24
Finished Aug 28 09:13:09 PM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398123691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.3398123691
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/38.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_interrupt_fixed.795672289
Short name T641
Test name
Test status
Simulation time 161610013694 ps
CPU time 179.08 seconds
Started Aug 28 09:06:16 PM UTC 24
Finished Aug 28 09:09:18 PM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795672289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt_fixed.795672289
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_polled.647787573
Short name T218
Test name
Test status
Simulation time 327166107041 ps
CPU time 312.63 seconds
Started Aug 28 09:05:45 PM UTC 24
Finished Aug 28 09:11:02 PM UTC 24
Peak memory 210912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647787573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.647787573
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/38.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_polled_fixed.2196932737
Short name T626
Test name
Test status
Simulation time 164804722127 ps
CPU time 58.74 seconds
Started Aug 28 09:06:03 PM UTC 24
Finished Aug 28 09:07:03 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196932737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fixed.2196932737
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_wakeup.1412056361
Short name T324
Test name
Test status
Simulation time 370216264978 ps
CPU time 1336.15 seconds
Started Aug 28 09:06:32 PM UTC 24
Finished Aug 28 09:29:02 PM UTC 24
Peak memory 212544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412056361 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_wakeup.1412056361
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/38.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_wakeup_fixed.1539487751
Short name T709
Test name
Test status
Simulation time 415182773783 ps
CPU time 757.71 seconds
Started Aug 28 09:06:46 PM UTC 24
Finished Aug 28 09:19:32 PM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539487751 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_wakeup_fixed.1539487751
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_fsm_reset.2351137531
Short name T383
Test name
Test status
Simulation time 75555877877 ps
CPU time 569.32 seconds
Started Aug 28 09:07:29 PM UTC 24
Finished Aug 28 09:17:05 PM UTC 24
Peak memory 211692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351137531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.2351137531
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/38.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_lowpower_counter.195338522
Short name T631
Test name
Test status
Simulation time 30497133862 ps
CPU time 15.87 seconds
Started Aug 28 09:07:21 PM UTC 24
Finished Aug 28 09:07:38 PM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195338522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.195338522
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/38.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_poweron_counter.3613977277
Short name T629
Test name
Test status
Simulation time 2785832356 ps
CPU time 12.38 seconds
Started Aug 28 09:07:13 PM UTC 24
Finished Aug 28 09:07:27 PM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613977277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3613977277
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/38.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_smoke.2636616298
Short name T622
Test name
Test status
Simulation time 5618181554 ps
CPU time 23.87 seconds
Started Aug 28 09:05:45 PM UTC 24
Finished Aug 28 09:06:10 PM UTC 24
Peak memory 210656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636616298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.2636616298
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/38.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_stress_all.4099266128
Short name T363
Test name
Test status
Simulation time 333790052829 ps
CPU time 1035.78 seconds
Started Aug 28 09:07:35 PM UTC 24
Finished Aug 28 09:25:01 PM UTC 24
Peak memory 212628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099266128 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.4099266128
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/38.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.704111041
Short name T636
Test name
Test status
Simulation time 7842940907 ps
CPU time 26.46 seconds
Started Aug 28 09:07:30 PM UTC 24
Finished Aug 28 09:07:57 PM UTC 24
Peak memory 222272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=704111041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
38.adc_ctrl_stress_all_with_rand_reset.704111041
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_alert_test.3140990333
Short name T644
Test name
Test status
Simulation time 454094774 ps
CPU time 2.54 seconds
Started Aug 28 09:09:35 PM UTC 24
Finished Aug 28 09:09:38 PM UTC 24
Peak memory 211140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140990333 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3140990333
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/39.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_clock_gating.3349699409
Short name T351
Test name
Test status
Simulation time 483473283198 ps
CPU time 315.72 seconds
Started Aug 28 09:08:25 PM UTC 24
Finished Aug 28 09:13:45 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349699409 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gating.3349699409
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/39.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_interrupt.2137519512
Short name T181
Test name
Test status
Simulation time 323080656948 ps
CPU time 231.39 seconds
Started Aug 28 09:07:54 PM UTC 24
Finished Aug 28 09:11:48 PM UTC 24
Peak memory 211692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137519512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.2137519512
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/39.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_interrupt_fixed.71615946
Short name T786
Test name
Test status
Simulation time 483725918209 ps
CPU time 1547.84 seconds
Started Aug 28 09:07:58 PM UTC 24
Finished Aug 28 09:34:01 PM UTC 24
Peak memory 212876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71615946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt_fixed.71615946
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_polled.3950335216
Short name T682
Test name
Test status
Simulation time 495873907115 ps
CPU time 392.68 seconds
Started Aug 28 09:07:47 PM UTC 24
Finished Aug 28 09:14:24 PM UTC 24
Peak memory 211556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950335216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.3950335216
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/39.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_polled_fixed.3794815212
Short name T760
Test name
Test status
Simulation time 327114237289 ps
CPU time 983.89 seconds
Started Aug 28 09:07:48 PM UTC 24
Finished Aug 28 09:24:22 PM UTC 24
Peak memory 212460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794815212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixed.3794815212
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_wakeup.3055847770
Short name T693
Test name
Test status
Simulation time 374193593357 ps
CPU time 551.57 seconds
Started Aug 28 09:08:14 PM UTC 24
Finished Aug 28 09:17:32 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055847770 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_wakeup.3055847770
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/39.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_wakeup_fixed.1091809576
Short name T789
Test name
Test status
Simulation time 597545426731 ps
CPU time 1615.04 seconds
Started Aug 28 09:08:24 PM UTC 24
Finished Aug 28 09:35:35 PM UTC 24
Peak memory 212504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091809576 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_wakeup_fixed.1091809576
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_fsm_reset.1276503351
Short name T753
Test name
Test status
Simulation time 125507674798 ps
CPU time 876.98 seconds
Started Aug 28 09:09:02 PM UTC 24
Finished Aug 28 09:23:47 PM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276503351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.1276503351
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/39.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_lowpower_counter.3061244449
Short name T643
Test name
Test status
Simulation time 38384854119 ps
CPU time 36.26 seconds
Started Aug 28 09:08:59 PM UTC 24
Finished Aug 28 09:09:36 PM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061244449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.3061244449
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/39.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_poweron_counter.1850957626
Short name T640
Test name
Test status
Simulation time 3810696706 ps
CPU time 16.09 seconds
Started Aug 28 09:08:44 PM UTC 24
Finished Aug 28 09:09:01 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850957626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1850957626
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/39.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_smoke.1520050445
Short name T634
Test name
Test status
Simulation time 6057161716 ps
CPU time 3.85 seconds
Started Aug 28 09:07:43 PM UTC 24
Finished Aug 28 09:07:48 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520050445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.1520050445
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/39.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_stress_all.1923457401
Short name T92
Test name
Test status
Simulation time 493884709364 ps
CPU time 343.69 seconds
Started Aug 28 09:09:28 PM UTC 24
Finished Aug 28 09:15:16 PM UTC 24
Peak memory 211460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923457401 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.1923457401
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/39.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_alert_test.436367704
Short name T391
Test name
Test status
Simulation time 545993420 ps
CPU time 1.39 seconds
Started Aug 28 08:14:23 PM UTC 24
Finished Aug 28 08:14:25 PM UTC 24
Peak memory 210340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436367704 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.436367704
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/4.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_clock_gating.669127021
Short name T221
Test name
Test status
Simulation time 254729339722 ps
CPU time 271.59 seconds
Started Aug 28 08:14:06 PM UTC 24
Finished Aug 28 08:18:41 PM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669127021 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gating.669127021
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/4.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt_fixed.4097283872
Short name T248
Test name
Test status
Simulation time 169758978173 ps
CPU time 282.84 seconds
Started Aug 28 08:13:52 PM UTC 24
Finished Aug 28 08:18:38 PM UTC 24
Peak memory 211604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097283872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt_fixed.4097283872
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled.3912590480
Short name T151
Test name
Test status
Simulation time 166847050319 ps
CPU time 199.13 seconds
Started Aug 28 08:13:45 PM UTC 24
Finished Aug 28 08:17:07 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912590480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.3912590480
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/4.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled_fixed.1518324537
Short name T445
Test name
Test status
Simulation time 492996575998 ps
CPU time 1215.41 seconds
Started Aug 28 08:13:47 PM UTC 24
Finished Aug 28 08:34:14 PM UTC 24
Peak memory 212544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518324537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed.1518324537
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup.1920740934
Short name T144
Test name
Test status
Simulation time 166640469376 ps
CPU time 523.75 seconds
Started Aug 28 08:13:59 PM UTC 24
Finished Aug 28 08:22:49 PM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920740934 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_wakeup.1920740934
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/4.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3097396217
Short name T410
Test name
Test status
Simulation time 209264965482 ps
CPU time 602.76 seconds
Started Aug 28 08:14:03 PM UTC 24
Finished Aug 28 08:24:12 PM UTC 24
Peak memory 211460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097396217 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_wakeup_fixed.3097396217
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_fsm_reset.3807521859
Short name T388
Test name
Test status
Simulation time 105493997914 ps
CPU time 913.62 seconds
Started Aug 28 08:14:12 PM UTC 24
Finished Aug 28 08:29:35 PM UTC 24
Peak memory 211892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807521859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3807521859
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/4.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_lowpower_counter.1220139133
Short name T160
Test name
Test status
Simulation time 45696747163 ps
CPU time 56.08 seconds
Started Aug 28 08:14:10 PM UTC 24
Finished Aug 28 08:15:08 PM UTC 24
Peak memory 211220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220139133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1220139133
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/4.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_poweron_counter.925898594
Short name T44
Test name
Test status
Simulation time 2970407733 ps
CPU time 7.73 seconds
Started Aug 28 08:14:07 PM UTC 24
Finished Aug 28 08:14:16 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925898594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.925898594
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/4.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_sec_cm.589380512
Short name T80
Test name
Test status
Simulation time 8090209105 ps
CPU time 22.27 seconds
Started Aug 28 08:14:17 PM UTC 24
Finished Aug 28 08:14:40 PM UTC 24
Peak memory 243560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589380512 -assert nopostproc +UVM_TESTNAME=adc
_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.589380512
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/4.adc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_smoke.3194191946
Short name T41
Test name
Test status
Simulation time 5936528170 ps
CPU time 20.7 seconds
Started Aug 28 08:13:45 PM UTC 24
Finished Aug 28 08:14:07 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194191946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.3194191946
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/4.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all.1963204071
Short name T58
Test name
Test status
Simulation time 288226088775 ps
CPU time 786.91 seconds
Started Aug 28 08:14:17 PM UTC 24
Finished Aug 28 08:27:31 PM UTC 24
Peak memory 211764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963204071 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.1963204071
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_alert_test.1893231605
Short name T654
Test name
Test status
Simulation time 332613326 ps
CPU time 1.06 seconds
Started Aug 28 09:10:45 PM UTC 24
Finished Aug 28 09:10:47 PM UTC 24
Peak memory 209796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893231605 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.1893231605
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/40.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_clock_gating.1704984533
Short name T359
Test name
Test status
Simulation time 527303483092 ps
CPU time 599.27 seconds
Started Aug 28 09:10:02 PM UTC 24
Finished Aug 28 09:20:07 PM UTC 24
Peak memory 211616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704984533 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gating.1704984533
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/40.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_both.349953201
Short name T367
Test name
Test status
Simulation time 519400133932 ps
CPU time 1003.88 seconds
Started Aug 28 09:10:07 PM UTC 24
Finished Aug 28 09:27:01 PM UTC 24
Peak memory 211744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349953201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.349953201
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/40.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_interrupt.1140673367
Short name T784
Test name
Test status
Simulation time 499738443215 ps
CPU time 1333.75 seconds
Started Aug 28 09:09:42 PM UTC 24
Finished Aug 28 09:32:09 PM UTC 24
Peak memory 212816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140673367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1140673367
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/40.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1013502527
Short name T732
Test name
Test status
Simulation time 324619423105 ps
CPU time 743.51 seconds
Started Aug 28 09:09:43 PM UTC 24
Finished Aug 28 09:22:14 PM UTC 24
Peak memory 211596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013502527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt_fixed.1013502527
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_polled_fixed.3006498908
Short name T94
Test name
Test status
Simulation time 167379608263 ps
CPU time 351.56 seconds
Started Aug 28 09:09:42 PM UTC 24
Finished Aug 28 09:15:38 PM UTC 24
Peak memory 211604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006498908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixed.3006498908
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_wakeup.1593719780
Short name T792
Test name
Test status
Simulation time 518954696694 ps
CPU time 1594 seconds
Started Aug 28 09:09:48 PM UTC 24
Finished Aug 28 09:36:38 PM UTC 24
Peak memory 212484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593719780 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_wakeup.1593719780
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/40.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_wakeup_fixed.1039723037
Short name T658
Test name
Test status
Simulation time 391760520091 ps
CPU time 69.78 seconds
Started Aug 28 09:09:54 PM UTC 24
Finished Aug 28 09:11:06 PM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039723037 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_wakeup_fixed.1039723037
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_fsm_reset.3407443121
Short name T707
Test name
Test status
Simulation time 101258042134 ps
CPU time 538.25 seconds
Started Aug 28 09:10:18 PM UTC 24
Finished Aug 28 09:19:22 PM UTC 24
Peak memory 212020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407443121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.3407443121
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/40.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_lowpower_counter.745206978
Short name T668
Test name
Test status
Simulation time 41113507873 ps
CPU time 162.77 seconds
Started Aug 28 09:10:12 PM UTC 24
Finished Aug 28 09:12:57 PM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745206978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.745206978
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/40.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_poweron_counter.3292846990
Short name T651
Test name
Test status
Simulation time 4400161140 ps
CPU time 8.51 seconds
Started Aug 28 09:10:08 PM UTC 24
Finished Aug 28 09:10:17 PM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292846990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3292846990
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/40.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_smoke.2746711186
Short name T645
Test name
Test status
Simulation time 5904457193 ps
CPU time 3.65 seconds
Started Aug 28 09:09:37 PM UTC 24
Finished Aug 28 09:09:42 PM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746711186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.2746711186
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/40.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_stress_all.210674165
Short name T684
Test name
Test status
Simulation time 227676738143 ps
CPU time 302.38 seconds
Started Aug 28 09:10:40 PM UTC 24
Finished Aug 28 09:15:46 PM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210674165 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.210674165
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/40.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.4092320778
Short name T214
Test name
Test status
Simulation time 3201865072 ps
CPU time 18.96 seconds
Started Aug 28 09:10:28 PM UTC 24
Finished Aug 28 09:10:48 PM UTC 24
Peak memory 221936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=4092320778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 40.adc_ctrl_stress_all_with_rand_reset.4092320778
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_alert_test.2474769482
Short name T662
Test name
Test status
Simulation time 527907862 ps
CPU time 1.29 seconds
Started Aug 28 09:12:13 PM UTC 24
Finished Aug 28 09:12:16 PM UTC 24
Peak memory 209796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474769482 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.2474769482
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/41.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_clock_gating.3124098376
Short name T659
Test name
Test status
Simulation time 166034915390 ps
CPU time 5.27 seconds
Started Aug 28 09:11:07 PM UTC 24
Finished Aug 28 09:11:13 PM UTC 24
Peak memory 211692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124098376 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gating.3124098376
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/41.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_both.1104790308
Short name T705
Test name
Test status
Simulation time 504920424676 ps
CPU time 473.56 seconds
Started Aug 28 09:11:14 PM UTC 24
Finished Aug 28 09:19:13 PM UTC 24
Peak memory 211616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104790308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.1104790308
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/41.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_interrupt.3952953403
Short name T341
Test name
Test status
Simulation time 167305478480 ps
CPU time 454.89 seconds
Started Aug 28 09:11:00 PM UTC 24
Finished Aug 28 09:18:41 PM UTC 24
Peak memory 211428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952953403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.3952953403
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/41.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_interrupt_fixed.883636409
Short name T725
Test name
Test status
Simulation time 163508769696 ps
CPU time 609.61 seconds
Started Aug 28 09:11:02 PM UTC 24
Finished Aug 28 09:21:19 PM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883636409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt_fixed.883636409
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_polled.1696783782
Short name T347
Test name
Test status
Simulation time 332202809380 ps
CPU time 790.37 seconds
Started Aug 28 09:10:49 PM UTC 24
Finished Aug 28 09:24:07 PM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696783782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1696783782
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/41.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_polled_fixed.4264364586
Short name T697
Test name
Test status
Simulation time 490106350179 ps
CPU time 429.15 seconds
Started Aug 28 09:10:56 PM UTC 24
Finished Aug 28 09:18:10 PM UTC 24
Peak memory 211672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264364586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fixed.4264364586
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_wakeup.1112205218
Short name T192
Test name
Test status
Simulation time 590245003888 ps
CPU time 413.94 seconds
Started Aug 28 09:11:03 PM UTC 24
Finished Aug 28 09:18:01 PM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112205218 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_wakeup.1112205218
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/41.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1203297390
Short name T669
Test name
Test status
Simulation time 198554441656 ps
CPU time 112.82 seconds
Started Aug 28 09:11:04 PM UTC 24
Finished Aug 28 09:12:58 PM UTC 24
Peak memory 211736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203297390 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_wakeup_fixed.1203297390
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_fsm_reset.1565412583
Short name T773
Test name
Test status
Simulation time 117073150774 ps
CPU time 886.21 seconds
Started Aug 28 09:11:49 PM UTC 24
Finished Aug 28 09:26:44 PM UTC 24
Peak memory 211804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565412583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.1565412583
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/41.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_lowpower_counter.3839280144
Short name T661
Test name
Test status
Simulation time 22877544084 ps
CPU time 27.26 seconds
Started Aug 28 09:11:34 PM UTC 24
Finished Aug 28 09:12:02 PM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839280144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.3839280144
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/41.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_poweron_counter.2237022082
Short name T660
Test name
Test status
Simulation time 3582243505 ps
CPU time 11.15 seconds
Started Aug 28 09:11:21 PM UTC 24
Finished Aug 28 09:11:33 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237022082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.2237022082
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/41.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_smoke.313253196
Short name T657
Test name
Test status
Simulation time 5942139900 ps
CPU time 13.38 seconds
Started Aug 28 09:10:48 PM UTC 24
Finished Aug 28 09:11:03 PM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313253196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.313253196
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/41.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_stress_all.2637922632
Short name T777
Test name
Test status
Simulation time 327966273793 ps
CPU time 1002.94 seconds
Started Aug 28 09:12:03 PM UTC 24
Finished Aug 28 09:28:56 PM UTC 24
Peak memory 212472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637922632 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.2637922632
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/41.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_alert_test.3322080607
Short name T673
Test name
Test status
Simulation time 280274934 ps
CPU time 2.06 seconds
Started Aug 28 09:13:10 PM UTC 24
Finished Aug 28 09:13:14 PM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322080607 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.3322080607
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/42.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_clock_gating.1584669175
Short name T90
Test name
Test status
Simulation time 330075702977 ps
CPU time 146.94 seconds
Started Aug 28 09:12:43 PM UTC 24
Finished Aug 28 09:15:12 PM UTC 24
Peak memory 211432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584669175 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gating.1584669175
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/42.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_both.407682087
Short name T742
Test name
Test status
Simulation time 166821811157 ps
CPU time 610.11 seconds
Started Aug 28 09:12:52 PM UTC 24
Finished Aug 28 09:23:08 PM UTC 24
Peak memory 211812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407682087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.407682087
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/42.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_interrupt.1866853800
Short name T352
Test name
Test status
Simulation time 325753474324 ps
CPU time 375.14 seconds
Started Aug 28 09:12:27 PM UTC 24
Finished Aug 28 09:18:46 PM UTC 24
Peak memory 211692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866853800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.1866853800
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/42.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3700730823
Short name T764
Test name
Test status
Simulation time 492201667484 ps
CPU time 757.06 seconds
Started Aug 28 09:12:35 PM UTC 24
Finished Aug 28 09:25:20 PM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700730823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt_fixed.3700730823
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_polled.1623675494
Short name T765
Test name
Test status
Simulation time 490315428953 ps
CPU time 789.3 seconds
Started Aug 28 09:12:20 PM UTC 24
Finished Aug 28 09:25:38 PM UTC 24
Peak memory 211688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623675494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1623675494
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/42.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_polled_fixed.2109246659
Short name T89
Test name
Test status
Simulation time 328706184573 ps
CPU time 166.78 seconds
Started Aug 28 09:12:21 PM UTC 24
Finished Aug 28 09:15:11 PM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109246659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixed.2109246659
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_wakeup.3805920440
Short name T702
Test name
Test status
Simulation time 169668584755 ps
CPU time 375.01 seconds
Started Aug 28 09:12:36 PM UTC 24
Finished Aug 28 09:18:55 PM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805920440 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_wakeup.3805920440
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/42.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3889204577
Short name T716
Test name
Test status
Simulation time 406366148427 ps
CPU time 443.04 seconds
Started Aug 28 09:12:36 PM UTC 24
Finished Aug 28 09:20:03 PM UTC 24
Peak memory 211736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889204577 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_wakeup_fixed.3889204577
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_fsm_reset.4138661573
Short name T718
Test name
Test status
Simulation time 67538230756 ps
CPU time 436.58 seconds
Started Aug 28 09:13:03 PM UTC 24
Finished Aug 28 09:20:24 PM UTC 24
Peak memory 211812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138661573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.4138661573
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/42.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_lowpower_counter.1189513759
Short name T675
Test name
Test status
Simulation time 38094248055 ps
CPU time 37.03 seconds
Started Aug 28 09:12:59 PM UTC 24
Finished Aug 28 09:13:37 PM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189513759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.1189513759
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/42.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_poweron_counter.1715458365
Short name T670
Test name
Test status
Simulation time 2806015065 ps
CPU time 3.61 seconds
Started Aug 28 09:12:58 PM UTC 24
Finished Aug 28 09:13:03 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715458365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.1715458365
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/42.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_smoke.3706399480
Short name T665
Test name
Test status
Simulation time 6047997618 ps
CPU time 16.99 seconds
Started Aug 28 09:12:16 PM UTC 24
Finished Aug 28 09:12:34 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706399480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3706399480
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/42.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_stress_all.2514220156
Short name T795
Test name
Test status
Simulation time 1034312923725 ps
CPU time 1593.09 seconds
Started Aug 28 09:13:10 PM UTC 24
Finished Aug 28 09:40:00 PM UTC 24
Peak memory 223272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514220156 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.2514220156
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/42.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2230883978
Short name T303
Test name
Test status
Simulation time 60335337933 ps
CPU time 22.91 seconds
Started Aug 28 09:13:06 PM UTC 24
Finished Aug 28 09:13:30 PM UTC 24
Peak memory 221676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2230883978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 42.adc_ctrl_stress_all_with_rand_reset.2230883978
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_alert_test.1863373976
Short name T86
Test name
Test status
Simulation time 292847158 ps
CPU time 2.07 seconds
Started Aug 28 09:14:42 PM UTC 24
Finished Aug 28 09:14:46 PM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863373976 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.1863373976
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/43.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_clock_gating.859593368
Short name T345
Test name
Test status
Simulation time 363672730856 ps
CPU time 157.16 seconds
Started Aug 28 09:13:50 PM UTC 24
Finished Aug 28 09:16:29 PM UTC 24
Peak memory 211816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859593368 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gating.859593368
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/43.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_both.3341496095
Short name T781
Test name
Test status
Simulation time 323415301631 ps
CPU time 988.3 seconds
Started Aug 28 09:13:53 PM UTC 24
Finished Aug 28 09:30:31 PM UTC 24
Peak memory 212556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341496095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3341496095
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/43.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_interrupt.1694636759
Short name T293
Test name
Test status
Simulation time 163203399862 ps
CPU time 334.75 seconds
Started Aug 28 09:13:39 PM UTC 24
Finished Aug 28 09:19:17 PM UTC 24
Peak memory 211428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694636759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1694636759
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/43.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_interrupt_fixed.3607103446
Short name T763
Test name
Test status
Simulation time 493011705276 ps
CPU time 669.07 seconds
Started Aug 28 09:13:44 PM UTC 24
Finished Aug 28 09:24:59 PM UTC 24
Peak memory 211660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607103446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt_fixed.3607103446
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_polled.3920344155
Short name T701
Test name
Test status
Simulation time 163914358469 ps
CPU time 323.59 seconds
Started Aug 28 09:13:23 PM UTC 24
Finished Aug 28 09:18:52 PM UTC 24
Peak memory 211692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920344155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3920344155
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/43.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_polled_fixed.507337747
Short name T721
Test name
Test status
Simulation time 158822980595 ps
CPU time 426.66 seconds
Started Aug 28 09:13:31 PM UTC 24
Finished Aug 28 09:20:43 PM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507337747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixed.507337747
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_wakeup.1360978643
Short name T366
Test name
Test status
Simulation time 181519192519 ps
CPU time 580.38 seconds
Started Aug 28 09:13:46 PM UTC 24
Finished Aug 28 09:23:32 PM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360978643 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_wakeup.1360978643
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/43.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_wakeup_fixed.104650010
Short name T703
Test name
Test status
Simulation time 192353109556 ps
CPU time 309.2 seconds
Started Aug 28 09:13:48 PM UTC 24
Finished Aug 28 09:19:01 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104650010 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_wakeup_fixed.104650010
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_fsm_reset.1104464088
Short name T746
Test name
Test status
Simulation time 95223775281 ps
CPU time 531.7 seconds
Started Aug 28 09:14:25 PM UTC 24
Finished Aug 28 09:23:23 PM UTC 24
Peak memory 211772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104464088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.1104464088
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/43.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_lowpower_counter.2582900858
Short name T683
Test name
Test status
Simulation time 24963745727 ps
CPU time 25.89 seconds
Started Aug 28 09:14:04 PM UTC 24
Finished Aug 28 09:14:31 PM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582900858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.2582900858
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/43.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_poweron_counter.821093811
Short name T680
Test name
Test status
Simulation time 5075084793 ps
CPU time 6.27 seconds
Started Aug 28 09:13:56 PM UTC 24
Finished Aug 28 09:14:03 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821093811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.821093811
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/43.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_smoke.2945288817
Short name T674
Test name
Test status
Simulation time 5783536237 ps
CPU time 6.52 seconds
Started Aug 28 09:13:14 PM UTC 24
Finished Aug 28 09:13:22 PM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945288817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2945288817
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/43.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_stress_all.2465083105
Short name T384
Test name
Test status
Simulation time 143534400437 ps
CPU time 547.06 seconds
Started Aug 28 09:14:32 PM UTC 24
Finished Aug 28 09:23:45 PM UTC 24
Peak memory 211688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465083105 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.2465083105
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/43.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1227442856
Short name T82
Test name
Test status
Simulation time 35646334094 ps
CPU time 15.58 seconds
Started Aug 28 09:14:25 PM UTC 24
Finished Aug 28 09:14:42 PM UTC 24
Peak memory 221940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1227442856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 43.adc_ctrl_stress_all_with_rand_reset.1227442856
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_alert_test.3138601038
Short name T688
Test name
Test status
Simulation time 315328023 ps
CPU time 2.25 seconds
Started Aug 28 09:16:35 PM UTC 24
Finished Aug 28 09:16:38 PM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138601038 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.3138601038
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/44.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_clock_gating.1524301572
Short name T728
Test name
Test status
Simulation time 490356309815 ps
CPU time 363.03 seconds
Started Aug 28 09:15:35 PM UTC 24
Finished Aug 28 09:21:42 PM UTC 24
Peak memory 211540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524301572 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gating.1524301572
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/44.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_both.3146171755
Short name T782
Test name
Test status
Simulation time 326747585254 ps
CPU time 949.53 seconds
Started Aug 28 09:15:38 PM UTC 24
Finished Aug 28 09:31:38 PM UTC 24
Peak memory 212608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146171755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.3146171755
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/44.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_interrupt.1407430651
Short name T319
Test name
Test status
Simulation time 497332080903 ps
CPU time 382.77 seconds
Started Aug 28 09:15:12 PM UTC 24
Finished Aug 28 09:21:39 PM UTC 24
Peak memory 211616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407430651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.1407430651
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/44.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_interrupt_fixed.413409850
Short name T712
Test name
Test status
Simulation time 496138322927 ps
CPU time 266.1 seconds
Started Aug 28 09:15:13 PM UTC 24
Finished Aug 28 09:19:42 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413409850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt_fixed.413409850
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_polled.2571595000
Short name T785
Test name
Test status
Simulation time 330372876271 ps
CPU time 1047.77 seconds
Started Aug 28 09:14:49 PM UTC 24
Finished Aug 28 09:32:28 PM UTC 24
Peak memory 212496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571595000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.2571595000
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/44.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_polled_fixed.1484605631
Short name T686
Test name
Test status
Simulation time 329066791662 ps
CPU time 88.36 seconds
Started Aug 28 09:14:53 PM UTC 24
Finished Aug 28 09:16:23 PM UTC 24
Peak memory 211540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484605631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixed.1484605631
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_wakeup.2049834696
Short name T743
Test name
Test status
Simulation time 182138333636 ps
CPU time 477.27 seconds
Started Aug 28 09:15:16 PM UTC 24
Finished Aug 28 09:23:18 PM UTC 24
Peak memory 211736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049834696 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_wakeup.2049834696
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/44.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1022889034
Short name T739
Test name
Test status
Simulation time 589219932691 ps
CPU time 438.95 seconds
Started Aug 28 09:15:17 PM UTC 24
Finished Aug 28 09:22:40 PM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022889034 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_wakeup_fixed.1022889034
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_fsm_reset.2844627714
Short name T768
Test name
Test status
Simulation time 124577080918 ps
CPU time 561.02 seconds
Started Aug 28 09:16:23 PM UTC 24
Finished Aug 28 09:25:50 PM UTC 24
Peak memory 212016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844627714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.2844627714
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/44.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_lowpower_counter.1700617545
Short name T691
Test name
Test status
Simulation time 38700516404 ps
CPU time 73.11 seconds
Started Aug 28 09:16:03 PM UTC 24
Finished Aug 28 09:17:18 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700617545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1700617545
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/44.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_poweron_counter.2820117136
Short name T685
Test name
Test status
Simulation time 3403692958 ps
CPU time 13.75 seconds
Started Aug 28 09:15:47 PM UTC 24
Finished Aug 28 09:16:02 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820117136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2820117136
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/44.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_smoke.3943543477
Short name T87
Test name
Test status
Simulation time 6154620468 ps
CPU time 1.67 seconds
Started Aug 28 09:14:46 PM UTC 24
Finished Aug 28 09:14:49 PM UTC 24
Peak memory 209984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943543477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.3943543477
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/44.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_stress_all.1473084498
Short name T695
Test name
Test status
Simulation time 174455760914 ps
CPU time 88.79 seconds
Started Aug 28 09:16:30 PM UTC 24
Finished Aug 28 09:18:01 PM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473084498 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.1473084498
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/44.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.3038550912
Short name T689
Test name
Test status
Simulation time 15192689380 ps
CPU time 14.52 seconds
Started Aug 28 09:16:29 PM UTC 24
Finished Aug 28 09:16:45 PM UTC 24
Peak memory 221688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3038550912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 44.adc_ctrl_stress_all_with_rand_reset.3038550912
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_alert_test.559928407
Short name T699
Test name
Test status
Simulation time 527875780 ps
CPU time 1.34 seconds
Started Aug 28 09:18:32 PM UTC 24
Finished Aug 28 09:18:34 PM UTC 24
Peak memory 210340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559928407 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.559928407
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/45.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_clock_gating.1671191920
Short name T298
Test name
Test status
Simulation time 167032198626 ps
CPU time 334.18 seconds
Started Aug 28 09:17:49 PM UTC 24
Finished Aug 28 09:23:28 PM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671191920 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gating.1671191920
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/45.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_both.3896325009
Short name T772
Test name
Test status
Simulation time 547644364623 ps
CPU time 517.09 seconds
Started Aug 28 09:17:58 PM UTC 24
Finished Aug 28 09:26:41 PM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896325009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.3896325009
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/45.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_interrupt.4152945249
Short name T771
Test name
Test status
Simulation time 160625684167 ps
CPU time 552.86 seconds
Started Aug 28 09:17:06 PM UTC 24
Finished Aug 28 09:26:25 PM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152945249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.4152945249
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/45.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1333221672
Short name T737
Test name
Test status
Simulation time 502850890928 ps
CPU time 313.84 seconds
Started Aug 28 09:17:19 PM UTC 24
Finished Aug 28 09:22:37 PM UTC 24
Peak memory 211788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333221672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt_fixed.1333221672
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_polled.2804155661
Short name T756
Test name
Test status
Simulation time 160316184670 ps
CPU time 425.11 seconds
Started Aug 28 09:16:46 PM UTC 24
Finished Aug 28 09:23:55 PM UTC 24
Peak memory 211748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804155661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.2804155661
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/45.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_polled_fixed.4102457851
Short name T761
Test name
Test status
Simulation time 162861882552 ps
CPU time 467.43 seconds
Started Aug 28 09:16:48 PM UTC 24
Finished Aug 28 09:24:40 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102457851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixed.4102457851
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_wakeup.3615629694
Short name T731
Test name
Test status
Simulation time 371610230259 ps
CPU time 268.35 seconds
Started Aug 28 09:17:29 PM UTC 24
Finished Aug 28 09:22:01 PM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615629694 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_wakeup.3615629694
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/45.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2482037370
Short name T754
Test name
Test status
Simulation time 401266313040 ps
CPU time 369.94 seconds
Started Aug 28 09:17:33 PM UTC 24
Finished Aug 28 09:23:49 PM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482037370 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_wakeup_fixed.2482037370
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_fsm_reset.1404272596
Short name T783
Test name
Test status
Simulation time 122866172575 ps
CPU time 808.27 seconds
Started Aug 28 09:18:11 PM UTC 24
Finished Aug 28 09:31:47 PM UTC 24
Peak memory 211696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404272596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1404272596
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/45.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_lowpower_counter.2358280869
Short name T708
Test name
Test status
Simulation time 39379151812 ps
CPU time 83.76 seconds
Started Aug 28 09:18:02 PM UTC 24
Finished Aug 28 09:19:28 PM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358280869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2358280869
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/45.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_poweron_counter.2600994696
Short name T696
Test name
Test status
Simulation time 3210856230 ps
CPU time 6.15 seconds
Started Aug 28 09:18:02 PM UTC 24
Finished Aug 28 09:18:10 PM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600994696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2600994696
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/45.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_smoke.3160494205
Short name T690
Test name
Test status
Simulation time 5953839182 ps
CPU time 7.54 seconds
Started Aug 28 09:16:39 PM UTC 24
Finished Aug 28 09:16:47 PM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160494205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3160494205
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/45.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_stress_all.2989200665
Short name T752
Test name
Test status
Simulation time 205708243209 ps
CPU time 321.82 seconds
Started Aug 28 09:18:15 PM UTC 24
Finished Aug 28 09:23:40 PM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989200665 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all.2989200665
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/45.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.2651610573
Short name T698
Test name
Test status
Simulation time 4122394088 ps
CPU time 18.6 seconds
Started Aug 28 09:18:12 PM UTC 24
Finished Aug 28 09:18:31 PM UTC 24
Peak memory 221996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=2651610573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 45.adc_ctrl_stress_all_with_rand_reset.2651610573
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_alert_test.144017160
Short name T710
Test name
Test status
Simulation time 477460146 ps
CPU time 1.91 seconds
Started Aug 28 09:19:34 PM UTC 24
Finished Aug 28 09:19:37 PM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144017160 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.144017160
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/46.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_both.3243707698
Short name T759
Test name
Test status
Simulation time 332767908845 ps
CPU time 299.48 seconds
Started Aug 28 09:19:04 PM UTC 24
Finished Aug 28 09:24:08 PM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243707698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.3243707698
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/46.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_interrupt.3122947057
Short name T203
Test name
Test status
Simulation time 495852877318 ps
CPU time 397.56 seconds
Started Aug 28 09:18:47 PM UTC 24
Finished Aug 28 09:25:29 PM UTC 24
Peak memory 211564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122947057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.3122947057
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/46.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3920052591
Short name T727
Test name
Test status
Simulation time 164937050788 ps
CPU time 161.97 seconds
Started Aug 28 09:18:50 PM UTC 24
Finished Aug 28 09:21:35 PM UTC 24
Peak memory 211604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920052591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt_fixed.3920052591
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_polled.4286605161
Short name T726
Test name
Test status
Simulation time 162475186339 ps
CPU time 173.63 seconds
Started Aug 28 09:18:37 PM UTC 24
Finished Aug 28 09:21:33 PM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286605161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.4286605161
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/46.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_polled_fixed.3382784391
Short name T711
Test name
Test status
Simulation time 164261022667 ps
CPU time 56.03 seconds
Started Aug 28 09:18:41 PM UTC 24
Finished Aug 28 09:19:38 PM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382784391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fixed.3382784391
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_wakeup.4271500799
Short name T715
Test name
Test status
Simulation time 178905189383 ps
CPU time 69.6 seconds
Started Aug 28 09:18:52 PM UTC 24
Finished Aug 28 09:20:03 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271500799 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_wakeup.4271500799
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/46.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_wakeup_fixed.2716369198
Short name T794
Test name
Test status
Simulation time 405220152361 ps
CPU time 1234.21 seconds
Started Aug 28 09:18:56 PM UTC 24
Finished Aug 28 09:39:44 PM UTC 24
Peak memory 212808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716369198 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_wakeup_fixed.2716369198
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_fsm_reset.1476317824
Short name T770
Test name
Test status
Simulation time 96156352297 ps
CPU time 408.42 seconds
Started Aug 28 09:19:22 PM UTC 24
Finished Aug 28 09:26:15 PM UTC 24
Peak memory 212024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476317824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1476317824
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/46.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_lowpower_counter.2665965178
Short name T714
Test name
Test status
Simulation time 23040625060 ps
CPU time 40.54 seconds
Started Aug 28 09:19:17 PM UTC 24
Finished Aug 28 09:19:59 PM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665965178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2665965178
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/46.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_poweron_counter.2533376856
Short name T706
Test name
Test status
Simulation time 2857936633 ps
CPU time 6.68 seconds
Started Aug 28 09:19:13 PM UTC 24
Finished Aug 28 09:19:21 PM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533376856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2533376856
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/46.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_smoke.4062147267
Short name T700
Test name
Test status
Simulation time 5525840690 ps
CPU time 12.89 seconds
Started Aug 28 09:18:35 PM UTC 24
Finished Aug 28 09:18:49 PM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062147267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.4062147267
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/46.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_stress_all.3273446561
Short name T779
Test name
Test status
Simulation time 114927056773 ps
CPU time 579.87 seconds
Started Aug 28 09:19:29 PM UTC 24
Finished Aug 28 09:29:14 PM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273446561 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.3273446561
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/46.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.4131388348
Short name T36
Test name
Test status
Simulation time 56362038782 ps
CPU time 45.44 seconds
Started Aug 28 09:19:24 PM UTC 24
Finished Aug 28 09:20:11 PM UTC 24
Peak memory 221996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=4131388348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 46.adc_ctrl_stress_all_with_rand_reset.4131388348
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_alert_test.832468153
Short name T722
Test name
Test status
Simulation time 493624816 ps
CPU time 2.96 seconds
Started Aug 28 09:20:44 PM UTC 24
Finished Aug 28 09:20:48 PM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832468153 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.832468153
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/47.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_both.1372875283
Short name T796
Test name
Test status
Simulation time 385380156905 ps
CPU time 1272.91 seconds
Started Aug 28 09:20:11 PM UTC 24
Finished Aug 28 09:41:38 PM UTC 24
Peak memory 212608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372875283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.1372875283
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/47.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_interrupt.4098689475
Short name T337
Test name
Test status
Simulation time 485462989149 ps
CPU time 1482.8 seconds
Started Aug 28 09:19:44 PM UTC 24
Finished Aug 28 09:44:42 PM UTC 24
Peak memory 212492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098689475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.4098689475
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/47.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_interrupt_fixed.711133807
Short name T780
Test name
Test status
Simulation time 493271843808 ps
CPU time 595.17 seconds
Started Aug 28 09:20:00 PM UTC 24
Finished Aug 28 09:30:02 PM UTC 24
Peak memory 211792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711133807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt_fixed.711133807
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_polled.2388825748
Short name T797
Test name
Test status
Simulation time 482352228937 ps
CPU time 1630.17 seconds
Started Aug 28 09:19:39 PM UTC 24
Finished Aug 28 09:47:06 PM UTC 24
Peak memory 212760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388825748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2388825748
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/47.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_polled_fixed.3257453739
Short name T762
Test name
Test status
Simulation time 165623862809 ps
CPU time 303.92 seconds
Started Aug 28 09:19:43 PM UTC 24
Finished Aug 28 09:24:51 PM UTC 24
Peak memory 211672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257453739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixed.3257453739
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1823497112
Short name T774
Test name
Test status
Simulation time 204215889703 ps
CPU time 413.49 seconds
Started Aug 28 09:20:04 PM UTC 24
Finished Aug 28 09:27:03 PM UTC 24
Peak memory 211528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823497112 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_wakeup_fixed.1823497112
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_fsm_reset.2457243163
Short name T769
Test name
Test status
Simulation time 79983741332 ps
CPU time 326.87 seconds
Started Aug 28 09:20:38 PM UTC 24
Finished Aug 28 09:26:08 PM UTC 24
Peak memory 212080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457243163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.2457243163
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/47.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_lowpower_counter.3064939555
Short name T740
Test name
Test status
Simulation time 39825404615 ps
CPU time 133.85 seconds
Started Aug 28 09:20:25 PM UTC 24
Finished Aug 28 09:22:42 PM UTC 24
Peak memory 211344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064939555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3064939555
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/47.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_poweron_counter.1105134975
Short name T720
Test name
Test status
Simulation time 5011336752 ps
CPU time 21.19 seconds
Started Aug 28 09:20:15 PM UTC 24
Finished Aug 28 09:20:38 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105134975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1105134975
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/47.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_smoke.3106842847
Short name T713
Test name
Test status
Simulation time 5896490613 ps
CPU time 4.5 seconds
Started Aug 28 09:19:38 PM UTC 24
Finished Aug 28 09:19:43 PM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106842847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.3106842847
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/47.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_stress_all.2227531532
Short name T749
Test name
Test status
Simulation time 166347307449 ps
CPU time 161.45 seconds
Started Aug 28 09:20:44 PM UTC 24
Finished Aug 28 09:23:28 PM UTC 24
Peak memory 211608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227531532 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.2227531532
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/47.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.3487666034
Short name T45
Test name
Test status
Simulation time 1643975997 ps
CPU time 13.23 seconds
Started Aug 28 09:20:39 PM UTC 24
Finished Aug 28 09:20:53 PM UTC 24
Peak memory 221688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3487666034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 47.adc_ctrl_stress_all_with_rand_reset.3487666034
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_alert_test.1915573596
Short name T735
Test name
Test status
Simulation time 414280048 ps
CPU time 2.57 seconds
Started Aug 28 09:22:28 PM UTC 24
Finished Aug 28 09:22:32 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915573596 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1915573596
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/48.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_clock_gating.1723014537
Short name T748
Test name
Test status
Simulation time 224149074910 ps
CPU time 103.61 seconds
Started Aug 28 09:21:39 PM UTC 24
Finished Aug 28 09:23:25 PM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723014537 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gating.1723014537
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/48.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_both.2378338172
Short name T734
Test name
Test status
Simulation time 169962381983 ps
CPU time 41.77 seconds
Started Aug 28 09:21:43 PM UTC 24
Finished Aug 28 09:22:27 PM UTC 24
Peak memory 211716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378338172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2378338172
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/48.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_interrupt.3103608693
Short name T767
Test name
Test status
Simulation time 164981825807 ps
CPU time 266.47 seconds
Started Aug 28 09:21:15 PM UTC 24
Finished Aug 28 09:25:45 PM UTC 24
Peak memory 211428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103608693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3103608693
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/48.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_interrupt_fixed.261454068
Short name T787
Test name
Test status
Simulation time 502222622380 ps
CPU time 783.11 seconds
Started Aug 28 09:21:19 PM UTC 24
Finished Aug 28 09:34:31 PM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261454068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt_fixed.261454068
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_polled.1110777449
Short name T729
Test name
Test status
Simulation time 172237676182 ps
CPU time 58.79 seconds
Started Aug 28 09:20:54 PM UTC 24
Finished Aug 28 09:21:54 PM UTC 24
Peak memory 211748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110777449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.1110777449
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/48.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_polled_fixed.3901553025
Short name T758
Test name
Test status
Simulation time 167298576695 ps
CPU time 165.26 seconds
Started Aug 28 09:21:15 PM UTC 24
Finished Aug 28 09:24:03 PM UTC 24
Peak memory 211672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901553025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixed.3901553025
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_wakeup.3101620012
Short name T354
Test name
Test status
Simulation time 542090202574 ps
CPU time 1826.4 seconds
Started Aug 28 09:21:34 PM UTC 24
Finished Aug 28 09:52:20 PM UTC 24
Peak memory 212484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101620012 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_wakeup.3101620012
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/48.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_wakeup_fixed.20060924
Short name T744
Test name
Test status
Simulation time 195082311502 ps
CPU time 100.14 seconds
Started Aug 28 09:21:36 PM UTC 24
Finished Aug 28 09:23:19 PM UTC 24
Peak memory 211516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20060924 -assert nopostpro
c +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_wakeup_fixed.20060924
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_fsm_reset.3709949361
Short name T778
Test name
Test status
Simulation time 121170926892 ps
CPU time 412.57 seconds
Started Aug 28 09:22:02 PM UTC 24
Finished Aug 28 09:28:59 PM UTC 24
Peak memory 211832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709949361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3709949361
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/48.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_lowpower_counter.2856756793
Short name T738
Test name
Test status
Simulation time 41383182751 ps
CPU time 35.78 seconds
Started Aug 28 09:22:00 PM UTC 24
Finished Aug 28 09:22:37 PM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856756793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.2856756793
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/48.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_poweron_counter.2037744045
Short name T730
Test name
Test status
Simulation time 4850418814 ps
CPU time 3.54 seconds
Started Aug 28 09:21:55 PM UTC 24
Finished Aug 28 09:21:59 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037744045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2037744045
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/48.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_smoke.959725587
Short name T723
Test name
Test status
Simulation time 5718143387 ps
CPU time 24.24 seconds
Started Aug 28 09:20:49 PM UTC 24
Finished Aug 28 09:21:14 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959725587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.959725587
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/48.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_stress_all.290127254
Short name T798
Test name
Test status
Simulation time 516379475968 ps
CPU time 1778.73 seconds
Started Aug 28 09:22:25 PM UTC 24
Finished Aug 28 09:52:21 PM UTC 24
Peak memory 223056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290127254 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.290127254
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/48.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.708849776
Short name T733
Test name
Test status
Simulation time 6990021609 ps
CPU time 8.44 seconds
Started Aug 28 09:22:15 PM UTC 24
Finished Aug 28 09:22:24 PM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=708849776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
48.adc_ctrl_stress_all_with_rand_reset.708849776
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_alert_test.2394289830
Short name T750
Test name
Test status
Simulation time 535628790 ps
CPU time 2.02 seconds
Started Aug 28 09:23:26 PM UTC 24
Finished Aug 28 09:23:29 PM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394289830 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.2394289830
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/49.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_clock_gating.293710843
Short name T342
Test name
Test status
Simulation time 362166838392 ps
CPU time 182.7 seconds
Started Aug 28 09:22:55 PM UTC 24
Finished Aug 28 09:26:01 PM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293710843 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gating.293710843
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/49.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_both.2419695163
Short name T776
Test name
Test status
Simulation time 184180231296 ps
CPU time 312.75 seconds
Started Aug 28 09:23:09 PM UTC 24
Finished Aug 28 09:28:27 PM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419695163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2419695163
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/49.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt_fixed.95762787
Short name T793
Test name
Test status
Simulation time 332622934393 ps
CPU time 1012.88 seconds
Started Aug 28 09:22:37 PM UTC 24
Finished Aug 28 09:39:41 PM UTC 24
Peak memory 212812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95762787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas
e_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt_fixed.95762787
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_polled.273233180
Short name T790
Test name
Test status
Simulation time 491573608572 ps
CPU time 785.51 seconds
Started Aug 28 09:22:32 PM UTC 24
Finished Aug 28 09:35:46 PM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273233180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.273233180
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/49.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_polled_fixed.1715436457
Short name T775
Test name
Test status
Simulation time 489441359283 ps
CPU time 348.23 seconds
Started Aug 28 09:22:34 PM UTC 24
Finished Aug 28 09:28:27 PM UTC 24
Peak memory 211460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715436457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixed.1715436457
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_wakeup.2250061974
Short name T204
Test name
Test status
Simulation time 411528341784 ps
CPU time 187.9 seconds
Started Aug 28 09:22:41 PM UTC 24
Finished Aug 28 09:25:52 PM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250061974 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_wakeup.2250061974
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/49.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_wakeup_fixed.2251621285
Short name T788
Test name
Test status
Simulation time 211997455680 ps
CPU time 744.48 seconds
Started Aug 28 09:22:42 PM UTC 24
Finished Aug 28 09:35:15 PM UTC 24
Peak memory 211736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251621285 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_wakeup_fixed.2251621285
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_fsm_reset.992944712
Short name T389
Test name
Test status
Simulation time 127295581017 ps
CPU time 902.83 seconds
Started Aug 28 09:23:22 PM UTC 24
Finished Aug 28 09:38:33 PM UTC 24
Peak memory 212844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992944712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.992944712
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/49.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_lowpower_counter.755129188
Short name T755
Test name
Test status
Simulation time 24997293066 ps
CPU time 33.29 seconds
Started Aug 28 09:23:20 PM UTC 24
Finished Aug 28 09:23:54 PM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755129188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.755129188
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/49.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_poweron_counter.2041055249
Short name T747
Test name
Test status
Simulation time 4980483997 ps
CPU time 3.93 seconds
Started Aug 28 09:23:19 PM UTC 24
Finished Aug 28 09:23:24 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041055249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2041055249
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/49.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_smoke.838641056
Short name T736
Test name
Test status
Simulation time 5788141939 ps
CPU time 3.69 seconds
Started Aug 28 09:22:29 PM UTC 24
Finished Aug 28 09:22:34 PM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838641056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.838641056
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/49.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_stress_all.1792963909
Short name T757
Test name
Test status
Simulation time 47399111677 ps
CPU time 32.01 seconds
Started Aug 28 09:23:25 PM UTC 24
Finished Aug 28 09:23:58 PM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792963909 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.1792963909
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/49.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.1727498718
Short name T751
Test name
Test status
Simulation time 18703391456 ps
CPU time 14.62 seconds
Started Aug 28 09:23:24 PM UTC 24
Finished Aug 28 09:23:40 PM UTC 24
Peak memory 221932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1727498718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 49.adc_ctrl_stress_all_with_rand_reset.1727498718
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_alert_test.1500892260
Short name T162
Test name
Test status
Simulation time 385390619 ps
CPU time 1.13 seconds
Started Aug 28 08:15:33 PM UTC 24
Finished Aug 28 08:15:36 PM UTC 24
Peak memory 210340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500892260 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.1500892260
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/5.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_clock_gating.3401791434
Short name T146
Test name
Test status
Simulation time 176994581426 ps
CPU time 500.34 seconds
Started Aug 28 08:14:57 PM UTC 24
Finished Aug 28 08:23:22 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401791434 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gating.3401791434
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/5.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_both.221013578
Short name T54
Test name
Test status
Simulation time 184682919954 ps
CPU time 143.52 seconds
Started Aug 28 08:14:57 PM UTC 24
Finished Aug 28 08:17:22 PM UTC 24
Peak memory 211460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221013578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.221013578
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/5.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt.3449222643
Short name T231
Test name
Test status
Simulation time 496050912969 ps
CPU time 800.06 seconds
Started Aug 28 08:14:41 PM UTC 24
Finished Aug 28 08:28:09 PM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449222643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3449222643
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/5.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1111350052
Short name T399
Test name
Test status
Simulation time 335197264999 ps
CPU time 324.25 seconds
Started Aug 28 08:14:42 PM UTC 24
Finished Aug 28 08:20:11 PM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111350052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt_fixed.1111350052
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled.325440475
Short name T165
Test name
Test status
Simulation time 332232548357 ps
CPU time 947.49 seconds
Started Aug 28 08:14:28 PM UTC 24
Finished Aug 28 08:30:25 PM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325440475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.325440475
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/5.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled_fixed.1861528894
Short name T405
Test name
Test status
Simulation time 325508086032 ps
CPU time 452.58 seconds
Started Aug 28 08:14:29 PM UTC 24
Finished Aug 28 08:22:07 PM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861528894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed.1861528894
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1921031463
Short name T488
Test name
Test status
Simulation time 612250499010 ps
CPU time 1745.92 seconds
Started Aug 28 08:14:56 PM UTC 24
Finished Aug 28 08:44:17 PM UTC 24
Peak memory 212480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921031463 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_wakeup_fixed.1921031463
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_fsm_reset.2795864089
Short name T377
Test name
Test status
Simulation time 121069514163 ps
CPU time 804.56 seconds
Started Aug 28 08:15:16 PM UTC 24
Finished Aug 28 08:28:49 PM UTC 24
Peak memory 211968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795864089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2795864089
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/5.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_lowpower_counter.1426320766
Short name T148
Test name
Test status
Simulation time 40777589944 ps
CPU time 61.54 seconds
Started Aug 28 08:15:12 PM UTC 24
Finished Aug 28 08:16:15 PM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426320766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1426320766
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/5.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_poweron_counter.871985700
Short name T161
Test name
Test status
Simulation time 4942961241 ps
CPU time 6.47 seconds
Started Aug 28 08:15:09 PM UTC 24
Finished Aug 28 08:15:16 PM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871985700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.871985700
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/5.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_smoke.4081291399
Short name T159
Test name
Test status
Simulation time 5742275226 ps
CPU time 27.4 seconds
Started Aug 28 08:14:26 PM UTC 24
Finished Aug 28 08:14:55 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081291399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.4081291399
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/5.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1620232814
Short name T20
Test name
Test status
Simulation time 69715571495 ps
CPU time 35.73 seconds
Started Aug 28 08:15:17 PM UTC 24
Finished Aug 28 08:15:54 PM UTC 24
Peak memory 221628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1620232814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.adc_ctrl_stress_all_with_rand_reset.1620232814
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_alert_test.1783769176
Short name T172
Test name
Test status
Simulation time 355952453 ps
CPU time 1.22 seconds
Started Aug 28 08:16:55 PM UTC 24
Finished Aug 28 08:16:57 PM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783769176 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.1783769176
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/6.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt_fixed.1322584257
Short name T141
Test name
Test status
Simulation time 326423606715 ps
CPU time 105.97 seconds
Started Aug 28 08:15:55 PM UTC 24
Finished Aug 28 08:17:43 PM UTC 24
Peak memory 211680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322584257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt_fixed.1322584257
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled.4101624896
Short name T222
Test name
Test status
Simulation time 486876704820 ps
CPU time 407.51 seconds
Started Aug 28 08:15:43 PM UTC 24
Finished Aug 28 08:22:35 PM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101624896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.4101624896
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/6.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled_fixed.3017419278
Short name T395
Test name
Test status
Simulation time 162141979802 ps
CPU time 206.18 seconds
Started Aug 28 08:15:45 PM UTC 24
Finished Aug 28 08:19:14 PM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017419278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixed.3017419278
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup.2492374630
Short name T139
Test name
Test status
Simulation time 384394395710 ps
CPU time 267.47 seconds
Started Aug 28 08:16:00 PM UTC 24
Finished Aug 28 08:20:31 PM UTC 24
Peak memory 211808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492374630 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_wakeup.2492374630
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/6.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup_fixed.4085981035
Short name T440
Test name
Test status
Simulation time 392088846888 ps
CPU time 914.33 seconds
Started Aug 28 08:16:11 PM UTC 24
Finished Aug 28 08:31:35 PM UTC 24
Peak memory 211404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085981035 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_wakeup_fixed.4085981035
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_lowpower_counter.929969734
Short name T184
Test name
Test status
Simulation time 39516714859 ps
CPU time 91.76 seconds
Started Aug 28 08:16:29 PM UTC 24
Finished Aug 28 08:18:03 PM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929969734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.929969734
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/6.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_poweron_counter.904717779
Short name T149
Test name
Test status
Simulation time 2791317546 ps
CPU time 2.83 seconds
Started Aug 28 08:16:24 PM UTC 24
Finished Aug 28 08:16:28 PM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904717779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.904717779
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/6.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_smoke.4209971352
Short name T147
Test name
Test status
Simulation time 6060156322 ps
CPU time 13.95 seconds
Started Aug 28 08:15:36 PM UTC 24
Finished Aug 28 08:15:52 PM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209971352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.4209971352
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/6.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all.1657991086
Short name T228
Test name
Test status
Simulation time 209950493688 ps
CPU time 666.78 seconds
Started Aug 28 08:16:50 PM UTC 24
Finished Aug 28 08:28:04 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657991086 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.1657991086
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/6.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.1991258987
Short name T48
Test name
Test status
Simulation time 2752067988 ps
CPU time 13.6 seconds
Started Aug 28 08:16:35 PM UTC 24
Finished Aug 28 08:16:50 PM UTC 24
Peak memory 221676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1991258987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.adc_ctrl_stress_all_with_rand_reset.1991258987
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_alert_test.1644030606
Short name T186
Test name
Test status
Simulation time 377218445 ps
CPU time 1.29 seconds
Started Aug 28 08:18:11 PM UTC 24
Finished Aug 28 08:18:13 PM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644030606 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.1644030606
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/7.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_clock_gating.1522132472
Short name T138
Test name
Test status
Simulation time 519228240986 ps
CPU time 222.4 seconds
Started Aug 28 08:17:38 PM UTC 24
Finished Aug 28 08:21:24 PM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522132472 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gating.1522132472
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/7.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_both.1435705340
Short name T239
Test name
Test status
Simulation time 352103202058 ps
CPU time 820.15 seconds
Started Aug 28 08:17:43 PM UTC 24
Finished Aug 28 08:31:31 PM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435705340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.1435705340
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/7.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt.1553086815
Short name T235
Test name
Test status
Simulation time 161017941602 ps
CPU time 663.09 seconds
Started Aug 28 08:17:14 PM UTC 24
Finished Aug 28 08:28:25 PM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553086815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1553086815
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/7.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3884878998
Short name T193
Test name
Test status
Simulation time 166102070545 ps
CPU time 91.65 seconds
Started Aug 28 08:17:17 PM UTC 24
Finished Aug 28 08:18:50 PM UTC 24
Peak memory 211796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884878998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt_fixed.3884878998
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled.398530238
Short name T208
Test name
Test status
Simulation time 165498089961 ps
CPU time 220.73 seconds
Started Aug 28 08:17:08 PM UTC 24
Finished Aug 28 08:20:52 PM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398530238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.398530238
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/7.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled_fixed.3769056933
Short name T396
Test name
Test status
Simulation time 171102351310 ps
CPU time 133.59 seconds
Started Aug 28 08:17:08 PM UTC 24
Finished Aug 28 08:19:23 PM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769056933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed.3769056933
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup.1052365148
Short name T253
Test name
Test status
Simulation time 354965151499 ps
CPU time 871.88 seconds
Started Aug 28 08:17:23 PM UTC 24
Finished Aug 28 08:32:04 PM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052365148 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_wakeup.1052365148
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/7.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup_fixed.382029136
Short name T257
Test name
Test status
Simulation time 403740810947 ps
CPU time 391.2 seconds
Started Aug 28 08:17:28 PM UTC 24
Finished Aug 28 08:24:04 PM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382029136 -assert nopostpr
oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_wakeup_fixed.382029136
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_fsm_reset.840006700
Short name T373
Test name
Test status
Simulation time 111816227873 ps
CPU time 610.12 seconds
Started Aug 28 08:17:50 PM UTC 24
Finished Aug 28 08:28:06 PM UTC 24
Peak memory 212028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840006700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.840006700
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/7.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_lowpower_counter.1762220272
Short name T185
Test name
Test status
Simulation time 42386672646 ps
CPU time 21.04 seconds
Started Aug 28 08:17:48 PM UTC 24
Finished Aug 28 08:18:10 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762220272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.1762220272
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/7.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_poweron_counter.3982543201
Short name T183
Test name
Test status
Simulation time 4096286289 ps
CPU time 5.01 seconds
Started Aug 28 08:17:45 PM UTC 24
Finished Aug 28 08:17:51 PM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982543201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.3982543201
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/7.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_smoke.419834986
Short name T173
Test name
Test status
Simulation time 6017492466 ps
CPU time 17.14 seconds
Started Aug 28 08:16:58 PM UTC 24
Finished Aug 28 08:17:16 PM UTC 24
Peak memory 211544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419834986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.419834986
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/7.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1074381201
Short name T49
Test name
Test status
Simulation time 7364333158 ps
CPU time 16.76 seconds
Started Aug 28 08:17:52 PM UTC 24
Finished Aug 28 08:18:10 PM UTC 24
Peak memory 211680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1074381201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.adc_ctrl_stress_all_with_rand_reset.1074381201
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_alert_test.2615406946
Short name T397
Test name
Test status
Simulation time 408824629 ps
CPU time 1.7 seconds
Started Aug 28 08:19:57 PM UTC 24
Finished Aug 28 08:20:01 PM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615406946 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2615406946
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/8.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt_fixed.1785518683
Short name T143
Test name
Test status
Simulation time 491945637492 ps
CPU time 196.99 seconds
Started Aug 28 08:18:36 PM UTC 24
Finished Aug 28 08:21:56 PM UTC 24
Peak memory 211544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785518683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt_fixed.1785518683
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled.228939775
Short name T158
Test name
Test status
Simulation time 164699974845 ps
CPU time 30.45 seconds
Started Aug 28 08:18:14 PM UTC 24
Finished Aug 28 08:18:46 PM UTC 24
Peak memory 211796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228939775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.228939775
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/8.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled_fixed.1544125584
Short name T480
Test name
Test status
Simulation time 478340596376 ps
CPU time 1374.74 seconds
Started Aug 28 08:18:15 PM UTC 24
Finished Aug 28 08:41:24 PM UTC 24
Peak memory 212464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544125584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed.1544125584
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup.2591122660
Short name T323
Test name
Test status
Simulation time 527669764381 ps
CPU time 1798.75 seconds
Started Aug 28 08:18:39 PM UTC 24
Finished Aug 28 08:48:57 PM UTC 24
Peak memory 212552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591122660 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_wakeup.2591122660
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/8.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1376369175
Short name T433
Test name
Test status
Simulation time 205361374863 ps
CPU time 647.83 seconds
Started Aug 28 08:18:42 PM UTC 24
Finished Aug 28 08:29:37 PM UTC 24
Peak memory 211732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376369175 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_wakeup_fixed.1376369175
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_fsm_reset.909331462
Short name T380
Test name
Test status
Simulation time 122445824364 ps
CPU time 906.69 seconds
Started Aug 28 08:19:15 PM UTC 24
Finished Aug 28 08:34:31 PM UTC 24
Peak memory 211756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909331462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.909331462
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/8.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_lowpower_counter.511592045
Short name T205
Test name
Test status
Simulation time 44458303548 ps
CPU time 78.34 seconds
Started Aug 28 08:19:04 PM UTC 24
Finished Aug 28 08:20:24 PM UTC 24
Peak memory 211200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511592045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.511592045
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/8.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_poweron_counter.766544891
Short name T394
Test name
Test status
Simulation time 4525120437 ps
CPU time 10.07 seconds
Started Aug 28 08:18:52 PM UTC 24
Finished Aug 28 08:19:03 PM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766544891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.766544891
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/8.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_smoke.602318009
Short name T392
Test name
Test status
Simulation time 5944032366 ps
CPU time 2.8 seconds
Started Aug 28 08:18:11 PM UTC 24
Finished Aug 28 08:18:15 PM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602318009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.602318009
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/8.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all.739460341
Short name T290
Test name
Test status
Simulation time 570784674410 ps
CPU time 2002.99 seconds
Started Aug 28 08:19:55 PM UTC 24
Finished Aug 28 08:53:37 PM UTC 24
Peak memory 213144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739460341 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.739460341
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/8.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3243924720
Short name T50
Test name
Test status
Simulation time 78394684580 ps
CPU time 28.97 seconds
Started Aug 28 08:19:24 PM UTC 24
Finished Aug 28 08:19:54 PM UTC 24
Peak memory 222016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3243924720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.adc_ctrl_stress_all_with_rand_reset.3243924720
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_alert_test.1088579642
Short name T210
Test name
Test status
Simulation time 301344077 ps
CPU time 2.1 seconds
Started Aug 28 08:21:05 PM UTC 24
Finished Aug 28 08:21:09 PM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088579642 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1088579642
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/9.adc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_clock_gating.3592010172
Short name T188
Test name
Test status
Simulation time 163639366454 ps
CPU time 99.75 seconds
Started Aug 28 08:20:29 PM UTC 24
Finished Aug 28 08:22:10 PM UTC 24
Peak memory 211432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592010172 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gating.3592010172
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/9.adc_ctrl_clock_gating/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_both.1506708226
Short name T226
Test name
Test status
Simulation time 163127146393 ps
CPU time 550.56 seconds
Started Aug 28 08:20:30 PM UTC 24
Finished Aug 28 08:29:47 PM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506708226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.1506708226
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/9.adc_ctrl_filters_both/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt.2947863945
Short name T264
Test name
Test status
Simulation time 494528287186 ps
CPU time 1108.54 seconds
Started Aug 28 08:20:14 PM UTC 24
Finished Aug 28 08:38:54 PM UTC 24
Peak memory 212568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947863945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2947863945
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/9.adc_ctrl_filters_interrupt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt_fixed.557126021
Short name T194
Test name
Test status
Simulation time 328364538353 ps
CPU time 163.89 seconds
Started Aug 28 08:20:21 PM UTC 24
Finished Aug 28 08:23:08 PM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557126021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba
se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt_fixed.557126021
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled.757021141
Short name T142
Test name
Test status
Simulation time 164902789229 ps
CPU time 89.12 seconds
Started Aug 28 08:20:10 PM UTC 24
Finished Aug 28 08:21:42 PM UTC 24
Peak memory 211612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757021141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.757021141
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/9.adc_ctrl_filters_polled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled_fixed.2371634700
Short name T415
Test name
Test status
Simulation time 494077778323 ps
CPU time 306.88 seconds
Started Aug 28 08:20:11 PM UTC 24
Finished Aug 28 08:25:22 PM UTC 24
Peak memory 211544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371634700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b
ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed.2371634700
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup.350959213
Short name T256
Test name
Test status
Simulation time 204826495655 ps
CPU time 572.14 seconds
Started Aug 28 08:20:25 PM UTC 24
Finished Aug 28 08:30:03 PM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350959213 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_wakeup.350959213
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/9.adc_ctrl_filters_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1687687889
Short name T462
Test name
Test status
Simulation time 401374996413 ps
CPU time 1025.32 seconds
Started Aug 28 08:20:25 PM UTC 24
Finished Aug 28 08:37:40 PM UTC 24
Peak memory 212600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687687889 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_wakeup_fixed.1687687889
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.1864898180
Short name T458
Test name
Test status
Simulation time 130042276366 ps
CPU time 970.34 seconds
Started Aug 28 08:20:50 PM UTC 24
Finished Aug 28 08:37:10 PM UTC 24
Peak memory 211776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864898180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.1864898180
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/9.adc_ctrl_fsm_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_lowpower_counter.921775204
Short name T400
Test name
Test status
Simulation time 22955801304 ps
CPU time 24.17 seconds
Started Aug 28 08:20:49 PM UTC 24
Finished Aug 28 08:21:14 PM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921775204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.921775204
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/9.adc_ctrl_lowpower_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_poweron_counter.944003316
Short name T207
Test name
Test status
Simulation time 3269936283 ps
CPU time 15.24 seconds
Started Aug 28 08:20:32 PM UTC 24
Finished Aug 28 08:20:48 PM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944003316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST
_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.944003316
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/9.adc_ctrl_poweron_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_smoke.3186536457
Short name T398
Test name
Test status
Simulation time 5662309347 ps
CPU time 7.49 seconds
Started Aug 28 08:20:01 PM UTC 24
Finished Aug 28 08:20:10 PM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186536457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES
T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.3186536457
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/9.adc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all.1705450471
Short name T223
Test name
Test status
Simulation time 178697932019 ps
CPU time 164.51 seconds
Started Aug 28 08:21:04 PM UTC 24
Finished Aug 28 08:23:51 PM UTC 24
Peak memory 211872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705450471 -assert nopostproc +UVM_TESTNAM
E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.1705450471
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.218998028
Short name T51
Test name
Test status
Simulation time 4421077567 ps
CPU time 26.62 seconds
Started Aug 28 08:20:52 PM UTC 24
Finished Aug 28 08:21:20 PM UTC 24
Peak memory 221968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=218998028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
9.adc_ctrl_stress_all_with_rand_reset.218998028
Directory /workspaces/repo/scratch/os_regression_2024_08_28/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all_with_rand_reset/latest
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