| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.71 | 99.07 | 96.67 | 100.00 | 100.00 | 98.83 | 98.33 | 91.09 |
| T795 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_both.2998131817 | Sep 01 08:48:36 AM UTC 24 | Sep 01 09:12:09 AM UTC 24 | 498908301546 ps | ||
| T796 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_polled_fixed.470943636 | Sep 01 08:47:35 AM UTC 24 | Sep 01 09:12:45 AM UTC 24 | 497470082381 ps | ||
| T306 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_stress_all.3594553737 | Sep 01 08:43:08 AM UTC 24 | Sep 01 09:13:20 AM UTC 24 | 578378529995 ps | ||
| T797 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3069093514 | Sep 01 08:51:33 AM UTC 24 | Sep 01 09:15:14 AM UTC 24 | 487854220034 ps | ||
| T798 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_polled_fixed.4116366252 | Sep 01 08:51:02 AM UTC 24 | Sep 01 09:17:06 AM UTC 24 | 487791959390 ps | ||
| T799 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.2417476332 | Sep 01 06:24:35 AM UTC 24 | Sep 01 06:24:38 AM UTC 24 | 481140570 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2809419815 | Sep 01 06:24:35 AM UTC 24 | Sep 01 06:24:38 AM UTC 24 | 552246853 ps | ||
| T110 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3631520354 | Sep 01 06:24:36 AM UTC 24 | Sep 01 06:24:39 AM UTC 24 | 596106838 ps | ||
| T800 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.1431870029 | Sep 01 06:24:37 AM UTC 24 | Sep 01 06:24:40 AM UTC 24 | 519251110 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1631994785 | Sep 01 06:24:37 AM UTC 24 | Sep 01 06:24:41 AM UTC 24 | 533731286 ps | ||
| T111 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2905463464 | Sep 01 06:24:39 AM UTC 24 | Sep 01 06:24:41 AM UTC 24 | 373082223 ps | ||
| T125 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.4250362991 | Sep 01 06:24:38 AM UTC 24 | Sep 01 06:24:42 AM UTC 24 | 1164894174 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1003748988 | Sep 01 06:24:36 AM UTC 24 | Sep 01 06:24:42 AM UTC 24 | 2046533796 ps | ||
| T112 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2771619515 | Sep 01 06:24:36 AM UTC 24 | Sep 01 06:24:42 AM UTC 24 | 1098257483 ps | ||
| T126 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2427742278 | Sep 01 06:24:36 AM UTC 24 | Sep 01 06:24:43 AM UTC 24 | 1282586225 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.846495827 | Sep 01 06:24:37 AM UTC 24 | Sep 01 06:24:44 AM UTC 24 | 511464526 ps | ||
| T801 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.2025502524 | Sep 01 06:24:41 AM UTC 24 | Sep 01 06:24:44 AM UTC 24 | 481722173 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3630829104 | Sep 01 06:24:41 AM UTC 24 | Sep 01 06:24:44 AM UTC 24 | 526044285 ps | ||
| T127 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1174886651 | Sep 01 06:24:41 AM UTC 24 | Sep 01 06:24:45 AM UTC 24 | 1281867577 ps | ||
| T113 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1831717786 | Sep 01 06:24:42 AM UTC 24 | Sep 01 06:24:45 AM UTC 24 | 384106638 ps | ||
| T79 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3937249592 | Sep 01 06:24:41 AM UTC 24 | Sep 01 06:24:46 AM UTC 24 | 546677353 ps | ||
| T802 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.2092764388 | Sep 01 06:24:44 AM UTC 24 | Sep 01 06:24:46 AM UTC 24 | 332117951 ps | ||
| T80 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2154198445 | Sep 01 06:24:42 AM UTC 24 | Sep 01 06:24:47 AM UTC 24 | 567931065 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2988666129 | Sep 01 06:24:42 AM UTC 24 | Sep 01 06:24:47 AM UTC 24 | 354052045 ps | ||
| T114 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3654559794 | Sep 01 06:24:45 AM UTC 24 | Sep 01 06:24:47 AM UTC 24 | 594894479 ps | ||
| T115 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2249299931 | Sep 01 06:24:40 AM UTC 24 | Sep 01 06:24:47 AM UTC 24 | 1205406536 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2725373979 | Sep 01 06:24:42 AM UTC 24 | Sep 01 06:24:47 AM UTC 24 | 2813509811 ps | ||
| T803 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2429368533 | Sep 01 06:24:44 AM UTC 24 | Sep 01 06:24:48 AM UTC 24 | 1184717566 ps | ||
| T81 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2594171600 | Sep 01 06:24:45 AM UTC 24 | Sep 01 06:24:48 AM UTC 24 | 528563348 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.4207360036 | Sep 01 06:24:42 AM UTC 24 | Sep 01 06:24:48 AM UTC 24 | 906809943 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3732848435 | Sep 01 06:24:46 AM UTC 24 | Sep 01 06:24:49 AM UTC 24 | 647978991 ps | ||
| T804 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_intr_test.3159126182 | Sep 01 06:24:46 AM UTC 24 | Sep 01 06:24:49 AM UTC 24 | 482671745 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.823363266 | Sep 01 06:24:46 AM UTC 24 | Sep 01 06:24:49 AM UTC 24 | 1245551756 ps | ||
| T119 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.246269338 | Sep 01 06:24:45 AM UTC 24 | Sep 01 06:24:50 AM UTC 24 | 1157914867 ps | ||
| T82 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3421587525 | Sep 01 06:24:47 AM UTC 24 | Sep 01 06:24:51 AM UTC 24 | 569890977 ps | ||
| T123 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.4125965902 | Sep 01 06:24:47 AM UTC 24 | Sep 01 06:24:51 AM UTC 24 | 2307734196 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_errors.286479505 | Sep 01 06:24:46 AM UTC 24 | Sep 01 06:24:51 AM UTC 24 | 624474199 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3325220674 | Sep 01 06:24:37 AM UTC 24 | Sep 01 06:24:51 AM UTC 24 | 8298034782 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3855258083 | Sep 01 06:24:45 AM UTC 24 | Sep 01 06:24:51 AM UTC 24 | 1906388902 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3418566489 | Sep 01 06:24:49 AM UTC 24 | Sep 01 06:24:52 AM UTC 24 | 512652122 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2453318445 | Sep 01 06:24:49 AM UTC 24 | Sep 01 06:24:52 AM UTC 24 | 537766532 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3737957959 | Sep 01 06:24:44 AM UTC 24 | Sep 01 06:24:52 AM UTC 24 | 4452623751 ps | ||
| T805 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_intr_test.167793986 | Sep 01 06:24:50 AM UTC 24 | Sep 01 06:24:52 AM UTC 24 | 349391386 ps | ||
| T806 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_intr_test.2905764717 | Sep 01 06:24:49 AM UTC 24 | Sep 01 06:24:52 AM UTC 24 | 409517525 ps | ||
| T807 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1344840789 | Sep 01 06:24:50 AM UTC 24 | Sep 01 06:24:52 AM UTC 24 | 353748214 ps | ||
| T808 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.728903590 | Sep 01 06:24:47 AM UTC 24 | Sep 01 06:24:53 AM UTC 24 | 872861795 ps | ||
| T809 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1989072333 | Sep 01 06:24:49 AM UTC 24 | Sep 01 06:24:53 AM UTC 24 | 498681128 ps | ||
| T120 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1464719110 | Sep 01 06:24:50 AM UTC 24 | Sep 01 06:24:53 AM UTC 24 | 543513040 ps | ||
| T810 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_intr_test.3432163423 | Sep 01 06:24:51 AM UTC 24 | Sep 01 06:24:53 AM UTC 24 | 650425645 ps | ||
| T811 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.947700948 | Sep 01 06:24:51 AM UTC 24 | Sep 01 06:24:54 AM UTC 24 | 496897939 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3648763563 | Sep 01 06:24:46 AM UTC 24 | Sep 01 06:24:54 AM UTC 24 | 8638372295 ps | ||
| T352 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1861575837 | Sep 01 06:24:41 AM UTC 24 | Sep 01 06:24:54 AM UTC 24 | 4455485571 ps | ||
| T812 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3814940717 | Sep 01 06:24:51 AM UTC 24 | Sep 01 06:24:54 AM UTC 24 | 406613186 ps | ||
| T813 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_intr_test.3718018812 | Sep 01 06:24:53 AM UTC 24 | Sep 01 06:24:55 AM UTC 24 | 550924618 ps | ||
| T814 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2558886153 | Sep 01 06:24:53 AM UTC 24 | Sep 01 06:24:55 AM UTC 24 | 369842709 ps | ||
| T815 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1588709177 | Sep 01 06:24:53 AM UTC 24 | Sep 01 06:24:55 AM UTC 24 | 471276262 ps | ||
| T816 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_intr_test.3785089831 | Sep 01 06:24:54 AM UTC 24 | Sep 01 06:24:56 AM UTC 24 | 323327726 ps | ||
| T817 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2225301840 | Sep 01 06:24:51 AM UTC 24 | Sep 01 06:24:56 AM UTC 24 | 557588077 ps | ||
| T818 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.390678505 | Sep 01 06:24:50 AM UTC 24 | Sep 01 06:24:56 AM UTC 24 | 5131833596 ps | ||
| T353 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2977645576 | Sep 01 06:24:49 AM UTC 24 | Sep 01 06:24:57 AM UTC 24 | 7914160303 ps | ||
| T354 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3458128222 | Sep 01 06:24:51 AM UTC 24 | Sep 01 06:24:57 AM UTC 24 | 4322703040 ps | ||
| T819 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3177330331 | Sep 01 06:24:54 AM UTC 24 | Sep 01 06:24:57 AM UTC 24 | 526917933 ps | ||
| T820 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2398554224 | Sep 01 06:24:53 AM UTC 24 | Sep 01 06:24:57 AM UTC 24 | 539298486 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4266482249 | Sep 01 06:24:54 AM UTC 24 | Sep 01 06:24:57 AM UTC 24 | 442409944 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.4260596108 | Sep 01 06:24:55 AM UTC 24 | Sep 01 06:24:58 AM UTC 24 | 559693575 ps | ||
| T821 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.179376893 | Sep 01 06:24:55 AM UTC 24 | Sep 01 06:24:58 AM UTC 24 | 534252880 ps | ||
| T822 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1047291600 | Sep 01 06:24:54 AM UTC 24 | Sep 01 06:24:58 AM UTC 24 | 2137567325 ps | ||
| T823 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.4261824869 | Sep 01 06:24:55 AM UTC 24 | Sep 01 06:24:59 AM UTC 24 | 505217210 ps | ||
| T824 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.106452942 | Sep 01 06:24:55 AM UTC 24 | Sep 01 06:24:59 AM UTC 24 | 478616052 ps | ||
| T825 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3484632259 | Sep 01 06:24:54 AM UTC 24 | Sep 01 06:25:00 AM UTC 24 | 607598747 ps | ||
| T826 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2182274248 | Sep 01 06:24:58 AM UTC 24 | Sep 01 06:25:01 AM UTC 24 | 386625218 ps | ||
| T827 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2197446884 | Sep 01 06:24:58 AM UTC 24 | Sep 01 06:25:01 AM UTC 24 | 563770182 ps | ||
| T828 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.1921991171 | Sep 01 06:24:58 AM UTC 24 | Sep 01 06:25:01 AM UTC 24 | 436046303 ps | ||
| T829 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2396428994 | Sep 01 06:24:54 AM UTC 24 | Sep 01 06:25:01 AM UTC 24 | 2272960153 ps | ||
| T830 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2395101696 | Sep 01 06:24:45 AM UTC 24 | Sep 01 06:25:01 AM UTC 24 | 31948879614 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1139831533 | Sep 01 06:24:35 AM UTC 24 | Sep 01 06:25:01 AM UTC 24 | 7916698033 ps | ||
| T831 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3147757375 | Sep 01 06:24:57 AM UTC 24 | Sep 01 06:25:01 AM UTC 24 | 601869932 ps | ||
| T832 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1328005588 | Sep 01 06:24:57 AM UTC 24 | Sep 01 06:25:02 AM UTC 24 | 369799042 ps | ||
| T833 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1537465797 | Sep 01 06:24:49 AM UTC 24 | Sep 01 06:25:02 AM UTC 24 | 4405543823 ps | ||
| T834 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.3566345161 | Sep 01 06:24:58 AM UTC 24 | Sep 01 06:25:02 AM UTC 24 | 385231207 ps | ||
| T835 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1662930977 | Sep 01 06:24:58 AM UTC 24 | Sep 01 06:25:02 AM UTC 24 | 692962263 ps | ||
| T836 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2099336498 | Sep 01 06:24:59 AM UTC 24 | Sep 01 06:25:03 AM UTC 24 | 514511413 ps | ||
| T837 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.275740424 | Sep 01 06:24:58 AM UTC 24 | Sep 01 06:25:03 AM UTC 24 | 546724021 ps | ||
| T838 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.2524666903 | Sep 01 06:25:01 AM UTC 24 | Sep 01 06:25:03 AM UTC 24 | 491226198 ps | ||
| T839 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2284767619 | Sep 01 06:24:40 AM UTC 24 | Sep 01 06:25:03 AM UTC 24 | 4384465738 ps | ||
| T840 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/46.adc_ctrl_intr_test.3145412837 | Sep 01 06:25:14 AM UTC 24 | Sep 01 06:25:17 AM UTC 24 | 527434395 ps | ||
| T841 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3773303032 | Sep 01 06:25:01 AM UTC 24 | Sep 01 06:25:04 AM UTC 24 | 485359418 ps | ||
| T842 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/49.adc_ctrl_intr_test.3028853715 | Sep 01 06:25:15 AM UTC 24 | Sep 01 06:25:19 AM UTC 24 | 401179097 ps | ||
| T843 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1413493458 | Sep 01 06:25:01 AM UTC 24 | Sep 01 06:25:04 AM UTC 24 | 544270091 ps | ||
| T844 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.4254739197 | Sep 01 06:24:59 AM UTC 24 | Sep 01 06:25:04 AM UTC 24 | 602436813 ps | ||
| T845 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.877719423 | Sep 01 06:25:02 AM UTC 24 | Sep 01 06:25:04 AM UTC 24 | 463527099 ps | ||
| T846 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1962404528 | Sep 01 06:25:02 AM UTC 24 | Sep 01 06:25:05 AM UTC 24 | 462160085 ps | ||
| T847 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.1780080225 | Sep 01 06:25:02 AM UTC 24 | Sep 01 06:25:05 AM UTC 24 | 536531474 ps | ||
| T848 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3117456906 | Sep 01 06:25:02 AM UTC 24 | Sep 01 06:25:05 AM UTC 24 | 492346804 ps | ||
| T849 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2660045786 | Sep 01 06:25:02 AM UTC 24 | Sep 01 06:25:06 AM UTC 24 | 877914858 ps | ||
| T850 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1263256018 | Sep 01 06:25:03 AM UTC 24 | Sep 01 06:25:06 AM UTC 24 | 436912377 ps | ||
| T851 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3694704227 | Sep 01 06:24:58 AM UTC 24 | Sep 01 06:25:06 AM UTC 24 | 1904528180 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1227682139 | Sep 01 06:24:55 AM UTC 24 | Sep 01 06:25:07 AM UTC 24 | 8426269448 ps | ||
| T852 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.281990808 | Sep 01 06:25:03 AM UTC 24 | Sep 01 06:25:07 AM UTC 24 | 535411590 ps | ||
| T853 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1207574311 | Sep 01 06:25:02 AM UTC 24 | Sep 01 06:25:07 AM UTC 24 | 322096966 ps | ||
| T854 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.766240013 | Sep 01 06:25:04 AM UTC 24 | Sep 01 06:25:07 AM UTC 24 | 479119175 ps | ||
| T855 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.1665503668 | Sep 01 06:25:05 AM UTC 24 | Sep 01 06:25:07 AM UTC 24 | 507771512 ps | ||
| T856 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3922851909 | Sep 01 06:25:05 AM UTC 24 | Sep 01 06:25:08 AM UTC 24 | 491342074 ps | ||
| T857 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3428202047 | Sep 01 06:25:07 AM UTC 24 | Sep 01 06:25:21 AM UTC 24 | 7993530836 ps | ||
| T858 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.4100232617 | Sep 01 06:25:04 AM UTC 24 | Sep 01 06:25:08 AM UTC 24 | 522071431 ps | ||
| T859 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3888894877 | Sep 01 06:25:09 AM UTC 24 | Sep 01 06:25:17 AM UTC 24 | 2174539536 ps | ||
| T860 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2876669698 | Sep 01 06:25:01 AM UTC 24 | Sep 01 06:25:08 AM UTC 24 | 2367882682 ps | ||
| T861 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2683519472 | Sep 01 06:25:04 AM UTC 24 | Sep 01 06:25:09 AM UTC 24 | 468901792 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2768417755 | Sep 01 06:24:54 AM UTC 24 | Sep 01 06:25:09 AM UTC 24 | 8077139239 ps | ||
| T862 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.872417794 | Sep 01 06:24:52 AM UTC 24 | Sep 01 06:25:09 AM UTC 24 | 4333780516 ps | ||
| T863 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3536811872 | Sep 01 06:25:06 AM UTC 24 | Sep 01 06:25:09 AM UTC 24 | 543742733 ps | ||
| T864 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2016752137 | Sep 01 06:25:06 AM UTC 24 | Sep 01 06:25:09 AM UTC 24 | 487787947 ps | ||
| T865 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3411914769 | Sep 01 06:24:51 AM UTC 24 | Sep 01 06:25:09 AM UTC 24 | 5096022053 ps | ||
| T866 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3185008403 | Sep 01 06:25:05 AM UTC 24 | Sep 01 06:25:10 AM UTC 24 | 479467926 ps | ||
| T867 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.1718292756 | Sep 01 06:25:07 AM UTC 24 | Sep 01 06:25:10 AM UTC 24 | 462660038 ps | ||
| T868 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2245357777 | Sep 01 06:25:07 AM UTC 24 | Sep 01 06:25:10 AM UTC 24 | 523716224 ps | ||
| T869 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1190142506 | Sep 01 06:25:05 AM UTC 24 | Sep 01 06:25:10 AM UTC 24 | 4141306820 ps | ||
| T870 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2555946498 | Sep 01 06:24:57 AM UTC 24 | Sep 01 06:25:10 AM UTC 24 | 5007369944 ps | ||
| T871 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.4284759848 | Sep 01 06:25:06 AM UTC 24 | Sep 01 06:25:10 AM UTC 24 | 2189462629 ps | ||
| T872 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3097339510 | Sep 01 06:25:08 AM UTC 24 | Sep 01 06:25:11 AM UTC 24 | 568554346 ps | ||
| T873 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1940866533 | Sep 01 06:25:06 AM UTC 24 | Sep 01 06:25:11 AM UTC 24 | 572270026 ps | ||
| T874 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1110956375 | Sep 01 06:24:59 AM UTC 24 | Sep 01 06:25:12 AM UTC 24 | 4673432672 ps | ||
| T875 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3892298991 | Sep 01 06:25:02 AM UTC 24 | Sep 01 06:25:12 AM UTC 24 | 4360974748 ps | ||
| T876 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2498399460 | Sep 01 06:25:08 AM UTC 24 | Sep 01 06:25:12 AM UTC 24 | 676349984 ps | ||
| T877 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.1010764018 | Sep 01 06:25:09 AM UTC 24 | Sep 01 06:25:12 AM UTC 24 | 452951267 ps | ||
| T878 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3901058622 | Sep 01 06:25:09 AM UTC 24 | Sep 01 06:25:12 AM UTC 24 | 632559167 ps | ||
| T879 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.4215420479 | Sep 01 06:25:09 AM UTC 24 | Sep 01 06:25:12 AM UTC 24 | 401052330 ps | ||
| T880 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1518136596 | Sep 01 06:25:02 AM UTC 24 | Sep 01 06:25:12 AM UTC 24 | 4151642649 ps | ||
| T881 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.2682347542 | Sep 01 06:25:09 AM UTC 24 | Sep 01 06:25:12 AM UTC 24 | 503392770 ps | ||
| T882 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.2607729583 | Sep 01 06:25:10 AM UTC 24 | Sep 01 06:25:13 AM UTC 24 | 403486972 ps | ||
| T883 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/30.adc_ctrl_intr_test.686502832 | Sep 01 06:25:11 AM UTC 24 | Sep 01 06:25:13 AM UTC 24 | 540435280 ps | ||
| T884 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.1443044108 | Sep 01 06:25:09 AM UTC 24 | Sep 01 06:25:13 AM UTC 24 | 428902058 ps | ||
| T355 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2108369376 | Sep 01 06:24:59 AM UTC 24 | Sep 01 06:25:13 AM UTC 24 | 8679242934 ps | ||
| T885 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1462179229 | Sep 01 06:25:03 AM UTC 24 | Sep 01 06:25:13 AM UTC 24 | 2614503677 ps | ||
| T886 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.2208327500 | Sep 01 06:25:11 AM UTC 24 | Sep 01 06:25:13 AM UTC 24 | 305247100 ps | ||
| T887 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3503979132 | Sep 01 06:25:09 AM UTC 24 | Sep 01 06:25:13 AM UTC 24 | 490295893 ps | ||
| T888 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.926267961 | Sep 01 06:25:08 AM UTC 24 | Sep 01 06:25:13 AM UTC 24 | 4582685348 ps | ||
| T889 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.3708577075 | Sep 01 06:25:10 AM UTC 24 | Sep 01 06:25:13 AM UTC 24 | 373086024 ps | ||
| T890 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.1777850830 | Sep 01 06:25:10 AM UTC 24 | Sep 01 06:25:13 AM UTC 24 | 387301601 ps | ||
| T891 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.3239330671 | Sep 01 06:25:11 AM UTC 24 | Sep 01 06:25:14 AM UTC 24 | 471536938 ps | ||
| T892 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.2856919602 | Sep 01 06:25:10 AM UTC 24 | Sep 01 06:25:14 AM UTC 24 | 369263855 ps | ||
| T893 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.4045604102 | Sep 01 06:25:10 AM UTC 24 | Sep 01 06:25:14 AM UTC 24 | 384550564 ps | ||
| T894 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/31.adc_ctrl_intr_test.1238047299 | Sep 01 06:25:12 AM UTC 24 | Sep 01 06:25:14 AM UTC 24 | 422798451 ps | ||
| T895 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/33.adc_ctrl_intr_test.3917812299 | Sep 01 06:25:12 AM UTC 24 | Sep 01 06:25:14 AM UTC 24 | 295223905 ps | ||
| T896 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/35.adc_ctrl_intr_test.1480731718 | Sep 01 06:25:12 AM UTC 24 | Sep 01 06:25:14 AM UTC 24 | 387013847 ps | ||
| T897 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/36.adc_ctrl_intr_test.883856270 | Sep 01 06:25:12 AM UTC 24 | Sep 01 06:25:15 AM UTC 24 | 542668164 ps | ||
| T898 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.516652359 | Sep 01 06:25:09 AM UTC 24 | Sep 01 06:25:15 AM UTC 24 | 4682781841 ps | ||
| T899 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/32.adc_ctrl_intr_test.1127762045 | Sep 01 06:25:12 AM UTC 24 | Sep 01 06:25:15 AM UTC 24 | 415045345 ps | ||
| T900 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/34.adc_ctrl_intr_test.1445633494 | Sep 01 06:25:12 AM UTC 24 | Sep 01 06:25:15 AM UTC 24 | 482314453 ps | ||
| T901 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/42.adc_ctrl_intr_test.1820718780 | Sep 01 06:25:13 AM UTC 24 | Sep 01 06:25:16 AM UTC 24 | 417741858 ps | ||
| T902 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/37.adc_ctrl_intr_test.2664882294 | Sep 01 06:25:13 AM UTC 24 | Sep 01 06:25:16 AM UTC 24 | 510531534 ps | ||
| T903 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1317509167 | Sep 01 06:24:53 AM UTC 24 | Sep 01 06:25:16 AM UTC 24 | 8216159767 ps | ||
| T904 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/39.adc_ctrl_intr_test.2944039465 | Sep 01 06:25:13 AM UTC 24 | Sep 01 06:25:16 AM UTC 24 | 568913623 ps | ||
| T905 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/40.adc_ctrl_intr_test.227055072 | Sep 01 06:25:13 AM UTC 24 | Sep 01 06:25:16 AM UTC 24 | 454562358 ps | ||
| T906 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/45.adc_ctrl_intr_test.807960284 | Sep 01 06:25:14 AM UTC 24 | Sep 01 06:25:16 AM UTC 24 | 373142494 ps | ||
| T907 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/44.adc_ctrl_intr_test.1367794300 | Sep 01 06:25:13 AM UTC 24 | Sep 01 06:25:16 AM UTC 24 | 495813997 ps | ||
| T908 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/43.adc_ctrl_intr_test.120949943 | Sep 01 06:25:13 AM UTC 24 | Sep 01 06:25:16 AM UTC 24 | 354847818 ps | ||
| T909 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/38.adc_ctrl_intr_test.2554881185 | Sep 01 06:25:13 AM UTC 24 | Sep 01 06:25:16 AM UTC 24 | 480233944 ps | ||
| T910 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/41.adc_ctrl_intr_test.1282809056 | Sep 01 06:25:13 AM UTC 24 | Sep 01 06:25:17 AM UTC 24 | 323577670 ps | ||
| T911 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/47.adc_ctrl_intr_test.1655530423 | Sep 01 06:25:15 AM UTC 24 | Sep 01 06:25:17 AM UTC 24 | 524552996 ps | ||
| T912 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3265061355 | Sep 01 06:25:02 AM UTC 24 | Sep 01 06:25:17 AM UTC 24 | 4338783030 ps | ||
| T913 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3576448959 | Sep 01 06:25:04 AM UTC 24 | Sep 01 06:25:17 AM UTC 24 | 4528633167 ps | ||
| T914 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/48.adc_ctrl_intr_test.3909261868 | Sep 01 06:25:15 AM UTC 24 | Sep 01 06:25:17 AM UTC 24 | 398503496 ps | ||
| T915 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2804610307 | Sep 01 06:24:57 AM UTC 24 | Sep 01 06:25:21 AM UTC 24 | 8137633133 ps | ||
| T916 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3248991993 | Sep 01 06:24:58 AM UTC 24 | Sep 01 06:25:23 AM UTC 24 | 8108800275 ps | ||
| T917 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1160918721 | Sep 01 06:24:39 AM UTC 24 | Sep 01 06:25:38 AM UTC 24 | 48328261322 ps | ||
| T356 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3159372513 | Sep 01 06:25:05 AM UTC 24 | Sep 01 06:25:40 AM UTC 24 | 8631086873 ps | ||
| T918 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3673040612 | Sep 01 06:24:36 AM UTC 24 | Sep 01 06:26:53 AM UTC 24 | 35672253166 ps | ||
| T919 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1598660051 | Sep 01 06:24:42 AM UTC 24 | Sep 01 06:27:01 AM UTC 24 | 30937288718 ps | ||
| T920 | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1379179521 | Sep 01 06:24:47 AM UTC 24 | Sep 01 06:27:23 AM UTC 24 | 53837367632 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2052444428 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 12079796659 ps |
| CPU time | 18.56 seconds |
| Started | Sep 01 07:37:41 AM UTC 24 |
| Finished | Sep 01 07:38:01 AM UTC 24 |
| Peak memory | 221628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2052444428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.adc_ctrl_stress_all_with_rand_reset.2052444428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.412456696 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 197776841953 ps |
| CPU time | 53.47 seconds |
| Started | Sep 01 07:37:49 AM UTC 24 |
| Finished | Sep 01 07:38:44 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412456696 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.412456696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_fsm_reset.713286462 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 105548066984 ps |
| CPU time | 778.23 seconds |
| Started | Sep 01 07:38:33 AM UTC 24 |
| Finished | Sep 01 07:51:39 AM UTC 24 |
| Peak memory | 211776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713286462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.713286462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/2.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.4139502001 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 592355427702 ps |
| CPU time | 545.5 seconds |
| Started | Sep 01 07:37:43 AM UTC 24 |
| Finished | Sep 01 07:46:55 AM UTC 24 |
| Peak memory | 211492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139502001 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gating.4139502001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/1.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt.379148469 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 328675909940 ps |
| CPU time | 105.87 seconds |
| Started | Sep 01 07:37:43 AM UTC 24 |
| Finished | Sep 01 07:39:31 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379148469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.379148469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/1.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3432239133 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 20219015660 ps |
| CPU time | 40.34 seconds |
| Started | Sep 01 07:51:40 AM UTC 24 |
| Finished | Sep 01 07:52:22 AM UTC 24 |
| Peak memory | 221960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3432239133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 9.adc_ctrl_stress_all_with_rand_reset.3432239133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_clock_gating.1804611590 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 518613819342 ps |
| CPU time | 414.4 seconds |
| Started | Sep 01 07:46:58 AM UTC 24 |
| Finished | Sep 01 07:53:58 AM UTC 24 |
| Peak memory | 211492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804611590 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gating.1804611590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/7.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all.1847840448 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 608255522491 ps |
| CPU time | 1278.01 seconds |
| Started | Sep 01 07:40:32 AM UTC 24 |
| Finished | Sep 01 08:02:02 AM UTC 24 |
| Peak memory | 212076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847840448 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.1847840448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all.4214842369 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 687549892594 ps |
| CPU time | 1728.49 seconds |
| Started | Sep 01 07:37:41 AM UTC 24 |
| Finished | Sep 01 08:06:46 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214842369 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.4214842369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_both.3155235606 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 500620781483 ps |
| CPU time | 1446.75 seconds |
| Started | Sep 01 07:37:44 AM UTC 24 |
| Finished | Sep 01 08:02:05 AM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155235606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.3155235606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/1.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_both.242574096 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 518029665222 ps |
| CPU time | 934.25 seconds |
| Started | Sep 01 07:56:58 AM UTC 24 |
| Finished | Sep 01 08:12:42 AM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242574096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.242574096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/12.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.846495827 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 511464526 ps |
| CPU time | 5.77 seconds |
| Started | Sep 01 06:24:37 AM UTC 24 |
| Finished | Sep 01 06:24:44 AM UTC 24 |
| Peak memory | 221392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846495827 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.846495827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/1.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.4075246399 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 7720108714 ps |
| CPU time | 10.13 seconds |
| Started | Sep 01 07:37:41 AM UTC 24 |
| Finished | Sep 01 07:37:53 AM UTC 24 |
| Peak memory | 243556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075246399 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.4075246399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/0.adc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup.3733198291 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 558634224524 ps |
| CPU time | 419.11 seconds |
| Started | Sep 01 07:38:04 AM UTC 24 |
| Finished | Sep 01 07:45:08 AM UTC 24 |
| Peak memory | 211472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733198291 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_wakeup.3733198291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/2.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_fsm_reset.1114294234 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 87743160407 ps |
| CPU time | 467.89 seconds |
| Started | Sep 01 08:10:42 AM UTC 24 |
| Finished | Sep 01 08:18:35 AM UTC 24 |
| Peak memory | 211824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114294234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.1114294234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/20.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt.371489376 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 487058446087 ps |
| CPU time | 450.54 seconds |
| Started | Sep 01 07:38:03 AM UTC 24 |
| Finished | Sep 01 07:45:39 AM UTC 24 |
| Peak memory | 211464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371489376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.371489376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/2.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2927373874 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 196393293645 ps |
| CPU time | 312.89 seconds |
| Started | Sep 01 07:37:41 AM UTC 24 |
| Finished | Sep 01 07:42:57 AM UTC 24 |
| Peak memory | 211684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927373874 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_wakeup_fixed.2927373874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/0.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_clock_gating.1113136773 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 353933199102 ps |
| CPU time | 271.69 seconds |
| Started | Sep 01 07:58:31 AM UTC 24 |
| Finished | Sep 01 08:03:06 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113136773 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gating.1113136773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/13.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.1084885589 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 540402001941 ps |
| CPU time | 1661.75 seconds |
| Started | Sep 01 07:39:46 AM UTC 24 |
| Finished | Sep 01 08:07:46 AM UTC 24 |
| Peak memory | 211504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084885589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.1084885589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/3.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_both.3728231969 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 520923652978 ps |
| CPU time | 1337.52 seconds |
| Started | Sep 01 07:45:40 AM UTC 24 |
| Finished | Sep 01 08:08:10 AM UTC 24 |
| Peak memory | 211540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728231969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3728231969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/6.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_clock_gating.242159448 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 347927084272 ps |
| CPU time | 240.83 seconds |
| Started | Sep 01 08:04:30 AM UTC 24 |
| Finished | Sep 01 08:08:34 AM UTC 24 |
| Peak memory | 211604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242159448 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gating.242159448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/17.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_clock_gating.721901667 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 527532013675 ps |
| CPU time | 1549.75 seconds |
| Started | Sep 01 07:44:14 AM UTC 24 |
| Finished | Sep 01 08:10:18 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721901667 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gating.721901667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/5.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2905463464 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 373082223 ps |
| CPU time | 1.33 seconds |
| Started | Sep 01 06:24:39 AM UTC 24 |
| Finished | Sep 01 06:24:41 AM UTC 24 |
| Peak memory | 210040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905463464 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2905463464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/1.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_clock_gating.4029084465 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 486063937027 ps |
| CPU time | 292.02 seconds |
| Started | Sep 01 08:23:06 AM UTC 24 |
| Finished | Sep 01 08:28:01 AM UTC 24 |
| Peak memory | 211428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029084465 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gating.4029084465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/30.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt.3325546555 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 496595993060 ps |
| CPU time | 367.33 seconds |
| Started | Sep 01 07:52:23 AM UTC 24 |
| Finished | Sep 01 07:58:35 AM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325546555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.3325546555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/10.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_clock_gating.1415176537 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 504088500672 ps |
| CPU time | 249.34 seconds |
| Started | Sep 01 08:12:43 AM UTC 24 |
| Finished | Sep 01 08:16:55 AM UTC 24 |
| Peak memory | 211792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415176537 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gating.1415176537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/22.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_clock_gating.2730897290 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 516262817416 ps |
| CPU time | 226.32 seconds |
| Started | Sep 01 08:01:46 AM UTC 24 |
| Finished | Sep 01 08:05:35 AM UTC 24 |
| Peak memory | 211536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730897290 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gating.2730897290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/15.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_both.310212019 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 449633657717 ps |
| CPU time | 244.23 seconds |
| Started | Sep 01 08:06:39 AM UTC 24 |
| Finished | Sep 01 08:10:46 AM UTC 24 |
| Peak memory | 211684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310212019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.310212019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/18.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_both.1815042427 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 347601881773 ps |
| CPU time | 332.03 seconds |
| Started | Sep 01 07:58:36 AM UTC 24 |
| Finished | Sep 01 08:04:12 AM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815042427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.1815042427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/13.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt.4061563597 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 167270536613 ps |
| CPU time | 473.86 seconds |
| Started | Sep 01 07:37:39 AM UTC 24 |
| Finished | Sep 01 07:45:39 AM UTC 24 |
| Peak memory | 211492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061563597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.4061563597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/0.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_clock_gating.2384250728 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 501165633744 ps |
| CPU time | 79.64 seconds |
| Started | Sep 01 08:09:56 AM UTC 24 |
| Finished | Sep 01 08:11:18 AM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384250728 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gating.2384250728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/20.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1227682139 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 8426269448 ps |
| CPU time | 10.32 seconds |
| Started | Sep 01 06:24:55 AM UTC 24 |
| Finished | Sep 01 06:25:07 AM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227682139 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_intg_err.1227682139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/10.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.2223807139 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 452731845 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 07:37:41 AM UTC 24 |
| Finished | Sep 01 07:37:44 AM UTC 24 |
| Peak memory | 210688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223807139 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2223807139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/0.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1003748988 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 2046533796 ps |
| CPU time | 4.39 seconds |
| Started | Sep 01 06:24:36 AM UTC 24 |
| Finished | Sep 01 06:24:42 AM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003748988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_same_csr_outstanding.1003748988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/0.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_clock_gating.4232748492 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 509273866257 ps |
| CPU time | 547.49 seconds |
| Started | Sep 01 08:39:46 AM UTC 24 |
| Finished | Sep 01 08:49:00 AM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232748492 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gating.4232748492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/41.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled.900590595 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 168809346221 ps |
| CPU time | 120.65 seconds |
| Started | Sep 01 07:37:43 AM UTC 24 |
| Finished | Sep 01 07:39:46 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900590595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.900590595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/1.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3320314165 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 325256473125 ps |
| CPU time | 231.3 seconds |
| Started | Sep 01 07:37:39 AM UTC 24 |
| Finished | Sep 01 07:41:34 AM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320314165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt_fixed.3320314165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/0.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all.412572335 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 347762515254 ps |
| CPU time | 969.14 seconds |
| Started | Sep 01 08:03:51 AM UTC 24 |
| Finished | Sep 01 08:20:10 AM UTC 24 |
| Peak memory | 211420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412572335 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.412572335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/16.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.2590557393 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 351563320481 ps |
| CPU time | 282.47 seconds |
| Started | Sep 01 07:52:28 AM UTC 24 |
| Finished | Sep 01 07:57:15 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590557393 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_wakeup.2590557393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/10.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_wakeup.129734758 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 515020981687 ps |
| CPU time | 411.07 seconds |
| Started | Sep 01 08:22:00 AM UTC 24 |
| Finished | Sep 01 08:28:56 AM UTC 24 |
| Peak memory | 211676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129734758 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_wakeup.129734758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/29.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.4055982431 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 7405826111 ps |
| CPU time | 13.81 seconds |
| Started | Sep 01 07:38:37 AM UTC 24 |
| Finished | Sep 01 07:38:52 AM UTC 24 |
| Peak memory | 221732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4055982431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.adc_ctrl_stress_all_with_rand_reset.4055982431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_both.3575788464 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 493745833362 ps |
| CPU time | 380.76 seconds |
| Started | Sep 01 08:42:10 AM UTC 24 |
| Finished | Sep 01 08:48:35 AM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575788464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3575788464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/43.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_clock_gating.1765870642 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 162405901039 ps |
| CPU time | 635.36 seconds |
| Started | Sep 01 07:37:41 AM UTC 24 |
| Finished | Sep 01 07:48:23 AM UTC 24 |
| Peak memory | 211536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765870642 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gating.1765870642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_both.3173041206 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 335054335163 ps |
| CPU time | 324.02 seconds |
| Started | Sep 01 08:19:55 AM UTC 24 |
| Finished | Sep 01 08:25:23 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173041206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.3173041206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/27.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_clock_gating.1689955570 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 497398270257 ps |
| CPU time | 695.53 seconds |
| Started | Sep 01 08:44:31 AM UTC 24 |
| Finished | Sep 01 08:56:14 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689955570 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gating.1689955570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/44.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup.623281760 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 551080256851 ps |
| CPU time | 1300.28 seconds |
| Started | Sep 01 08:02:55 AM UTC 24 |
| Finished | Sep 01 08:24:47 AM UTC 24 |
| Peak memory | 211544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623281760 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_wakeup.623281760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/16.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_interrupt.1670612608 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 495794755823 ps |
| CPU time | 983.44 seconds |
| Started | Sep 01 08:45:24 AM UTC 24 |
| Finished | Sep 01 09:01:58 AM UTC 24 |
| Peak memory | 211428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670612608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.1670612608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/45.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.3345056921 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 525306616169 ps |
| CPU time | 1475.6 seconds |
| Started | Sep 01 07:56:41 AM UTC 24 |
| Finished | Sep 01 08:21:31 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345056921 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gating.3345056921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/12.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_both.1376329855 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 336401004000 ps |
| CPU time | 1206.2 seconds |
| Started | Sep 01 08:35:47 AM UTC 24 |
| Finished | Sep 01 08:56:05 AM UTC 24 |
| Peak memory | 212592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376329855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.1376329855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/38.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_stress_all.3594553737 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 578378529995 ps |
| CPU time | 1794.8 seconds |
| Started | Sep 01 08:43:08 AM UTC 24 |
| Finished | Sep 01 09:13:20 AM UTC 24 |
| Peak memory | 229264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594553737 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.3594553737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/43.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all.2668301154 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 218744749030 ps |
| CPU time | 302.11 seconds |
| Started | Sep 01 07:55:51 AM UTC 24 |
| Finished | Sep 01 08:00:56 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668301154 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.2668301154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/11.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_both.1462027211 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 167040630909 ps |
| CPU time | 209.23 seconds |
| Started | Sep 01 08:12:47 AM UTC 24 |
| Finished | Sep 01 08:16:19 AM UTC 24 |
| Peak memory | 211680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462027211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1462027211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/22.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_stress_all.1386575964 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 520732429555 ps |
| CPU time | 316.65 seconds |
| Started | Sep 01 08:17:40 AM UTC 24 |
| Finished | Sep 01 08:23:01 AM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386575964 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.1386575964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/25.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_wakeup.284100444 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 423879813997 ps |
| CPU time | 314.54 seconds |
| Started | Sep 01 08:23:03 AM UTC 24 |
| Finished | Sep 01 08:28:21 AM UTC 24 |
| Peak memory | 211484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284100444 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_wakeup.284100444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/30.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.1183952822 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 26836288796 ps |
| CPU time | 16.45 seconds |
| Started | Sep 01 08:30:20 AM UTC 24 |
| Finished | Sep 01 08:30:38 AM UTC 24 |
| Peak memory | 222268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1183952822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 34.adc_ctrl_stress_all_with_rand_reset.1183952822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/34.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup.2649482299 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 459112400864 ps |
| CPU time | 339.66 seconds |
| Started | Sep 01 07:41:35 AM UTC 24 |
| Finished | Sep 01 07:47:19 AM UTC 24 |
| Peak memory | 211612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649482299 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_wakeup.2649482299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/4.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2988666129 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 354052045 ps |
| CPU time | 3.32 seconds |
| Started | Sep 01 06:24:42 AM UTC 24 |
| Finished | Sep 01 06:24:47 AM UTC 24 |
| Peak memory | 221320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988666129 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2988666129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/3.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_fsm_reset.2729042061 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 113246258230 ps |
| CPU time | 920.97 seconds |
| Started | Sep 01 07:53:07 AM UTC 24 |
| Finished | Sep 01 08:08:37 AM UTC 24 |
| Peak memory | 211708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729042061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.2729042061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/10.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup.969551224 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 199049709271 ps |
| CPU time | 712.56 seconds |
| Started | Sep 01 08:00:06 AM UTC 24 |
| Finished | Sep 01 08:12:07 AM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969551224 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_wakeup.969551224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/14.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_clock_gating.3438283360 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 206865272722 ps |
| CPU time | 213.12 seconds |
| Started | Sep 01 08:03:02 AM UTC 24 |
| Finished | Sep 01 08:06:38 AM UTC 24 |
| Peak memory | 211800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438283360 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gating.3438283360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/16.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_both.466857724 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 166199687009 ps |
| CPU time | 385.68 seconds |
| Started | Sep 01 07:47:05 AM UTC 24 |
| Finished | Sep 01 07:53:36 AM UTC 24 |
| Peak memory | 211524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466857724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.466857724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/7.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all.2787370325 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 310759563954 ps |
| CPU time | 1072.6 seconds |
| Started | Sep 01 07:53:23 AM UTC 24 |
| Finished | Sep 01 08:11:25 AM UTC 24 |
| Peak memory | 223912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787370325 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.2787370325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/10.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_both.1921181769 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 325389010561 ps |
| CPU time | 482.05 seconds |
| Started | Sep 01 08:11:47 AM UTC 24 |
| Finished | Sep 01 08:19:54 AM UTC 24 |
| Peak memory | 211668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921181769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.1921181769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/21.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_interrupt.153743362 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 487967208711 ps |
| CPU time | 1431.7 seconds |
| Started | Sep 01 08:40:19 AM UTC 24 |
| Finished | Sep 01 09:04:25 AM UTC 24 |
| Peak memory | 212828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153743362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.153743362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/42.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup.1978303818 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 542300550276 ps |
| CPU time | 1593.24 seconds |
| Started | Sep 01 08:08:01 AM UTC 24 |
| Finished | Sep 01 08:34:49 AM UTC 24 |
| Peak memory | 211860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978303818 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_wakeup.1978303818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/19.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_fsm_reset.4208222630 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 114404598408 ps |
| CPU time | 789.96 seconds |
| Started | Sep 01 08:08:53 AM UTC 24 |
| Finished | Sep 01 08:22:10 AM UTC 24 |
| Peak memory | 211752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208222630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.4208222630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/19.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1218956571 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 12764162991 ps |
| CPU time | 19.54 seconds |
| Started | Sep 01 08:14:39 AM UTC 24 |
| Finished | Sep 01 08:15:00 AM UTC 24 |
| Peak memory | 221724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1218956571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 23.adc_ctrl_stress_all_with_rand_reset.1218956571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/23.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.200863538 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 2422953794 ps |
| CPU time | 7.99 seconds |
| Started | Sep 01 08:17:33 AM UTC 24 |
| Finished | Sep 01 08:17:42 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=200863538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.200863538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/25.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.4140505610 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 4988497318 ps |
| CPU time | 19.29 seconds |
| Started | Sep 01 08:19:01 AM UTC 24 |
| Finished | Sep 01 08:19:22 AM UTC 24 |
| Peak memory | 221672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4140505610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 26.adc_ctrl_stress_all_with_rand_reset.4140505610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/26.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_stress_all.149135313 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 168545507457 ps |
| CPU time | 38.96 seconds |
| Started | Sep 01 08:40:03 AM UTC 24 |
| Finished | Sep 01 08:40:43 AM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149135313 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.149135313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/41.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2108369376 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 8679242934 ps |
| CPU time | 12.36 seconds |
| Started | Sep 01 06:24:59 AM UTC 24 |
| Finished | Sep 01 06:25:13 AM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108369376 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_intg_err.2108369376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/13.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.809130330 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 378371574439 ps |
| CPU time | 598.97 seconds |
| Started | Sep 01 07:52:30 AM UTC 24 |
| Finished | Sep 01 08:02:35 AM UTC 24 |
| Peak memory | 211480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809130330 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gating.809130330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/10.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_fsm_reset.2973254252 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 120044537607 ps |
| CPU time | 633.98 seconds |
| Started | Sep 01 07:57:20 AM UTC 24 |
| Finished | Sep 01 08:08:00 AM UTC 24 |
| Peak memory | 211824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973254252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.2973254252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/12.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_fsm_reset.2611819789 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 110001756281 ps |
| CPU time | 460.68 seconds |
| Started | Sep 01 08:00:43 AM UTC 24 |
| Finished | Sep 01 08:08:28 AM UTC 24 |
| Peak memory | 211776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611819789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.2611819789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/14.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_both.3178847763 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 524523574299 ps |
| CPU time | 821.01 seconds |
| Started | Sep 01 08:05:11 AM UTC 24 |
| Finished | Sep 01 08:19:01 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178847763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.3178847763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/17.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all.108511420 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 162313567666 ps |
| CPU time | 634.83 seconds |
| Started | Sep 01 08:10:47 AM UTC 24 |
| Finished | Sep 01 08:21:27 AM UTC 24 |
| Peak memory | 211680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108511420 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.108511420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/20.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.443407166 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 69749909430 ps |
| CPU time | 348.77 seconds |
| Started | Sep 01 07:40:10 AM UTC 24 |
| Finished | Sep 01 07:46:02 AM UTC 24 |
| Peak memory | 211888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443407166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.443407166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/3.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all.1038497367 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 508563541365 ps |
| CPU time | 476.31 seconds |
| Started | Sep 01 08:23:47 AM UTC 24 |
| Finished | Sep 01 08:31:49 AM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038497367 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all.1038497367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/30.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_wakeup.2341134249 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 556639946404 ps |
| CPU time | 1304.73 seconds |
| Started | Sep 01 08:24:22 AM UTC 24 |
| Finished | Sep 01 08:46:19 AM UTC 24 |
| Peak memory | 212752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341134249 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_wakeup.2341134249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/31.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_stress_all.30012267 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 485129957475 ps |
| CPU time | 329.17 seconds |
| Started | Sep 01 08:27:57 AM UTC 24 |
| Finished | Sep 01 08:33:31 AM UTC 24 |
| Peak memory | 211492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30012267 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all.30012267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/32.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_fsm_reset.1252952133 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 122064004943 ps |
| CPU time | 497.11 seconds |
| Started | Sep 01 08:37:46 AM UTC 24 |
| Finished | Sep 01 08:46:09 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252952133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.1252952133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/39.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_wakeup.3793850160 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 350431024466 ps |
| CPU time | 614.14 seconds |
| Started | Sep 01 08:46:30 AM UTC 24 |
| Finished | Sep 01 08:56:51 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793850160 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_wakeup.3793850160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/46.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.3104254577 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 6967376593 ps |
| CPU time | 32.22 seconds |
| Started | Sep 01 08:47:01 AM UTC 24 |
| Finished | Sep 01 08:47:34 AM UTC 24 |
| Peak memory | 221956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3104254577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 46.adc_ctrl_stress_all_with_rand_reset.3104254577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/46.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.1642301153 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 12291826013 ps |
| CPU time | 14.02 seconds |
| Started | Sep 01 08:52:11 AM UTC 24 |
| Finished | Sep 01 08:52:26 AM UTC 24 |
| Peak memory | 221884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1642301153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 49.adc_ctrl_stress_all_with_rand_reset.1642301153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/49.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2771619515 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1098257483 ps |
| CPU time | 4.57 seconds |
| Started | Sep 01 06:24:36 AM UTC 24 |
| Finished | Sep 01 06:24:42 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771619515 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_aliasing.2771619515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/0.adc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3673040612 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 35672253166 ps |
| CPU time | 134.16 seconds |
| Started | Sep 01 06:24:36 AM UTC 24 |
| Finished | Sep 01 06:26:53 AM UTC 24 |
| Peak memory | 211424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673040612 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_bash.3673040612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/0.adc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2427742278 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 1282586225 ps |
| CPU time | 6.2 seconds |
| Started | Sep 01 06:24:36 AM UTC 24 |
| Finished | Sep 01 06:24:43 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427742278 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_reset.2427742278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/0.adc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1631994785 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 533731286 ps |
| CPU time | 2.34 seconds |
| Started | Sep 01 06:24:37 AM UTC 24 |
| Finished | Sep 01 06:24:41 AM UTC 24 |
| Peak memory | 211200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1631994785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_cs r_mem_rw_with_rand_reset.1631994785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3631520354 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 596106838 ps |
| CPU time | 1.58 seconds |
| Started | Sep 01 06:24:36 AM UTC 24 |
| Finished | Sep 01 06:24:39 AM UTC 24 |
| Peak memory | 210040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631520354 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.3631520354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/0.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.2417476332 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 481140570 ps |
| CPU time | 1.94 seconds |
| Started | Sep 01 06:24:35 AM UTC 24 |
| Finished | Sep 01 06:24:38 AM UTC 24 |
| Peak memory | 210520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417476332 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.2417476332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/0.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2809419815 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 552246853 ps |
| CPU time | 2.07 seconds |
| Started | Sep 01 06:24:35 AM UTC 24 |
| Finished | Sep 01 06:24:38 AM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809419815 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2809419815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/0.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1139831533 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 7916698033 ps |
| CPU time | 25.31 seconds |
| Started | Sep 01 06:24:35 AM UTC 24 |
| Finished | Sep 01 06:25:01 AM UTC 24 |
| Peak memory | 211480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139831533 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_intg_err.1139831533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/0.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2249299931 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1205406536 ps |
| CPU time | 6.71 seconds |
| Started | Sep 01 06:24:40 AM UTC 24 |
| Finished | Sep 01 06:24:47 AM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249299931 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_aliasing.2249299931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/1.adc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1160918721 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 48328261322 ps |
| CPU time | 57.54 seconds |
| Started | Sep 01 06:24:39 AM UTC 24 |
| Finished | Sep 01 06:25:38 AM UTC 24 |
| Peak memory | 211504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160918721 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_bash.1160918721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/1.adc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.4250362991 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 1164894174 ps |
| CPU time | 2.15 seconds |
| Started | Sep 01 06:24:38 AM UTC 24 |
| Finished | Sep 01 06:24:42 AM UTC 24 |
| Peak memory | 211288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250362991 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_reset.4250362991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/1.adc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3937249592 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 546677353 ps |
| CPU time | 3.7 seconds |
| Started | Sep 01 06:24:41 AM UTC 24 |
| Finished | Sep 01 06:24:46 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3937249592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_cs r_mem_rw_with_rand_reset.3937249592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.1431870029 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 519251110 ps |
| CPU time | 1.42 seconds |
| Started | Sep 01 06:24:37 AM UTC 24 |
| Finished | Sep 01 06:24:40 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431870029 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.1431870029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/1.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2284767619 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 4384465738 ps |
| CPU time | 22.48 seconds |
| Started | Sep 01 06:24:40 AM UTC 24 |
| Finished | Sep 01 06:25:03 AM UTC 24 |
| Peak memory | 211428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284767619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_same_csr_outstanding.2284767619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/1.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3325220674 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 8298034782 ps |
| CPU time | 12.53 seconds |
| Started | Sep 01 06:24:37 AM UTC 24 |
| Finished | Sep 01 06:24:51 AM UTC 24 |
| Peak memory | 211616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325220674 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_intg_err.3325220674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/1.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3147757375 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 601869932 ps |
| CPU time | 3.86 seconds |
| Started | Sep 01 06:24:57 AM UTC 24 |
| Finished | Sep 01 06:25:01 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3147757375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_c sr_mem_rw_with_rand_reset.3147757375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.4260596108 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 559693575 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 06:24:55 AM UTC 24 |
| Finished | Sep 01 06:24:58 AM UTC 24 |
| Peak memory | 210040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260596108 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.4260596108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/10.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.179376893 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 534252880 ps |
| CPU time | 1.4 seconds |
| Started | Sep 01 06:24:55 AM UTC 24 |
| Finished | Sep 01 06:24:58 AM UTC 24 |
| Peak memory | 209920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179376893 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.179376893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/10.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2555946498 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 5007369944 ps |
| CPU time | 12.51 seconds |
| Started | Sep 01 06:24:57 AM UTC 24 |
| Finished | Sep 01 06:25:10 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555946498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_same_csr_outstanding.2555946498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/10.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.106452942 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 478616052 ps |
| CPU time | 2.77 seconds |
| Started | Sep 01 06:24:55 AM UTC 24 |
| Finished | Sep 01 06:24:59 AM UTC 24 |
| Peak memory | 211492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106452942 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.106452942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/10.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.275740424 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 546724021 ps |
| CPU time | 3.51 seconds |
| Started | Sep 01 06:24:58 AM UTC 24 |
| Finished | Sep 01 06:25:03 AM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=275740424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_cs r_mem_rw_with_rand_reset.275740424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2182274248 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 386625218 ps |
| CPU time | 1.64 seconds |
| Started | Sep 01 06:24:58 AM UTC 24 |
| Finished | Sep 01 06:25:01 AM UTC 24 |
| Peak memory | 210040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182274248 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.2182274248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/11.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.1921991171 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 436046303 ps |
| CPU time | 2.14 seconds |
| Started | Sep 01 06:24:58 AM UTC 24 |
| Finished | Sep 01 06:25:01 AM UTC 24 |
| Peak memory | 211136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921991171 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.1921991171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/11.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3694704227 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 1904528180 ps |
| CPU time | 7.12 seconds |
| Started | Sep 01 06:24:58 AM UTC 24 |
| Finished | Sep 01 06:25:06 AM UTC 24 |
| Peak memory | 211260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694704227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_same_csr_outstanding.3694704227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/11.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1328005588 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 369799042 ps |
| CPU time | 3.81 seconds |
| Started | Sep 01 06:24:57 AM UTC 24 |
| Finished | Sep 01 06:25:02 AM UTC 24 |
| Peak memory | 227748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328005588 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.1328005588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/11.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2804610307 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 8137633133 ps |
| CPU time | 23.3 seconds |
| Started | Sep 01 06:24:57 AM UTC 24 |
| Finished | Sep 01 06:25:21 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804610307 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_intg_err.2804610307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/11.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2099336498 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 514511413 ps |
| CPU time | 2.08 seconds |
| Started | Sep 01 06:24:59 AM UTC 24 |
| Finished | Sep 01 06:25:03 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2099336498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_c sr_mem_rw_with_rand_reset.2099336498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2197446884 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 563770182 ps |
| CPU time | 1.53 seconds |
| Started | Sep 01 06:24:58 AM UTC 24 |
| Finished | Sep 01 06:25:01 AM UTC 24 |
| Peak memory | 210040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197446884 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.2197446884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/12.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.3566345161 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 385231207 ps |
| CPU time | 2.79 seconds |
| Started | Sep 01 06:24:58 AM UTC 24 |
| Finished | Sep 01 06:25:02 AM UTC 24 |
| Peak memory | 211168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566345161 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3566345161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/12.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1110956375 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 4673432672 ps |
| CPU time | 11.19 seconds |
| Started | Sep 01 06:24:59 AM UTC 24 |
| Finished | Sep 01 06:25:12 AM UTC 24 |
| Peak memory | 211464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110956375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_same_csr_outstanding.1110956375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/12.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1662930977 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 692962263 ps |
| CPU time | 3.08 seconds |
| Started | Sep 01 06:24:58 AM UTC 24 |
| Finished | Sep 01 06:25:02 AM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662930977 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.1662930977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/12.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3248991993 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 8108800275 ps |
| CPU time | 23.71 seconds |
| Started | Sep 01 06:24:58 AM UTC 24 |
| Finished | Sep 01 06:25:23 AM UTC 24 |
| Peak memory | 211484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248991993 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_intg_err.3248991993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/12.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3773303032 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 485359418 ps |
| CPU time | 2.22 seconds |
| Started | Sep 01 06:25:01 AM UTC 24 |
| Finished | Sep 01 06:25:04 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3773303032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_c sr_mem_rw_with_rand_reset.3773303032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1413493458 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 544270091 ps |
| CPU time | 2.33 seconds |
| Started | Sep 01 06:25:01 AM UTC 24 |
| Finished | Sep 01 06:25:04 AM UTC 24 |
| Peak memory | 211196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413493458 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.1413493458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/13.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.2524666903 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 491226198 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 06:25:01 AM UTC 24 |
| Finished | Sep 01 06:25:03 AM UTC 24 |
| Peak memory | 210392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524666903 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.2524666903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/13.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2876669698 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 2367882682 ps |
| CPU time | 6.22 seconds |
| Started | Sep 01 06:25:01 AM UTC 24 |
| Finished | Sep 01 06:25:08 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876669698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_same_csr_outstanding.2876669698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/13.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.4254739197 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 602436813 ps |
| CPU time | 3.82 seconds |
| Started | Sep 01 06:24:59 AM UTC 24 |
| Finished | Sep 01 06:25:04 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254739197 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.4254739197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/13.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3117456906 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 492346804 ps |
| CPU time | 1.65 seconds |
| Started | Sep 01 06:25:02 AM UTC 24 |
| Finished | Sep 01 06:25:05 AM UTC 24 |
| Peak memory | 209864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3117456906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_c sr_mem_rw_with_rand_reset.3117456906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1962404528 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 462160085 ps |
| CPU time | 1.64 seconds |
| Started | Sep 01 06:25:02 AM UTC 24 |
| Finished | Sep 01 06:25:05 AM UTC 24 |
| Peak memory | 210040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962404528 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1962404528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/14.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.1780080225 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 536531474 ps |
| CPU time | 1.73 seconds |
| Started | Sep 01 06:25:02 AM UTC 24 |
| Finished | Sep 01 06:25:05 AM UTC 24 |
| Peak memory | 210096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780080225 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.1780080225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/14.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3892298991 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 4360974748 ps |
| CPU time | 8.5 seconds |
| Started | Sep 01 06:25:02 AM UTC 24 |
| Finished | Sep 01 06:25:12 AM UTC 24 |
| Peak memory | 211716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892298991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_same_csr_outstanding.3892298991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/14.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2660045786 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 877914858 ps |
| CPU time | 3.11 seconds |
| Started | Sep 01 06:25:02 AM UTC 24 |
| Finished | Sep 01 06:25:06 AM UTC 24 |
| Peak memory | 227828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660045786 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2660045786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/14.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3265061355 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 4338783030 ps |
| CPU time | 13.82 seconds |
| Started | Sep 01 06:25:02 AM UTC 24 |
| Finished | Sep 01 06:25:17 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265061355 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_intg_err.3265061355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/14.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.281990808 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 535411590 ps |
| CPU time | 2.45 seconds |
| Started | Sep 01 06:25:03 AM UTC 24 |
| Finished | Sep 01 06:25:07 AM UTC 24 |
| Peak memory | 211200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=281990808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_cs r_mem_rw_with_rand_reset.281990808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1263256018 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 436912377 ps |
| CPU time | 1.73 seconds |
| Started | Sep 01 06:25:03 AM UTC 24 |
| Finished | Sep 01 06:25:06 AM UTC 24 |
| Peak memory | 210040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263256018 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.1263256018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/15.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.877719423 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 463527099 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 06:25:02 AM UTC 24 |
| Finished | Sep 01 06:25:04 AM UTC 24 |
| Peak memory | 210280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877719423 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.877719423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/15.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1462179229 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 2614503677 ps |
| CPU time | 8.59 seconds |
| Started | Sep 01 06:25:03 AM UTC 24 |
| Finished | Sep 01 06:25:13 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462179229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_same_csr_outstanding.1462179229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/15.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1207574311 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 322096966 ps |
| CPU time | 3.69 seconds |
| Started | Sep 01 06:25:02 AM UTC 24 |
| Finished | Sep 01 06:25:07 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207574311 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1207574311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/15.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1518136596 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 4151642649 ps |
| CPU time | 9 seconds |
| Started | Sep 01 06:25:02 AM UTC 24 |
| Finished | Sep 01 06:25:12 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518136596 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_intg_err.1518136596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/15.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3922851909 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 491342074 ps |
| CPU time | 1.69 seconds |
| Started | Sep 01 06:25:05 AM UTC 24 |
| Finished | Sep 01 06:25:08 AM UTC 24 |
| Peak memory | 209984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3922851909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_c sr_mem_rw_with_rand_reset.3922851909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.766240013 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 479119175 ps |
| CPU time | 2.5 seconds |
| Started | Sep 01 06:25:04 AM UTC 24 |
| Finished | Sep 01 06:25:07 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766240013 -assert nopostproc +UVM_TESTNAME=adc_ ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.766240013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/16.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.4100232617 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 522071431 ps |
| CPU time | 3.16 seconds |
| Started | Sep 01 06:25:04 AM UTC 24 |
| Finished | Sep 01 06:25:08 AM UTC 24 |
| Peak memory | 211232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100232617 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.4100232617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/16.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1190142506 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 4141306820 ps |
| CPU time | 4.29 seconds |
| Started | Sep 01 06:25:05 AM UTC 24 |
| Finished | Sep 01 06:25:10 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190142506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_same_csr_outstanding.1190142506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/16.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2683519472 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 468901792 ps |
| CPU time | 4.14 seconds |
| Started | Sep 01 06:25:04 AM UTC 24 |
| Finished | Sep 01 06:25:09 AM UTC 24 |
| Peak memory | 221340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683519472 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2683519472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/16.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3576448959 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 4528633167 ps |
| CPU time | 12.31 seconds |
| Started | Sep 01 06:25:04 AM UTC 24 |
| Finished | Sep 01 06:25:17 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576448959 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_intg_err.3576448959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/16.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3536811872 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 543742733 ps |
| CPU time | 1.78 seconds |
| Started | Sep 01 06:25:06 AM UTC 24 |
| Finished | Sep 01 06:25:09 AM UTC 24 |
| Peak memory | 220384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3536811872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_c sr_mem_rw_with_rand_reset.3536811872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2016752137 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 487787947 ps |
| CPU time | 2.06 seconds |
| Started | Sep 01 06:25:06 AM UTC 24 |
| Finished | Sep 01 06:25:09 AM UTC 24 |
| Peak memory | 211200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016752137 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2016752137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/17.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.1665503668 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 507771512 ps |
| CPU time | 1.37 seconds |
| Started | Sep 01 06:25:05 AM UTC 24 |
| Finished | Sep 01 06:25:07 AM UTC 24 |
| Peak memory | 209916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665503668 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.1665503668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/17.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.4284759848 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 2189462629 ps |
| CPU time | 3.04 seconds |
| Started | Sep 01 06:25:06 AM UTC 24 |
| Finished | Sep 01 06:25:10 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284759848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_same_csr_outstanding.4284759848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/17.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3185008403 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 479467926 ps |
| CPU time | 3.59 seconds |
| Started | Sep 01 06:25:05 AM UTC 24 |
| Finished | Sep 01 06:25:10 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185008403 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.3185008403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/17.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3159372513 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 8631086873 ps |
| CPU time | 33.63 seconds |
| Started | Sep 01 06:25:05 AM UTC 24 |
| Finished | Sep 01 06:25:40 AM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159372513 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_intg_err.3159372513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/17.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3097339510 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 568554346 ps |
| CPU time | 1.8 seconds |
| Started | Sep 01 06:25:08 AM UTC 24 |
| Finished | Sep 01 06:25:11 AM UTC 24 |
| Peak memory | 210164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3097339510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_c sr_mem_rw_with_rand_reset.3097339510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2245357777 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 523716224 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 06:25:07 AM UTC 24 |
| Finished | Sep 01 06:25:10 AM UTC 24 |
| Peak memory | 210040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245357777 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.2245357777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/18.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.1718292756 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 462660038 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 06:25:07 AM UTC 24 |
| Finished | Sep 01 06:25:10 AM UTC 24 |
| Peak memory | 210096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718292756 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.1718292756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/18.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.926267961 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 4582685348 ps |
| CPU time | 4.54 seconds |
| Started | Sep 01 06:25:08 AM UTC 24 |
| Finished | Sep 01 06:25:13 AM UTC 24 |
| Peak memory | 211504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926267961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_same_csr_outstanding.926267961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/18.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1940866533 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 572270026 ps |
| CPU time | 3.25 seconds |
| Started | Sep 01 06:25:06 AM UTC 24 |
| Finished | Sep 01 06:25:11 AM UTC 24 |
| Peak memory | 221368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940866533 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1940866533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/18.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3428202047 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 7993530836 ps |
| CPU time | 12.16 seconds |
| Started | Sep 01 06:25:07 AM UTC 24 |
| Finished | Sep 01 06:25:21 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428202047 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_intg_err.3428202047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/18.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3901058622 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 632559167 ps |
| CPU time | 1.94 seconds |
| Started | Sep 01 06:25:09 AM UTC 24 |
| Finished | Sep 01 06:25:12 AM UTC 24 |
| Peak memory | 210988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3901058622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_c sr_mem_rw_with_rand_reset.3901058622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3503979132 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 490295893 ps |
| CPU time | 2.9 seconds |
| Started | Sep 01 06:25:09 AM UTC 24 |
| Finished | Sep 01 06:25:13 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503979132 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3503979132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/19.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.1010764018 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 452951267 ps |
| CPU time | 2.05 seconds |
| Started | Sep 01 06:25:09 AM UTC 24 |
| Finished | Sep 01 06:25:12 AM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010764018 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1010764018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/19.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3888894877 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 2174539536 ps |
| CPU time | 6.7 seconds |
| Started | Sep 01 06:25:09 AM UTC 24 |
| Finished | Sep 01 06:25:17 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888894877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_same_csr_outstanding.3888894877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/19.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2498399460 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 676349984 ps |
| CPU time | 3.41 seconds |
| Started | Sep 01 06:25:08 AM UTC 24 |
| Finished | Sep 01 06:25:12 AM UTC 24 |
| Peak memory | 211388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498399460 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2498399460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/19.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.516652359 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 4682781841 ps |
| CPU time | 4.45 seconds |
| Started | Sep 01 06:25:09 AM UTC 24 |
| Finished | Sep 01 06:25:15 AM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516652359 -assert nopostproc +UVM_TEST NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_intg_err.516652359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/19.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.4207360036 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 906809943 ps |
| CPU time | 5.12 seconds |
| Started | Sep 01 06:24:42 AM UTC 24 |
| Finished | Sep 01 06:24:48 AM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207360036 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_aliasing.4207360036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/2.adc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1598660051 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 30937288718 ps |
| CPU time | 136.57 seconds |
| Started | Sep 01 06:24:42 AM UTC 24 |
| Finished | Sep 01 06:27:01 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598660051 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_bash.1598660051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/2.adc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1174886651 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 1281867577 ps |
| CPU time | 2.41 seconds |
| Started | Sep 01 06:24:41 AM UTC 24 |
| Finished | Sep 01 06:24:45 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174886651 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_reset.1174886651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/2.adc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2154198445 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 567931065 ps |
| CPU time | 3.24 seconds |
| Started | Sep 01 06:24:42 AM UTC 24 |
| Finished | Sep 01 06:24:47 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2154198445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_cs r_mem_rw_with_rand_reset.2154198445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1831717786 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 384106638 ps |
| CPU time | 1.57 seconds |
| Started | Sep 01 06:24:42 AM UTC 24 |
| Finished | Sep 01 06:24:45 AM UTC 24 |
| Peak memory | 210040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831717786 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1831717786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/2.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.2025502524 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 481722173 ps |
| CPU time | 2.24 seconds |
| Started | Sep 01 06:24:41 AM UTC 24 |
| Finished | Sep 01 06:24:44 AM UTC 24 |
| Peak memory | 211180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025502524 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2025502524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/2.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2725373979 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 2813509811 ps |
| CPU time | 4.02 seconds |
| Started | Sep 01 06:24:42 AM UTC 24 |
| Finished | Sep 01 06:24:47 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725373979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_same_csr_outstanding.2725373979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/2.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3630829104 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 526044285 ps |
| CPU time | 2.62 seconds |
| Started | Sep 01 06:24:41 AM UTC 24 |
| Finished | Sep 01 06:24:44 AM UTC 24 |
| Peak memory | 211524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630829104 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.3630829104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/2.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1861575837 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 4455485571 ps |
| CPU time | 12.1 seconds |
| Started | Sep 01 06:24:41 AM UTC 24 |
| Finished | Sep 01 06:24:54 AM UTC 24 |
| Peak memory | 211480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861575837 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_intg_err.1861575837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/2.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.2682347542 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 503392770 ps |
| CPU time | 2.04 seconds |
| Started | Sep 01 06:25:09 AM UTC 24 |
| Finished | Sep 01 06:25:12 AM UTC 24 |
| Peak memory | 211136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682347542 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2682347542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/20.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.1443044108 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 428902058 ps |
| CPU time | 2.3 seconds |
| Started | Sep 01 06:25:09 AM UTC 24 |
| Finished | Sep 01 06:25:13 AM UTC 24 |
| Peak memory | 210792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443044108 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.1443044108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/21.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.4215420479 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 401052330 ps |
| CPU time | 1.91 seconds |
| Started | Sep 01 06:25:09 AM UTC 24 |
| Finished | Sep 01 06:25:12 AM UTC 24 |
| Peak memory | 209976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215420479 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.4215420479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/22.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.1777850830 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 387301601 ps |
| CPU time | 2.12 seconds |
| Started | Sep 01 06:25:10 AM UTC 24 |
| Finished | Sep 01 06:25:13 AM UTC 24 |
| Peak memory | 211228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777850830 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.1777850830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/23.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.3708577075 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 373086024 ps |
| CPU time | 2.07 seconds |
| Started | Sep 01 06:25:10 AM UTC 24 |
| Finished | Sep 01 06:25:13 AM UTC 24 |
| Peak memory | 211232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708577075 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.3708577075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/24.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.2607729583 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 403486972 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 06:25:10 AM UTC 24 |
| Finished | Sep 01 06:25:13 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607729583 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.2607729583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/25.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.4045604102 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 384550564 ps |
| CPU time | 2.35 seconds |
| Started | Sep 01 06:25:10 AM UTC 24 |
| Finished | Sep 01 06:25:14 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045604102 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.4045604102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/26.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.2856919602 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 369263855 ps |
| CPU time | 2.2 seconds |
| Started | Sep 01 06:25:10 AM UTC 24 |
| Finished | Sep 01 06:25:14 AM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856919602 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2856919602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/27.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.3239330671 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 471536938 ps |
| CPU time | 2.1 seconds |
| Started | Sep 01 06:25:11 AM UTC 24 |
| Finished | Sep 01 06:25:14 AM UTC 24 |
| Peak memory | 211092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239330671 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.3239330671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/28.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.2208327500 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 305247100 ps |
| CPU time | 1.53 seconds |
| Started | Sep 01 06:25:11 AM UTC 24 |
| Finished | Sep 01 06:25:13 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208327500 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.2208327500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/29.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.246269338 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 1157914867 ps |
| CPU time | 4.18 seconds |
| Started | Sep 01 06:24:45 AM UTC 24 |
| Finished | Sep 01 06:24:50 AM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246269338 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_aliasing.246269338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/3.adc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2395101696 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 31948879614 ps |
| CPU time | 15.33 seconds |
| Started | Sep 01 06:24:45 AM UTC 24 |
| Finished | Sep 01 06:25:01 AM UTC 24 |
| Peak memory | 211424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395101696 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_bash.2395101696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/3.adc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2429368533 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 1184717566 ps |
| CPU time | 3.18 seconds |
| Started | Sep 01 06:24:44 AM UTC 24 |
| Finished | Sep 01 06:24:48 AM UTC 24 |
| Peak memory | 211224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429368533 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_reset.2429368533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/3.adc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2594171600 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 528563348 ps |
| CPU time | 1.91 seconds |
| Started | Sep 01 06:24:45 AM UTC 24 |
| Finished | Sep 01 06:24:48 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2594171600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_cs r_mem_rw_with_rand_reset.2594171600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3654559794 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 594894479 ps |
| CPU time | 1.54 seconds |
| Started | Sep 01 06:24:45 AM UTC 24 |
| Finished | Sep 01 06:24:47 AM UTC 24 |
| Peak memory | 210040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654559794 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3654559794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/3.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.2092764388 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 332117951 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 06:24:44 AM UTC 24 |
| Finished | Sep 01 06:24:46 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092764388 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2092764388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/3.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3855258083 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1906388902 ps |
| CPU time | 5.51 seconds |
| Started | Sep 01 06:24:45 AM UTC 24 |
| Finished | Sep 01 06:24:51 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855258083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_same_csr_outstanding.3855258083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/3.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3737957959 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 4452623751 ps |
| CPU time | 7.59 seconds |
| Started | Sep 01 06:24:44 AM UTC 24 |
| Finished | Sep 01 06:24:52 AM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737957959 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_intg_err.3737957959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/3.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/30.adc_ctrl_intr_test.686502832 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 540435280 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 06:25:11 AM UTC 24 |
| Finished | Sep 01 06:25:13 AM UTC 24 |
| Peak memory | 210280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686502832 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.686502832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/30.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/31.adc_ctrl_intr_test.1238047299 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 422798451 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 06:25:12 AM UTC 24 |
| Finished | Sep 01 06:25:14 AM UTC 24 |
| Peak memory | 210096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238047299 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1238047299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/31.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/32.adc_ctrl_intr_test.1127762045 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 415045345 ps |
| CPU time | 1.71 seconds |
| Started | Sep 01 06:25:12 AM UTC 24 |
| Finished | Sep 01 06:25:15 AM UTC 24 |
| Peak memory | 209976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127762045 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1127762045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/32.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/33.adc_ctrl_intr_test.3917812299 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 295223905 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 06:25:12 AM UTC 24 |
| Finished | Sep 01 06:25:14 AM UTC 24 |
| Peak memory | 209916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917812299 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.3917812299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/33.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/34.adc_ctrl_intr_test.1445633494 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 482314453 ps |
| CPU time | 1.83 seconds |
| Started | Sep 01 06:25:12 AM UTC 24 |
| Finished | Sep 01 06:25:15 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445633494 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.1445633494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/34.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/35.adc_ctrl_intr_test.1480731718 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 387013847 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 06:25:12 AM UTC 24 |
| Finished | Sep 01 06:25:14 AM UTC 24 |
| Peak memory | 209976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480731718 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1480731718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/35.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/36.adc_ctrl_intr_test.883856270 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 542668164 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 06:25:12 AM UTC 24 |
| Finished | Sep 01 06:25:15 AM UTC 24 |
| Peak memory | 210280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883856270 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.883856270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/36.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/37.adc_ctrl_intr_test.2664882294 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 510531534 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 06:25:13 AM UTC 24 |
| Finished | Sep 01 06:25:16 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664882294 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.2664882294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/37.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/38.adc_ctrl_intr_test.2554881185 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 480233944 ps |
| CPU time | 1.63 seconds |
| Started | Sep 01 06:25:13 AM UTC 24 |
| Finished | Sep 01 06:25:16 AM UTC 24 |
| Peak memory | 210392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554881185 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.2554881185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/38.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/39.adc_ctrl_intr_test.2944039465 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 568913623 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 06:25:13 AM UTC 24 |
| Finished | Sep 01 06:25:16 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944039465 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.2944039465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/39.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.728903590 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 872861795 ps |
| CPU time | 4.64 seconds |
| Started | Sep 01 06:24:47 AM UTC 24 |
| Finished | Sep 01 06:24:53 AM UTC 24 |
| Peak memory | 211232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728903590 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_aliasing.728903590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/4.adc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1379179521 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 53837367632 ps |
| CPU time | 152.56 seconds |
| Started | Sep 01 06:24:47 AM UTC 24 |
| Finished | Sep 01 06:27:23 AM UTC 24 |
| Peak memory | 211492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379179521 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_bash.1379179521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/4.adc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.823363266 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1245551756 ps |
| CPU time | 1.68 seconds |
| Started | Sep 01 06:24:46 AM UTC 24 |
| Finished | Sep 01 06:24:49 AM UTC 24 |
| Peak memory | 210040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823363266 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_reset.823363266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/4.adc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3421587525 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 569890977 ps |
| CPU time | 2.13 seconds |
| Started | Sep 01 06:24:47 AM UTC 24 |
| Finished | Sep 01 06:24:51 AM UTC 24 |
| Peak memory | 211268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3421587525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_cs r_mem_rw_with_rand_reset.3421587525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3732848435 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 647978991 ps |
| CPU time | 1.36 seconds |
| Started | Sep 01 06:24:46 AM UTC 24 |
| Finished | Sep 01 06:24:49 AM UTC 24 |
| Peak memory | 210040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732848435 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3732848435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/4.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_intr_test.3159126182 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 482671745 ps |
| CPU time | 1.45 seconds |
| Started | Sep 01 06:24:46 AM UTC 24 |
| Finished | Sep 01 06:24:49 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159126182 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3159126182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/4.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.4125965902 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 2307734196 ps |
| CPU time | 2.42 seconds |
| Started | Sep 01 06:24:47 AM UTC 24 |
| Finished | Sep 01 06:24:51 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125965902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_same_csr_outstanding.4125965902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/4.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_errors.286479505 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 624474199 ps |
| CPU time | 3.69 seconds |
| Started | Sep 01 06:24:46 AM UTC 24 |
| Finished | Sep 01 06:24:51 AM UTC 24 |
| Peak memory | 227484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286479505 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.286479505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/4.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3648763563 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 8638372295 ps |
| CPU time | 6.67 seconds |
| Started | Sep 01 06:24:46 AM UTC 24 |
| Finished | Sep 01 06:24:54 AM UTC 24 |
| Peak memory | 211504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648763563 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_intg_err.3648763563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/4.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/40.adc_ctrl_intr_test.227055072 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 454562358 ps |
| CPU time | 1.21 seconds |
| Started | Sep 01 06:25:13 AM UTC 24 |
| Finished | Sep 01 06:25:16 AM UTC 24 |
| Peak memory | 210280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227055072 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.227055072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/40.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/41.adc_ctrl_intr_test.1282809056 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 323577670 ps |
| CPU time | 1.76 seconds |
| Started | Sep 01 06:25:13 AM UTC 24 |
| Finished | Sep 01 06:25:17 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282809056 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.1282809056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/41.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/42.adc_ctrl_intr_test.1820718780 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 417741858 ps |
| CPU time | 0.85 seconds |
| Started | Sep 01 06:25:13 AM UTC 24 |
| Finished | Sep 01 06:25:16 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820718780 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1820718780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/42.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/43.adc_ctrl_intr_test.120949943 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 354847818 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 06:25:13 AM UTC 24 |
| Finished | Sep 01 06:25:16 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120949943 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.120949943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/43.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/44.adc_ctrl_intr_test.1367794300 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 495813997 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 06:25:13 AM UTC 24 |
| Finished | Sep 01 06:25:16 AM UTC 24 |
| Peak memory | 210392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367794300 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.1367794300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/44.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/45.adc_ctrl_intr_test.807960284 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 373142494 ps |
| CPU time | 0.96 seconds |
| Started | Sep 01 06:25:14 AM UTC 24 |
| Finished | Sep 01 06:25:16 AM UTC 24 |
| Peak memory | 210240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807960284 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.807960284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/45.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/46.adc_ctrl_intr_test.3145412837 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 527434395 ps |
| CPU time | 1.84 seconds |
| Started | Sep 01 06:25:14 AM UTC 24 |
| Finished | Sep 01 06:25:17 AM UTC 24 |
| Peak memory | 209976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145412837 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.3145412837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/46.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/47.adc_ctrl_intr_test.1655530423 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 524552996 ps |
| CPU time | 0.84 seconds |
| Started | Sep 01 06:25:15 AM UTC 24 |
| Finished | Sep 01 06:25:17 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655530423 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.1655530423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/47.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/48.adc_ctrl_intr_test.3909261868 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 398503496 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 06:25:15 AM UTC 24 |
| Finished | Sep 01 06:25:17 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909261868 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.3909261868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/48.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/49.adc_ctrl_intr_test.3028853715 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 401179097 ps |
| CPU time | 2.76 seconds |
| Started | Sep 01 06:25:15 AM UTC 24 |
| Finished | Sep 01 06:25:19 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028853715 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.3028853715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/49.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1989072333 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 498681128 ps |
| CPU time | 3.36 seconds |
| Started | Sep 01 06:24:49 AM UTC 24 |
| Finished | Sep 01 06:24:53 AM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1989072333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_cs r_mem_rw_with_rand_reset.1989072333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2453318445 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 537766532 ps |
| CPU time | 2.07 seconds |
| Started | Sep 01 06:24:49 AM UTC 24 |
| Finished | Sep 01 06:24:52 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453318445 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.2453318445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/5.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_intr_test.2905764717 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 409517525 ps |
| CPU time | 2.67 seconds |
| Started | Sep 01 06:24:49 AM UTC 24 |
| Finished | Sep 01 06:24:52 AM UTC 24 |
| Peak memory | 211180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905764717 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.2905764717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/5.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1537465797 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 4405543823 ps |
| CPU time | 11.75 seconds |
| Started | Sep 01 06:24:49 AM UTC 24 |
| Finished | Sep 01 06:25:02 AM UTC 24 |
| Peak memory | 211648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537465797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_same_csr_outstanding.1537465797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/5.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3418566489 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 512652122 ps |
| CPU time | 2.08 seconds |
| Started | Sep 01 06:24:49 AM UTC 24 |
| Finished | Sep 01 06:24:52 AM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418566489 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3418566489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/5.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2977645576 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 7914160303 ps |
| CPU time | 6.95 seconds |
| Started | Sep 01 06:24:49 AM UTC 24 |
| Finished | Sep 01 06:24:57 AM UTC 24 |
| Peak memory | 211420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977645576 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_intg_err.2977645576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/5.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.947700948 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 496897939 ps |
| CPU time | 1.52 seconds |
| Started | Sep 01 06:24:51 AM UTC 24 |
| Finished | Sep 01 06:24:54 AM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=947700948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr _mem_rw_with_rand_reset.947700948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1464719110 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 543513040 ps |
| CPU time | 2.16 seconds |
| Started | Sep 01 06:24:50 AM UTC 24 |
| Finished | Sep 01 06:24:53 AM UTC 24 |
| Peak memory | 211272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464719110 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.1464719110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/6.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_intr_test.167793986 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 349391386 ps |
| CPU time | 1.3 seconds |
| Started | Sep 01 06:24:50 AM UTC 24 |
| Finished | Sep 01 06:24:52 AM UTC 24 |
| Peak memory | 209916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167793986 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.167793986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/6.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3411914769 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 5096022053 ps |
| CPU time | 16.91 seconds |
| Started | Sep 01 06:24:51 AM UTC 24 |
| Finished | Sep 01 06:25:09 AM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411914769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_same_csr_outstanding.3411914769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/6.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1344840789 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 353748214 ps |
| CPU time | 1.54 seconds |
| Started | Sep 01 06:24:50 AM UTC 24 |
| Finished | Sep 01 06:24:52 AM UTC 24 |
| Peak memory | 210336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344840789 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.1344840789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/6.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.390678505 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 5131833596 ps |
| CPU time | 5.42 seconds |
| Started | Sep 01 06:24:50 AM UTC 24 |
| Finished | Sep 01 06:24:56 AM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390678505 -assert nopostproc +UVM_TEST NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_intg_err.390678505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/6.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1588709177 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 471276262 ps |
| CPU time | 1.61 seconds |
| Started | Sep 01 06:24:53 AM UTC 24 |
| Finished | Sep 01 06:24:55 AM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1588709177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_cs r_mem_rw_with_rand_reset.1588709177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3814940717 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 406613186 ps |
| CPU time | 1.94 seconds |
| Started | Sep 01 06:24:51 AM UTC 24 |
| Finished | Sep 01 06:24:54 AM UTC 24 |
| Peak memory | 210040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814940717 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.3814940717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/7.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_intr_test.3432163423 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 650425645 ps |
| CPU time | 1.02 seconds |
| Started | Sep 01 06:24:51 AM UTC 24 |
| Finished | Sep 01 06:24:53 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432163423 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.3432163423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/7.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.872417794 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 4333780516 ps |
| CPU time | 15.13 seconds |
| Started | Sep 01 06:24:52 AM UTC 24 |
| Finished | Sep 01 06:25:09 AM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872417794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_same_csr_outstanding.872417794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/7.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2225301840 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 557588077 ps |
| CPU time | 3.97 seconds |
| Started | Sep 01 06:24:51 AM UTC 24 |
| Finished | Sep 01 06:24:56 AM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225301840 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2225301840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/7.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3458128222 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 4322703040 ps |
| CPU time | 4.35 seconds |
| Started | Sep 01 06:24:51 AM UTC 24 |
| Finished | Sep 01 06:24:57 AM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458128222 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_intg_err.3458128222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/7.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3177330331 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 526917933 ps |
| CPU time | 2.49 seconds |
| Started | Sep 01 06:24:54 AM UTC 24 |
| Finished | Sep 01 06:24:57 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3177330331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_cs r_mem_rw_with_rand_reset.3177330331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2558886153 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 369842709 ps |
| CPU time | 1.32 seconds |
| Started | Sep 01 06:24:53 AM UTC 24 |
| Finished | Sep 01 06:24:55 AM UTC 24 |
| Peak memory | 210040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558886153 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.2558886153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/8.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_intr_test.3718018812 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 550924618 ps |
| CPU time | 1.07 seconds |
| Started | Sep 01 06:24:53 AM UTC 24 |
| Finished | Sep 01 06:24:55 AM UTC 24 |
| Peak memory | 210392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718018812 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.3718018812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/8.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1047291600 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 2137567325 ps |
| CPU time | 2.95 seconds |
| Started | Sep 01 06:24:54 AM UTC 24 |
| Finished | Sep 01 06:24:58 AM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047291600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_same_csr_outstanding.1047291600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/8.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2398554224 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 539298486 ps |
| CPU time | 3.97 seconds |
| Started | Sep 01 06:24:53 AM UTC 24 |
| Finished | Sep 01 06:24:57 AM UTC 24 |
| Peak memory | 211332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398554224 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2398554224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/8.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1317509167 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 8216159767 ps |
| CPU time | 22.03 seconds |
| Started | Sep 01 06:24:53 AM UTC 24 |
| Finished | Sep 01 06:25:16 AM UTC 24 |
| Peak memory | 211420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317509167 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_intg_err.1317509167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/8.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.4261824869 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 505217210 ps |
| CPU time | 2.49 seconds |
| Started | Sep 01 06:24:55 AM UTC 24 |
| Finished | Sep 01 06:24:59 AM UTC 24 |
| Peak memory | 211272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4261824869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_cs r_mem_rw_with_rand_reset.4261824869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4266482249 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 442409944 ps |
| CPU time | 2.36 seconds |
| Started | Sep 01 06:24:54 AM UTC 24 |
| Finished | Sep 01 06:24:57 AM UTC 24 |
| Peak memory | 211200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266482249 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.4266482249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/9.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_intr_test.3785089831 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 323327726 ps |
| CPU time | 1.03 seconds |
| Started | Sep 01 06:24:54 AM UTC 24 |
| Finished | Sep 01 06:24:56 AM UTC 24 |
| Peak memory | 210036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785089831 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.3785089831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/9.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2396428994 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 2272960153 ps |
| CPU time | 6.03 seconds |
| Started | Sep 01 06:24:54 AM UTC 24 |
| Finished | Sep 01 06:25:01 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396428994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_same_csr_outstanding.2396428994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/9.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3484632259 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 607598747 ps |
| CPU time | 5.12 seconds |
| Started | Sep 01 06:24:54 AM UTC 24 |
| Finished | Sep 01 06:25:00 AM UTC 24 |
| Peak memory | 211432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484632259 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.3484632259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/9.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2768417755 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 8077139239 ps |
| CPU time | 13.62 seconds |
| Started | Sep 01 06:24:54 AM UTC 24 |
| Finished | Sep 01 06:25:09 AM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768417755 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_intg_err.2768417755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/9.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_both.1210997094 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 435358754202 ps |
| CPU time | 331.81 seconds |
| Started | Sep 01 07:37:41 AM UTC 24 |
| Finished | Sep 01 07:43:17 AM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210997094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.1210997094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/0.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled.2025826691 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 500079179812 ps |
| CPU time | 536.76 seconds |
| Started | Sep 01 07:37:39 AM UTC 24 |
| Finished | Sep 01 07:46:42 AM UTC 24 |
| Peak memory | 211424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025826691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2025826691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/0.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled_fixed.1254070190 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 166112557330 ps |
| CPU time | 446.85 seconds |
| Started | Sep 01 07:37:39 AM UTC 24 |
| Finished | Sep 01 07:45:12 AM UTC 24 |
| Peak memory | 211680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254070190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixed.1254070190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/0.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup.2927479630 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 190739251388 ps |
| CPU time | 562.49 seconds |
| Started | Sep 01 07:37:39 AM UTC 24 |
| Finished | Sep 01 07:47:08 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927479630 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_wakeup.2927479630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/0.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_fsm_reset.2855246962 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 78172189417 ps |
| CPU time | 470.04 seconds |
| Started | Sep 01 07:37:41 AM UTC 24 |
| Finished | Sep 01 07:45:37 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855246962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.2855246962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/0.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_lowpower_counter.4213034562 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 29754536217 ps |
| CPU time | 19.37 seconds |
| Started | Sep 01 07:37:41 AM UTC 24 |
| Finished | Sep 01 07:38:02 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213034562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.4213034562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/0.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_poweron_counter.3029991871 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 3871506609 ps |
| CPU time | 5.47 seconds |
| Started | Sep 01 07:37:41 AM UTC 24 |
| Finished | Sep 01 07:37:48 AM UTC 24 |
| Peak memory | 211228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029991871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.3029991871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/0.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_smoke.2042742267 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 6041123954 ps |
| CPU time | 6.83 seconds |
| Started | Sep 01 07:37:39 AM UTC 24 |
| Finished | Sep 01 07:37:47 AM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042742267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.2042742267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/0.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_alert_test.1475926118 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 443755081 ps |
| CPU time | 1.16 seconds |
| Started | Sep 01 07:37:54 AM UTC 24 |
| Finished | Sep 01 07:37:56 AM UTC 24 |
| Peak memory | 209796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475926118 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.1475926118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/1.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2642561757 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 325607257901 ps |
| CPU time | 1188.78 seconds |
| Started | Sep 01 07:37:43 AM UTC 24 |
| Finished | Sep 01 07:57:44 AM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642561757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt_fixed.2642561757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/1.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled_fixed.2108715494 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 327642937387 ps |
| CPU time | 1185.07 seconds |
| Started | Sep 01 07:37:43 AM UTC 24 |
| Finished | Sep 01 07:57:40 AM UTC 24 |
| Peak memory | 211428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108715494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixed.2108715494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/1.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup.2261426567 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 174831201474 ps |
| CPU time | 130 seconds |
| Started | Sep 01 07:37:43 AM UTC 24 |
| Finished | Sep 01 07:39:55 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261426567 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_wakeup.2261426567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/1.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup_fixed.869225890 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 405581893654 ps |
| CPU time | 147.99 seconds |
| Started | Sep 01 07:37:43 AM UTC 24 |
| Finished | Sep 01 07:40:13 AM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869225890 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_wakeup_fixed.869225890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/1.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_fsm_reset.3938930073 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 94386993616 ps |
| CPU time | 630.76 seconds |
| Started | Sep 01 07:37:47 AM UTC 24 |
| Finished | Sep 01 07:48:25 AM UTC 24 |
| Peak memory | 211756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938930073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.3938930073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/1.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_lowpower_counter.183311497 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 45666139310 ps |
| CPU time | 30.8 seconds |
| Started | Sep 01 07:37:46 AM UTC 24 |
| Finished | Sep 01 07:38:19 AM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183311497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.183311497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/1.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_poweron_counter.4031530849 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4306919763 ps |
| CPU time | 23.18 seconds |
| Started | Sep 01 07:37:44 AM UTC 24 |
| Finished | Sep 01 07:38:09 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031530849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.4031530849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/1.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_sec_cm.1382883205 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 7769609763 ps |
| CPU time | 8.47 seconds |
| Started | Sep 01 07:37:49 AM UTC 24 |
| Finished | Sep 01 07:37:58 AM UTC 24 |
| Peak memory | 243556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382883205 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.1382883205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/1.adc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_smoke.3465871094 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5871447344 ps |
| CPU time | 5.21 seconds |
| Started | Sep 01 07:37:41 AM UTC 24 |
| Finished | Sep 01 07:37:48 AM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465871094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.3465871094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/1.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1552597285 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4080665849 ps |
| CPU time | 23.11 seconds |
| Started | Sep 01 07:37:49 AM UTC 24 |
| Finished | Sep 01 07:38:13 AM UTC 24 |
| Peak memory | 221672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1552597285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.adc_ctrl_stress_all_with_rand_reset.1552597285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_alert_test.2998965863 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 520418690 ps |
| CPU time | 3.13 seconds |
| Started | Sep 01 07:53:32 AM UTC 24 |
| Finished | Sep 01 07:53:36 AM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998965863 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.2998965863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/10.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_both.3115587548 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 514182341294 ps |
| CPU time | 1504.19 seconds |
| Started | Sep 01 07:52:42 AM UTC 24 |
| Finished | Sep 01 08:18:01 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115587548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.3115587548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/10.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2676532284 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 333266917573 ps |
| CPU time | 1023.89 seconds |
| Started | Sep 01 07:52:28 AM UTC 24 |
| Finished | Sep 01 08:09:44 AM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676532284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt_fixed.2676532284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/10.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled.1589149662 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 490075786589 ps |
| CPU time | 1418.58 seconds |
| Started | Sep 01 07:52:14 AM UTC 24 |
| Finished | Sep 01 08:16:07 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589149662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.1589149662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/10.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled_fixed.1377053573 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 157535556895 ps |
| CPU time | 127.49 seconds |
| Started | Sep 01 07:52:22 AM UTC 24 |
| Finished | Sep 01 07:54:32 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377053573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixed.1377053573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/10.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1501372177 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 415917832170 ps |
| CPU time | 330.46 seconds |
| Started | Sep 01 07:52:30 AM UTC 24 |
| Finished | Sep 01 07:58:04 AM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501372177 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_wakeup_fixed.1501372177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/10.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_lowpower_counter.1583707323 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 23825259487 ps |
| CPU time | 70.51 seconds |
| Started | Sep 01 07:52:49 AM UTC 24 |
| Finished | Sep 01 07:54:01 AM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583707323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1583707323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/10.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_poweron_counter.2385848613 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 3908520519 ps |
| CPU time | 17.49 seconds |
| Started | Sep 01 07:52:48 AM UTC 24 |
| Finished | Sep 01 07:53:06 AM UTC 24 |
| Peak memory | 211472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385848613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.2385848613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/10.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_smoke.2564734169 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 5894583727 ps |
| CPU time | 7.1 seconds |
| Started | Sep 01 07:52:05 AM UTC 24 |
| Finished | Sep 01 07:52:13 AM UTC 24 |
| Peak memory | 211292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564734169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.2564734169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/10.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1147854799 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 10390782998 ps |
| CPU time | 17.4 seconds |
| Started | Sep 01 07:53:13 AM UTC 24 |
| Finished | Sep 01 07:53:32 AM UTC 24 |
| Peak memory | 228296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1147854799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 10.adc_ctrl_stress_all_with_rand_reset.1147854799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/10.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_alert_test.3630949670 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 548585726 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 07:55:54 AM UTC 24 |
| Finished | Sep 01 07:55:56 AM UTC 24 |
| Peak memory | 210340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630949670 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3630949670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/11.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_clock_gating.1820944906 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 169178772658 ps |
| CPU time | 116.26 seconds |
| Started | Sep 01 07:54:05 AM UTC 24 |
| Finished | Sep 01 07:56:04 AM UTC 24 |
| Peak memory | 211492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820944906 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gating.1820944906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/11.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_both.1682572747 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 162986127130 ps |
| CPU time | 494.47 seconds |
| Started | Sep 01 07:54:33 AM UTC 24 |
| Finished | Sep 01 08:02:53 AM UTC 24 |
| Peak memory | 211796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682572747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.1682572747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/11.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt.3321454664 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 168048456899 ps |
| CPU time | 480.81 seconds |
| Started | Sep 01 07:53:39 AM UTC 24 |
| Finished | Sep 01 08:01:45 AM UTC 24 |
| Peak memory | 211428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321454664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.3321454664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/11.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2739389565 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 334202889297 ps |
| CPU time | 134.86 seconds |
| Started | Sep 01 07:53:59 AM UTC 24 |
| Finished | Sep 01 07:56:16 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739389565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt_fixed.2739389565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/11.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled.2694459992 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 163941403204 ps |
| CPU time | 176.86 seconds |
| Started | Sep 01 07:53:36 AM UTC 24 |
| Finished | Sep 01 07:56:36 AM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694459992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.2694459992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/11.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled_fixed.2330301441 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 330913981238 ps |
| CPU time | 250.07 seconds |
| Started | Sep 01 07:53:38 AM UTC 24 |
| Finished | Sep 01 07:57:51 AM UTC 24 |
| Peak memory | 211472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330301441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixed.2330301441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/11.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup.4020325754 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 347046428360 ps |
| CPU time | 107.48 seconds |
| Started | Sep 01 07:54:00 AM UTC 24 |
| Finished | Sep 01 07:55:49 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020325754 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_wakeup.4020325754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/11.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3443082497 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 577260218143 ps |
| CPU time | 402.05 seconds |
| Started | Sep 01 07:54:02 AM UTC 24 |
| Finished | Sep 01 08:00:49 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443082497 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_wakeup_fixed.3443082497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/11.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_fsm_reset.95250616 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 99500661145 ps |
| CPU time | 531.33 seconds |
| Started | Sep 01 07:55:32 AM UTC 24 |
| Finished | Sep 01 08:04:29 AM UTC 24 |
| Peak memory | 211816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95250616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_ SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.95250616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/11.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_lowpower_counter.2043772241 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 42908207729 ps |
| CPU time | 187.36 seconds |
| Started | Sep 01 07:55:19 AM UTC 24 |
| Finished | Sep 01 07:58:30 AM UTC 24 |
| Peak memory | 211540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043772241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.2043772241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/11.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_poweron_counter.3676250388 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 5044326795 ps |
| CPU time | 14.02 seconds |
| Started | Sep 01 07:55:16 AM UTC 24 |
| Finished | Sep 01 07:55:31 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676250388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.3676250388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/11.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_smoke.787399851 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 5616797317 ps |
| CPU time | 25.13 seconds |
| Started | Sep 01 07:53:32 AM UTC 24 |
| Finished | Sep 01 07:53:59 AM UTC 24 |
| Peak memory | 211536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787399851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.787399851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/11.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3890656535 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 11166445931 ps |
| CPU time | 20.07 seconds |
| Started | Sep 01 07:55:34 AM UTC 24 |
| Finished | Sep 01 07:55:55 AM UTC 24 |
| Peak memory | 221672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3890656535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 11.adc_ctrl_stress_all_with_rand_reset.3890656535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/11.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_alert_test.2970955524 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 552396855 ps |
| CPU time | 1.41 seconds |
| Started | Sep 01 07:57:40 AM UTC 24 |
| Finished | Sep 01 07:57:43 AM UTC 24 |
| Peak memory | 209800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970955524 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.2970955524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/12.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt.2267613348 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 161811171746 ps |
| CPU time | 479.59 seconds |
| Started | Sep 01 07:56:06 AM UTC 24 |
| Finished | Sep 01 08:04:11 AM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267613348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.2267613348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/12.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt_fixed.13089606 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 323258195389 ps |
| CPU time | 366.31 seconds |
| Started | Sep 01 07:56:17 AM UTC 24 |
| Finished | Sep 01 08:02:28 AM UTC 24 |
| Peak memory | 211740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13089606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas e_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt_fixed.13089606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/12.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled.1001557654 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 328942316155 ps |
| CPU time | 939.23 seconds |
| Started | Sep 01 07:55:57 AM UTC 24 |
| Finished | Sep 01 08:11:46 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001557654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1001557654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/12.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled_fixed.3697755002 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 319076740387 ps |
| CPU time | 431.71 seconds |
| Started | Sep 01 07:56:05 AM UTC 24 |
| Finished | Sep 01 08:03:22 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697755002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fixed.3697755002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/12.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup.1204487882 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 207678696530 ps |
| CPU time | 153.23 seconds |
| Started | Sep 01 07:56:22 AM UTC 24 |
| Finished | Sep 01 07:58:58 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204487882 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_wakeup.1204487882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/12.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup_fixed.145879106 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 395948547154 ps |
| CPU time | 1363.62 seconds |
| Started | Sep 01 07:56:36 AM UTC 24 |
| Finished | Sep 01 08:19:34 AM UTC 24 |
| Peak memory | 211792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145879106 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_wakeup_fixed.145879106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/12.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_lowpower_counter.1317148768 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 40765543369 ps |
| CPU time | 170.32 seconds |
| Started | Sep 01 07:57:16 AM UTC 24 |
| Finished | Sep 01 08:00:09 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317148768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.1317148768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/12.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_poweron_counter.745331718 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 3295557918 ps |
| CPU time | 13.76 seconds |
| Started | Sep 01 07:57:13 AM UTC 24 |
| Finished | Sep 01 07:57:28 AM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745331718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.745331718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/12.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_smoke.789976648 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 5803449989 ps |
| CPU time | 24.83 seconds |
| Started | Sep 01 07:55:56 AM UTC 24 |
| Finished | Sep 01 07:56:22 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789976648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.789976648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/12.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all.2662497477 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 134641076270 ps |
| CPU time | 786.08 seconds |
| Started | Sep 01 07:57:28 AM UTC 24 |
| Finished | Sep 01 08:10:42 AM UTC 24 |
| Peak memory | 211816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662497477 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.2662497477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/12.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3386902456 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1788258214 ps |
| CPU time | 13.21 seconds |
| Started | Sep 01 07:57:25 AM UTC 24 |
| Finished | Sep 01 07:57:39 AM UTC 24 |
| Peak memory | 222016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3386902456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 12.adc_ctrl_stress_all_with_rand_reset.3386902456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/12.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_alert_test.988371176 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 405752114 ps |
| CPU time | 2.47 seconds |
| Started | Sep 01 07:59:47 AM UTC 24 |
| Finished | Sep 01 07:59:50 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988371176 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.988371176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/13.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt.1229900202 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 161549189190 ps |
| CPU time | 451.36 seconds |
| Started | Sep 01 07:57:51 AM UTC 24 |
| Finished | Sep 01 08:05:28 AM UTC 24 |
| Peak memory | 211424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229900202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1229900202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/13.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1020152111 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 326241293153 ps |
| CPU time | 987.58 seconds |
| Started | Sep 01 07:57:58 AM UTC 24 |
| Finished | Sep 01 08:14:36 AM UTC 24 |
| Peak memory | 211524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020152111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt_fixed.1020152111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/13.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled.1334260238 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 165298399904 ps |
| CPU time | 73.6 seconds |
| Started | Sep 01 07:57:43 AM UTC 24 |
| Finished | Sep 01 07:58:59 AM UTC 24 |
| Peak memory | 211492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334260238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1334260238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/13.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled_fixed.4224604672 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 330331977511 ps |
| CPU time | 127.28 seconds |
| Started | Sep 01 07:57:44 AM UTC 24 |
| Finished | Sep 01 07:59:54 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224604672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixed.4224604672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/13.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup.2546170701 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 422650568189 ps |
| CPU time | 1306.96 seconds |
| Started | Sep 01 07:58:06 AM UTC 24 |
| Finished | Sep 01 08:20:06 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546170701 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_wakeup.2546170701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/13.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup_fixed.1863415727 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 203127270534 ps |
| CPU time | 529.01 seconds |
| Started | Sep 01 07:58:29 AM UTC 24 |
| Finished | Sep 01 08:07:23 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863415727 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_wakeup_fixed.1863415727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/13.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_fsm_reset.2758301276 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 116629908072 ps |
| CPU time | 643.25 seconds |
| Started | Sep 01 07:59:05 AM UTC 24 |
| Finished | Sep 01 08:09:55 AM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758301276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2758301276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/13.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_lowpower_counter.4144100122 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 24487480034 ps |
| CPU time | 22.14 seconds |
| Started | Sep 01 07:58:59 AM UTC 24 |
| Finished | Sep 01 07:59:22 AM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144100122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.4144100122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/13.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_poweron_counter.3997019618 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 3598239096 ps |
| CPU time | 4.27 seconds |
| Started | Sep 01 07:58:59 AM UTC 24 |
| Finished | Sep 01 07:59:04 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997019618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.3997019618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/13.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_smoke.2735667212 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 5823636587 ps |
| CPU time | 13.81 seconds |
| Started | Sep 01 07:57:41 AM UTC 24 |
| Finished | Sep 01 07:57:56 AM UTC 24 |
| Peak memory | 211292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735667212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2735667212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/13.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all.397903096 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 45281325093 ps |
| CPU time | 24.4 seconds |
| Started | Sep 01 07:59:23 AM UTC 24 |
| Finished | Sep 01 07:59:49 AM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397903096 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.397903096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/13.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.4130803698 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 22303401397 ps |
| CPU time | 34.28 seconds |
| Started | Sep 01 07:59:10 AM UTC 24 |
| Finished | Sep 01 07:59:46 AM UTC 24 |
| Peak memory | 221884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4130803698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 13.adc_ctrl_stress_all_with_rand_reset.4130803698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/13.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_alert_test.3911222491 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 307491716 ps |
| CPU time | 2.22 seconds |
| Started | Sep 01 08:00:57 AM UTC 24 |
| Finished | Sep 01 08:01:00 AM UTC 24 |
| Peak memory | 211288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911222491 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.3911222491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/14.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_clock_gating.3571509643 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 610863040857 ps |
| CPU time | 168.98 seconds |
| Started | Sep 01 08:00:09 AM UTC 24 |
| Finished | Sep 01 08:03:01 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571509643 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gating.3571509643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/14.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_both.873083012 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 156570452722 ps |
| CPU time | 65.8 seconds |
| Started | Sep 01 08:00:23 AM UTC 24 |
| Finished | Sep 01 08:01:31 AM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873083012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.873083012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/14.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt.3837084870 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 166346604991 ps |
| CPU time | 354.22 seconds |
| Started | Sep 01 07:59:55 AM UTC 24 |
| Finished | Sep 01 08:05:53 AM UTC 24 |
| Peak memory | 211744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837084870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3837084870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/14.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt_fixed.561552643 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 494018678946 ps |
| CPU time | 477.91 seconds |
| Started | Sep 01 07:59:59 AM UTC 24 |
| Finished | Sep 01 08:08:02 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561552643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt_fixed.561552643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/14.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled.3649932469 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 331197677888 ps |
| CPU time | 246.95 seconds |
| Started | Sep 01 07:59:50 AM UTC 24 |
| Finished | Sep 01 08:04:00 AM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649932469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3649932469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/14.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled_fixed.2018658192 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 495424131742 ps |
| CPU time | 131.59 seconds |
| Started | Sep 01 07:59:51 AM UTC 24 |
| Finished | Sep 01 08:02:05 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018658192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixed.2018658192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/14.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup_fixed.345396913 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 383971268228 ps |
| CPU time | 634.4 seconds |
| Started | Sep 01 08:00:09 AM UTC 24 |
| Finished | Sep 01 08:10:51 AM UTC 24 |
| Peak memory | 211604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345396913 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_wakeup_fixed.345396913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/14.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_lowpower_counter.1141007883 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 27867757618 ps |
| CPU time | 6.74 seconds |
| Started | Sep 01 08:00:33 AM UTC 24 |
| Finished | Sep 01 08:00:41 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141007883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.1141007883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/14.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_poweron_counter.4183626300 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 3001851708 ps |
| CPU time | 4.2 seconds |
| Started | Sep 01 08:00:27 AM UTC 24 |
| Finished | Sep 01 08:00:33 AM UTC 24 |
| Peak memory | 211472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183626300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.4183626300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/14.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_smoke.4030973701 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 6122987640 ps |
| CPU time | 7.77 seconds |
| Started | Sep 01 07:59:49 AM UTC 24 |
| Finished | Sep 01 07:59:58 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030973701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.4030973701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/14.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all.169887692 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 165600828093 ps |
| CPU time | 509.85 seconds |
| Started | Sep 01 08:00:55 AM UTC 24 |
| Finished | Sep 01 08:09:30 AM UTC 24 |
| Peak memory | 211472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169887692 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.169887692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/14.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.901173124 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 6304014807 ps |
| CPU time | 14.35 seconds |
| Started | Sep 01 08:00:50 AM UTC 24 |
| Finished | Sep 01 08:01:05 AM UTC 24 |
| Peak memory | 222272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=901173124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.901173124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/14.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_alert_test.1571622266 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 500150858 ps |
| CPU time | 1.96 seconds |
| Started | Sep 01 08:02:23 AM UTC 24 |
| Finished | Sep 01 08:02:26 AM UTC 24 |
| Peak memory | 210340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571622266 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1571622266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/15.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_both.1684258618 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 208329639079 ps |
| CPU time | 138.66 seconds |
| Started | Sep 01 08:01:51 AM UTC 24 |
| Finished | Sep 01 08:04:12 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684258618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.1684258618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/15.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt.2614824701 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 175211133402 ps |
| CPU time | 538.76 seconds |
| Started | Sep 01 08:01:23 AM UTC 24 |
| Finished | Sep 01 08:10:28 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614824701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.2614824701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/15.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2041635958 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 162181680794 ps |
| CPU time | 61.53 seconds |
| Started | Sep 01 08:01:28 AM UTC 24 |
| Finished | Sep 01 08:02:32 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041635958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt_fixed.2041635958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/15.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled.2608173041 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 166705955270 ps |
| CPU time | 118.43 seconds |
| Started | Sep 01 08:01:06 AM UTC 24 |
| Finished | Sep 01 08:03:07 AM UTC 24 |
| Peak memory | 211484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608173041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.2608173041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/15.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled_fixed.4240280557 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 160132928634 ps |
| CPU time | 157.56 seconds |
| Started | Sep 01 08:01:09 AM UTC 24 |
| Finished | Sep 01 08:03:50 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240280557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixed.4240280557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/15.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup.3288255670 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 368059205310 ps |
| CPU time | 577.45 seconds |
| Started | Sep 01 08:01:31 AM UTC 24 |
| Finished | Sep 01 08:11:16 AM UTC 24 |
| Peak memory | 211740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288255670 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_wakeup.3288255670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/15.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1404685568 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 392612473538 ps |
| CPU time | 456.61 seconds |
| Started | Sep 01 08:01:46 AM UTC 24 |
| Finished | Sep 01 08:09:27 AM UTC 24 |
| Peak memory | 211464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404685568 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_wakeup_fixed.1404685568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/15.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_fsm_reset.1759933374 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 103240868957 ps |
| CPU time | 803.48 seconds |
| Started | Sep 01 08:02:03 AM UTC 24 |
| Finished | Sep 01 08:15:35 AM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759933374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.1759933374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/15.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_lowpower_counter.724444950 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 32114983561 ps |
| CPU time | 19.33 seconds |
| Started | Sep 01 08:02:02 AM UTC 24 |
| Finished | Sep 01 08:02:22 AM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724444950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.724444950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/15.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_poweron_counter.1535859585 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 3875441038 ps |
| CPU time | 4.16 seconds |
| Started | Sep 01 08:01:56 AM UTC 24 |
| Finished | Sep 01 08:02:01 AM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535859585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.1535859585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/15.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_smoke.2223316420 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 6151301180 ps |
| CPU time | 20.63 seconds |
| Started | Sep 01 08:01:01 AM UTC 24 |
| Finished | Sep 01 08:01:23 AM UTC 24 |
| Peak memory | 211484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223316420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.2223316420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/15.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all.437394352 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 430294440975 ps |
| CPU time | 2298.35 seconds |
| Started | Sep 01 08:02:06 AM UTC 24 |
| Finished | Sep 01 08:40:47 AM UTC 24 |
| Peak memory | 212812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437394352 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.437394352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.4201137454 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 13349609828 ps |
| CPU time | 29.16 seconds |
| Started | Sep 01 08:02:06 AM UTC 24 |
| Finished | Sep 01 08:02:36 AM UTC 24 |
| Peak memory | 222156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4201137454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 15.adc_ctrl_stress_all_with_rand_reset.4201137454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_alert_test.1889698546 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 333076051 ps |
| CPU time | 2.28 seconds |
| Started | Sep 01 08:04:00 AM UTC 24 |
| Finished | Sep 01 08:04:04 AM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889698546 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1889698546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/16.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_both.1238095417 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 342562202883 ps |
| CPU time | 455.08 seconds |
| Started | Sep 01 08:03:07 AM UTC 24 |
| Finished | Sep 01 08:10:47 AM UTC 24 |
| Peak memory | 211408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238095417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.1238095417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/16.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt.871522974 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 161987720486 ps |
| CPU time | 160.25 seconds |
| Started | Sep 01 08:02:36 AM UTC 24 |
| Finished | Sep 01 08:05:18 AM UTC 24 |
| Peak memory | 211696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871522974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.871522974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/16.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt_fixed.500329619 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 486052155774 ps |
| CPU time | 218.18 seconds |
| Started | Sep 01 08:02:38 AM UTC 24 |
| Finished | Sep 01 08:06:19 AM UTC 24 |
| Peak memory | 211524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500329619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt_fixed.500329619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/16.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled.1044538527 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 489388760994 ps |
| CPU time | 882.1 seconds |
| Started | Sep 01 08:02:29 AM UTC 24 |
| Finished | Sep 01 08:17:21 AM UTC 24 |
| Peak memory | 211420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044538527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.1044538527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/16.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled_fixed.3302023867 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 169041970166 ps |
| CPU time | 183.23 seconds |
| Started | Sep 01 08:02:32 AM UTC 24 |
| Finished | Sep 01 08:05:38 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302023867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixed.3302023867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/16.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1972873776 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 605718470521 ps |
| CPU time | 441.95 seconds |
| Started | Sep 01 08:02:55 AM UTC 24 |
| Finished | Sep 01 08:10:21 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972873776 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_wakeup_fixed.1972873776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/16.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_fsm_reset.1968159352 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 116594505686 ps |
| CPU time | 506.76 seconds |
| Started | Sep 01 08:03:26 AM UTC 24 |
| Finished | Sep 01 08:11:58 AM UTC 24 |
| Peak memory | 212084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968159352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.1968159352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/16.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_lowpower_counter.953395834 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 43758761109 ps |
| CPU time | 27.06 seconds |
| Started | Sep 01 08:03:22 AM UTC 24 |
| Finished | Sep 01 08:03:50 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953395834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.953395834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/16.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_poweron_counter.362928573 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 3804359556 ps |
| CPU time | 16.71 seconds |
| Started | Sep 01 08:03:07 AM UTC 24 |
| Finished | Sep 01 08:03:25 AM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362928573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.362928573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/16.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_smoke.1384759548 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 5803457117 ps |
| CPU time | 25.27 seconds |
| Started | Sep 01 08:02:27 AM UTC 24 |
| Finished | Sep 01 08:02:54 AM UTC 24 |
| Peak memory | 211484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384759548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1384759548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/16.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.1552057712 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 75346526286 ps |
| CPU time | 34.13 seconds |
| Started | Sep 01 08:03:50 AM UTC 24 |
| Finished | Sep 01 08:04:26 AM UTC 24 |
| Peak memory | 221940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1552057712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 16.adc_ctrl_stress_all_with_rand_reset.1552057712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/16.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_alert_test.2172087008 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 496566243 ps |
| CPU time | 2.93 seconds |
| Started | Sep 01 08:05:36 AM UTC 24 |
| Finished | Sep 01 08:05:40 AM UTC 24 |
| Peak memory | 211480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172087008 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2172087008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/17.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt.3127922299 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 489752001780 ps |
| CPU time | 322.14 seconds |
| Started | Sep 01 08:04:13 AM UTC 24 |
| Finished | Sep 01 08:09:39 AM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127922299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.3127922299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/17.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2845455515 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 495837700783 ps |
| CPU time | 509.51 seconds |
| Started | Sep 01 08:04:14 AM UTC 24 |
| Finished | Sep 01 08:12:49 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845455515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt_fixed.2845455515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/17.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled.3464689729 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 499454135159 ps |
| CPU time | 697.73 seconds |
| Started | Sep 01 08:04:12 AM UTC 24 |
| Finished | Sep 01 08:15:56 AM UTC 24 |
| Peak memory | 211480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464689729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.3464689729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/17.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled_fixed.2980920142 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 163578462552 ps |
| CPU time | 55.81 seconds |
| Started | Sep 01 08:04:13 AM UTC 24 |
| Finished | Sep 01 08:05:10 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980920142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixed.2980920142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/17.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup.1218196901 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 370048326233 ps |
| CPU time | 1150.83 seconds |
| Started | Sep 01 08:04:16 AM UTC 24 |
| Finished | Sep 01 08:23:38 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218196901 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_wakeup.1218196901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/17.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup_fixed.2527999185 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 610182183841 ps |
| CPU time | 1537.35 seconds |
| Started | Sep 01 08:04:26 AM UTC 24 |
| Finished | Sep 01 08:30:18 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527999185 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_wakeup_fixed.2527999185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/17.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_fsm_reset.3909124912 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 82531215955 ps |
| CPU time | 512.65 seconds |
| Started | Sep 01 08:05:20 AM UTC 24 |
| Finished | Sep 01 08:13:58 AM UTC 24 |
| Peak memory | 211972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909124912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.3909124912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/17.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_lowpower_counter.67467297 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 43307392292 ps |
| CPU time | 88.71 seconds |
| Started | Sep 01 08:05:19 AM UTC 24 |
| Finished | Sep 01 08:06:50 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67467297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_ SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.67467297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/17.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_poweron_counter.129526056 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 4477905458 ps |
| CPU time | 20.56 seconds |
| Started | Sep 01 08:05:13 AM UTC 24 |
| Finished | Sep 01 08:05:35 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129526056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.129526056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/17.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_smoke.4085235620 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 5782922726 ps |
| CPU time | 7.04 seconds |
| Started | Sep 01 08:04:05 AM UTC 24 |
| Finished | Sep 01 08:04:13 AM UTC 24 |
| Peak memory | 211484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085235620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.4085235620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/17.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all.1834548768 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 67905498029 ps |
| CPU time | 95.98 seconds |
| Started | Sep 01 08:05:29 AM UTC 24 |
| Finished | Sep 01 08:07:06 AM UTC 24 |
| Peak memory | 211196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834548768 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.1834548768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.2707979370 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3580805663 ps |
| CPU time | 8.07 seconds |
| Started | Sep 01 08:05:28 AM UTC 24 |
| Finished | Sep 01 08:05:37 AM UTC 24 |
| Peak memory | 211328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2707979370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 17.adc_ctrl_stress_all_with_rand_reset.2707979370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_alert_test.3316743760 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 524201244 ps |
| CPU time | 3.01 seconds |
| Started | Sep 01 08:07:29 AM UTC 24 |
| Finished | Sep 01 08:07:33 AM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316743760 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.3316743760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/18.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_clock_gating.3038413874 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 163356908853 ps |
| CPU time | 67.78 seconds |
| Started | Sep 01 08:06:23 AM UTC 24 |
| Finished | Sep 01 08:07:33 AM UTC 24 |
| Peak memory | 211680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038413874 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gating.3038413874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/18.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt.540845622 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 489511929294 ps |
| CPU time | 1282.05 seconds |
| Started | Sep 01 08:05:41 AM UTC 24 |
| Finished | Sep 01 08:27:16 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540845622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.540845622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/18.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt_fixed.667853085 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 338211811091 ps |
| CPU time | 1046.75 seconds |
| Started | Sep 01 08:05:48 AM UTC 24 |
| Finished | Sep 01 08:23:25 AM UTC 24 |
| Peak memory | 211604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667853085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt_fixed.667853085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/18.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled.4244373129 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 160055330655 ps |
| CPU time | 445.36 seconds |
| Started | Sep 01 08:05:38 AM UTC 24 |
| Finished | Sep 01 08:13:08 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244373129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.4244373129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/18.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled_fixed.3561333235 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 492349679127 ps |
| CPU time | 1417.95 seconds |
| Started | Sep 01 08:05:39 AM UTC 24 |
| Finished | Sep 01 08:29:32 AM UTC 24 |
| Peak memory | 211680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561333235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixed.3561333235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/18.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_wakeup.927042733 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 522843728685 ps |
| CPU time | 438.73 seconds |
| Started | Sep 01 08:05:54 AM UTC 24 |
| Finished | Sep 01 08:13:18 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927042733 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_wakeup.927042733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/18.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1792596870 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 596303271764 ps |
| CPU time | 401.18 seconds |
| Started | Sep 01 08:06:19 AM UTC 24 |
| Finished | Sep 01 08:13:05 AM UTC 24 |
| Peak memory | 211408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792596870 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_wakeup_fixed.1792596870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/18.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_fsm_reset.1177557280 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 77607893900 ps |
| CPU time | 535.71 seconds |
| Started | Sep 01 08:06:54 AM UTC 24 |
| Finished | Sep 01 08:15:55 AM UTC 24 |
| Peak memory | 211972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177557280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1177557280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/18.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_lowpower_counter.2140107085 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 36714688923 ps |
| CPU time | 119.74 seconds |
| Started | Sep 01 08:06:51 AM UTC 24 |
| Finished | Sep 01 08:08:52 AM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140107085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2140107085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/18.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_poweron_counter.1676112873 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 3828633622 ps |
| CPU time | 4.92 seconds |
| Started | Sep 01 08:06:47 AM UTC 24 |
| Finished | Sep 01 08:06:53 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676112873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1676112873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/18.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_smoke.2909096289 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 5598423076 ps |
| CPU time | 10.43 seconds |
| Started | Sep 01 08:05:36 AM UTC 24 |
| Finished | Sep 01 08:05:47 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909096289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.2909096289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/18.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all.32248178 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 346503847620 ps |
| CPU time | 297.19 seconds |
| Started | Sep 01 08:07:24 AM UTC 24 |
| Finished | Sep 01 08:12:25 AM UTC 24 |
| Peak memory | 211492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32248178 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.32248178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/18.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.4212237337 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 9086414967 ps |
| CPU time | 20.23 seconds |
| Started | Sep 01 08:07:07 AM UTC 24 |
| Finished | Sep 01 08:07:29 AM UTC 24 |
| Peak memory | 221668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4212237337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 18.adc_ctrl_stress_all_with_rand_reset.4212237337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/18.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_alert_test.741042073 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 376694047 ps |
| CPU time | 2.28 seconds |
| Started | Sep 01 08:09:23 AM UTC 24 |
| Finished | Sep 01 08:09:27 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741042073 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.741042073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/19.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_clock_gating.4061364646 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 156785480885 ps |
| CPU time | 70.68 seconds |
| Started | Sep 01 08:08:11 AM UTC 24 |
| Finished | Sep 01 08:09:23 AM UTC 24 |
| Peak memory | 211680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061364646 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gating.4061364646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/19.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_both.2379218860 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 500914179808 ps |
| CPU time | 339.41 seconds |
| Started | Sep 01 08:08:29 AM UTC 24 |
| Finished | Sep 01 08:14:12 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379218860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.2379218860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/19.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_interrupt.3146199479 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 331250783324 ps |
| CPU time | 286.24 seconds |
| Started | Sep 01 08:07:46 AM UTC 24 |
| Finished | Sep 01 08:12:36 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146199479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3146199479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/19.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_interrupt_fixed.115850293 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 166177909634 ps |
| CPU time | 495.88 seconds |
| Started | Sep 01 08:07:55 AM UTC 24 |
| Finished | Sep 01 08:16:16 AM UTC 24 |
| Peak memory | 211408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115850293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt_fixed.115850293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/19.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled.2573281361 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 484394276439 ps |
| CPU time | 1522.29 seconds |
| Started | Sep 01 08:07:34 AM UTC 24 |
| Finished | Sep 01 08:33:12 AM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573281361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.2573281361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/19.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled_fixed.1729862659 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 326560320868 ps |
| CPU time | 476.37 seconds |
| Started | Sep 01 08:07:43 AM UTC 24 |
| Finished | Sep 01 08:15:45 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729862659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixed.1729862659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/19.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3071708931 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 411650428530 ps |
| CPU time | 337.5 seconds |
| Started | Sep 01 08:08:04 AM UTC 24 |
| Finished | Sep 01 08:13:45 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071708931 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_wakeup_fixed.3071708931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/19.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_lowpower_counter.969463645 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 48183624726 ps |
| CPU time | 206.76 seconds |
| Started | Sep 01 08:08:38 AM UTC 24 |
| Finished | Sep 01 08:12:08 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969463645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.969463645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/19.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_poweron_counter.1121607872 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 4533213145 ps |
| CPU time | 19.37 seconds |
| Started | Sep 01 08:08:35 AM UTC 24 |
| Finished | Sep 01 08:08:56 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121607872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.1121607872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/19.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_smoke.2665604079 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 5917882715 ps |
| CPU time | 19.01 seconds |
| Started | Sep 01 08:07:33 AM UTC 24 |
| Finished | Sep 01 08:07:53 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665604079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.2665604079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/19.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all.897702370 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 190905031734 ps |
| CPU time | 490.62 seconds |
| Started | Sep 01 08:09:03 AM UTC 24 |
| Finished | Sep 01 08:17:19 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897702370 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.897702370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/19.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.836386382 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 2130789219 ps |
| CPU time | 5.32 seconds |
| Started | Sep 01 08:08:56 AM UTC 24 |
| Finished | Sep 01 08:09:03 AM UTC 24 |
| Peak memory | 211540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=836386382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.836386382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/19.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_alert_test.2720810958 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 417970778 ps |
| CPU time | 2.65 seconds |
| Started | Sep 01 07:38:53 AM UTC 24 |
| Finished | Sep 01 07:38:57 AM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720810958 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.2720810958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/2.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.3852041628 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 182562003369 ps |
| CPU time | 46.33 seconds |
| Started | Sep 01 07:38:09 AM UTC 24 |
| Finished | Sep 01 07:38:57 AM UTC 24 |
| Peak memory | 211492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852041628 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gating.3852041628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/2.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.3947805357 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 504851775493 ps |
| CPU time | 1603.56 seconds |
| Started | Sep 01 07:38:14 AM UTC 24 |
| Finished | Sep 01 08:05:13 AM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947805357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3947805357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/2.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3264628015 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 325965997864 ps |
| CPU time | 272.7 seconds |
| Started | Sep 01 07:38:04 AM UTC 24 |
| Finished | Sep 01 07:42:40 AM UTC 24 |
| Peak memory | 211680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264628015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt_fixed.3264628015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/2.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled.3206655097 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 160898740182 ps |
| CPU time | 309.35 seconds |
| Started | Sep 01 07:37:59 AM UTC 24 |
| Finished | Sep 01 07:43:12 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206655097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3206655097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/2.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled_fixed.3965301491 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 327506353156 ps |
| CPU time | 269.55 seconds |
| Started | Sep 01 07:38:02 AM UTC 24 |
| Finished | Sep 01 07:42:35 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965301491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed.3965301491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/2.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup_fixed.591965849 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 210840828289 ps |
| CPU time | 587.68 seconds |
| Started | Sep 01 07:38:06 AM UTC 24 |
| Finished | Sep 01 07:48:00 AM UTC 24 |
| Peak memory | 211480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591965849 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_wakeup_fixed.591965849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/2.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_lowpower_counter.2905448673 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 21137551467 ps |
| CPU time | 97.04 seconds |
| Started | Sep 01 07:38:30 AM UTC 24 |
| Finished | Sep 01 07:40:09 AM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905448673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2905448673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/2.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_poweron_counter.3472164945 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3580148583 ps |
| CPU time | 15.79 seconds |
| Started | Sep 01 07:38:20 AM UTC 24 |
| Finished | Sep 01 07:38:37 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472164945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.3472164945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/2.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_sec_cm.643720665 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 3831540927 ps |
| CPU time | 8.08 seconds |
| Started | Sep 01 07:38:44 AM UTC 24 |
| Finished | Sep 01 07:38:53 AM UTC 24 |
| Peak memory | 243552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643720665 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.643720665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/2.adc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_smoke.431025642 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5967211445 ps |
| CPU time | 5.31 seconds |
| Started | Sep 01 07:37:57 AM UTC 24 |
| Finished | Sep 01 07:38:03 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431025642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.431025642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/2.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all.1353327719 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 174377185125 ps |
| CPU time | 515.5 seconds |
| Started | Sep 01 07:38:37 AM UTC 24 |
| Finished | Sep 01 07:47:18 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353327719 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.1353327719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_alert_test.3291875034 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 462122908 ps |
| CPU time | 1.34 seconds |
| Started | Sep 01 08:10:48 AM UTC 24 |
| Finished | Sep 01 08:10:50 AM UTC 24 |
| Peak memory | 210340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291875034 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.3291875034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/20.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_both.925784582 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 370800987603 ps |
| CPU time | 520.8 seconds |
| Started | Sep 01 08:10:19 AM UTC 24 |
| Finished | Sep 01 08:19:06 AM UTC 24 |
| Peak memory | 211604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925784582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.925784582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/20.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_interrupt.297905902 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 331481309805 ps |
| CPU time | 1094.66 seconds |
| Started | Sep 01 08:09:40 AM UTC 24 |
| Finished | Sep 01 08:28:05 AM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297905902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.297905902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/20.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3915040291 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 167561086398 ps |
| CPU time | 140.51 seconds |
| Started | Sep 01 08:09:44 AM UTC 24 |
| Finished | Sep 01 08:12:07 AM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915040291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt_fixed.3915040291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/20.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_polled.1119136005 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 487488288078 ps |
| CPU time | 1637.51 seconds |
| Started | Sep 01 08:09:29 AM UTC 24 |
| Finished | Sep 01 08:37:03 AM UTC 24 |
| Peak memory | 212488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119136005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.1119136005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/20.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_polled_fixed.3299927863 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 169655459273 ps |
| CPU time | 538.34 seconds |
| Started | Sep 01 08:09:32 AM UTC 24 |
| Finished | Sep 01 08:18:36 AM UTC 24 |
| Peak memory | 211680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299927863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixed.3299927863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/20.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_wakeup.2176140014 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 184568882154 ps |
| CPU time | 245.56 seconds |
| Started | Sep 01 08:09:44 AM UTC 24 |
| Finished | Sep 01 08:13:53 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176140014 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_wakeup.2176140014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/20.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_wakeup_fixed.2461344951 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 388088331450 ps |
| CPU time | 391.75 seconds |
| Started | Sep 01 08:09:53 AM UTC 24 |
| Finished | Sep 01 08:16:30 AM UTC 24 |
| Peak memory | 211744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461344951 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_wakeup_fixed.2461344951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/20.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_lowpower_counter.1410282602 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 43733951442 ps |
| CPU time | 21.3 seconds |
| Started | Sep 01 08:10:28 AM UTC 24 |
| Finished | Sep 01 08:10:51 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410282602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1410282602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/20.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_poweron_counter.2043333826 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 4354061201 ps |
| CPU time | 18.19 seconds |
| Started | Sep 01 08:10:22 AM UTC 24 |
| Finished | Sep 01 08:10:42 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043333826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2043333826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/20.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_smoke.3396629340 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 5662398025 ps |
| CPU time | 23.57 seconds |
| Started | Sep 01 08:09:28 AM UTC 24 |
| Finished | Sep 01 08:09:52 AM UTC 24 |
| Peak memory | 211484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396629340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3396629340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/20.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.1750542954 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 62832723336 ps |
| CPU time | 79.02 seconds |
| Started | Sep 01 08:10:43 AM UTC 24 |
| Finished | Sep 01 08:12:03 AM UTC 24 |
| Peak memory | 228520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1750542954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 20.adc_ctrl_stress_all_with_rand_reset.1750542954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/20.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_alert_test.3380740611 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 388894651 ps |
| CPU time | 1.17 seconds |
| Started | Sep 01 08:12:07 AM UTC 24 |
| Finished | Sep 01 08:12:09 AM UTC 24 |
| Peak memory | 209800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380740611 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3380740611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/21.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_clock_gating.3471459477 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 171428737349 ps |
| CPU time | 87.26 seconds |
| Started | Sep 01 08:11:27 AM UTC 24 |
| Finished | Sep 01 08:12:56 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471459477 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gating.3471459477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/21.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_interrupt.440750801 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 322441158142 ps |
| CPU time | 136.36 seconds |
| Started | Sep 01 08:10:53 AM UTC 24 |
| Finished | Sep 01 08:13:12 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440750801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.440750801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/21.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_interrupt_fixed.2951476290 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 330544535046 ps |
| CPU time | 408.79 seconds |
| Started | Sep 01 08:11:06 AM UTC 24 |
| Finished | Sep 01 08:18:00 AM UTC 24 |
| Peak memory | 211456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951476290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt_fixed.2951476290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/21.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_polled.3151869913 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 487860287455 ps |
| CPU time | 769.78 seconds |
| Started | Sep 01 08:10:52 AM UTC 24 |
| Finished | Sep 01 08:23:50 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151869913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.3151869913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/21.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_polled_fixed.1201806260 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 489128360465 ps |
| CPU time | 403.07 seconds |
| Started | Sep 01 08:10:52 AM UTC 24 |
| Finished | Sep 01 08:17:39 AM UTC 24 |
| Peak memory | 211616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201806260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fixed.1201806260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/21.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_wakeup.157976038 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 170441456031 ps |
| CPU time | 554.82 seconds |
| Started | Sep 01 08:11:16 AM UTC 24 |
| Finished | Sep 01 08:20:37 AM UTC 24 |
| Peak memory | 211484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157976038 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_wakeup.157976038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/21.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_wakeup_fixed.2395460758 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 198653846455 ps |
| CPU time | 397.47 seconds |
| Started | Sep 01 08:11:18 AM UTC 24 |
| Finished | Sep 01 08:18:01 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395460758 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_wakeup_fixed.2395460758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/21.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_fsm_reset.1951580030 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 73178641511 ps |
| CPU time | 531.29 seconds |
| Started | Sep 01 08:12:04 AM UTC 24 |
| Finished | Sep 01 08:21:01 AM UTC 24 |
| Peak memory | 211708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951580030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.1951580030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/21.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_lowpower_counter.3152594182 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 36751151434 ps |
| CPU time | 11.99 seconds |
| Started | Sep 01 08:11:59 AM UTC 24 |
| Finished | Sep 01 08:12:12 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152594182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.3152594182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/21.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_poweron_counter.2802179968 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 2694236057 ps |
| CPU time | 6.89 seconds |
| Started | Sep 01 08:11:56 AM UTC 24 |
| Finished | Sep 01 08:12:04 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802179968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2802179968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/21.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_smoke.3966441076 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 6038017941 ps |
| CPU time | 14.04 seconds |
| Started | Sep 01 08:10:51 AM UTC 24 |
| Finished | Sep 01 08:11:06 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966441076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.3966441076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/21.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_stress_all.2638528256 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 170640248657 ps |
| CPU time | 407.22 seconds |
| Started | Sep 01 08:12:07 AM UTC 24 |
| Finished | Sep 01 08:18:59 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638528256 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.2638528256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/21.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2472342717 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 1809033148 ps |
| CPU time | 14.68 seconds |
| Started | Sep 01 08:12:05 AM UTC 24 |
| Finished | Sep 01 08:12:21 AM UTC 24 |
| Peak memory | 211268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2472342717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 21.adc_ctrl_stress_all_with_rand_reset.2472342717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/21.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_alert_test.3666985671 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 321308936 ps |
| CPU time | 2.12 seconds |
| Started | Sep 01 08:13:13 AM UTC 24 |
| Finished | Sep 01 08:13:16 AM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666985671 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3666985671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/22.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_interrupt.253997339 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 497198902869 ps |
| CPU time | 1673.28 seconds |
| Started | Sep 01 08:12:22 AM UTC 24 |
| Finished | Sep 01 08:40:32 AM UTC 24 |
| Peak memory | 212820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253997339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.253997339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/22.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_interrupt_fixed.4290232280 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 477412954003 ps |
| CPU time | 131.85 seconds |
| Started | Sep 01 08:12:24 AM UTC 24 |
| Finished | Sep 01 08:14:38 AM UTC 24 |
| Peak memory | 211592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290232280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt_fixed.4290232280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/22.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_polled.1033610721 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 324288845267 ps |
| CPU time | 688.77 seconds |
| Started | Sep 01 08:12:10 AM UTC 24 |
| Finished | Sep 01 08:23:46 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033610721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.1033610721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/22.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_polled_fixed.2467863325 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 498356131522 ps |
| CPU time | 757.98 seconds |
| Started | Sep 01 08:12:12 AM UTC 24 |
| Finished | Sep 01 08:24:58 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467863325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixed.2467863325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/22.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_wakeup.390927897 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 186410207212 ps |
| CPU time | 671.16 seconds |
| Started | Sep 01 08:12:26 AM UTC 24 |
| Finished | Sep 01 08:23:44 AM UTC 24 |
| Peak memory | 211544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390927897 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_wakeup.390927897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/22.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1782054622 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 409119564865 ps |
| CPU time | 411.16 seconds |
| Started | Sep 01 08:12:37 AM UTC 24 |
| Finished | Sep 01 08:19:33 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782054622 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_wakeup_fixed.1782054622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/22.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_fsm_reset.3115411632 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 75781302746 ps |
| CPU time | 433.44 seconds |
| Started | Sep 01 08:12:59 AM UTC 24 |
| Finished | Sep 01 08:20:17 AM UTC 24 |
| Peak memory | 211816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115411632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.3115411632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/22.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_lowpower_counter.2978645218 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 32067394870 ps |
| CPU time | 23.87 seconds |
| Started | Sep 01 08:12:57 AM UTC 24 |
| Finished | Sep 01 08:13:23 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978645218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.2978645218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/22.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_poweron_counter.2018257604 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 3082592125 ps |
| CPU time | 7.09 seconds |
| Started | Sep 01 08:12:49 AM UTC 24 |
| Finished | Sep 01 08:12:57 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018257604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2018257604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/22.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_smoke.2283375585 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 5973396356 ps |
| CPU time | 13.83 seconds |
| Started | Sep 01 08:12:08 AM UTC 24 |
| Finished | Sep 01 08:12:23 AM UTC 24 |
| Peak memory | 211484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283375585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.2283375585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/22.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_stress_all.2983563676 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 421672059840 ps |
| CPU time | 1464.74 seconds |
| Started | Sep 01 08:13:09 AM UTC 24 |
| Finished | Sep 01 08:37:48 AM UTC 24 |
| Peak memory | 221920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983563676 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.2983563676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/22.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.3423979543 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 6415573187 ps |
| CPU time | 23.29 seconds |
| Started | Sep 01 08:13:06 AM UTC 24 |
| Finished | Sep 01 08:13:30 AM UTC 24 |
| Peak memory | 221728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3423979543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 22.adc_ctrl_stress_all_with_rand_reset.3423979543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/22.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_alert_test.2756249826 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 441536397 ps |
| CPU time | 1.01 seconds |
| Started | Sep 01 08:15:03 AM UTC 24 |
| Finished | Sep 01 08:15:05 AM UTC 24 |
| Peak memory | 209800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756249826 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.2756249826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/23.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_clock_gating.3834879274 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 175698690824 ps |
| CPU time | 174.18 seconds |
| Started | Sep 01 08:13:53 AM UTC 24 |
| Finished | Sep 01 08:16:50 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834879274 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gating.3834879274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/23.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_both.2663839236 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 547257176665 ps |
| CPU time | 489.21 seconds |
| Started | Sep 01 08:13:59 AM UTC 24 |
| Finished | Sep 01 08:22:13 AM UTC 24 |
| Peak memory | 211524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663839236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2663839236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/23.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_interrupt.3321899035 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 168492995934 ps |
| CPU time | 156.09 seconds |
| Started | Sep 01 08:13:26 AM UTC 24 |
| Finished | Sep 01 08:16:05 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321899035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3321899035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/23.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_interrupt_fixed.3092533594 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 490603907208 ps |
| CPU time | 1230.84 seconds |
| Started | Sep 01 08:13:26 AM UTC 24 |
| Finished | Sep 01 08:34:09 AM UTC 24 |
| Peak memory | 211784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092533594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt_fixed.3092533594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/23.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_polled.820429848 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 321723329090 ps |
| CPU time | 239.44 seconds |
| Started | Sep 01 08:13:19 AM UTC 24 |
| Finished | Sep 01 08:17:22 AM UTC 24 |
| Peak memory | 211420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820429848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.820429848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/23.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_polled_fixed.1748727676 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 319202980727 ps |
| CPU time | 217.04 seconds |
| Started | Sep 01 08:13:24 AM UTC 24 |
| Finished | Sep 01 08:17:04 AM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748727676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixed.1748727676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/23.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_wakeup.3346375982 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 169974314645 ps |
| CPU time | 233.58 seconds |
| Started | Sep 01 08:13:31 AM UTC 24 |
| Finished | Sep 01 08:17:28 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346375982 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_wakeup.3346375982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/23.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_wakeup_fixed.1253078510 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 203699511890 ps |
| CPU time | 329.81 seconds |
| Started | Sep 01 08:13:46 AM UTC 24 |
| Finished | Sep 01 08:19:20 AM UTC 24 |
| Peak memory | 211684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253078510 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_wakeup_fixed.1253078510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/23.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_fsm_reset.2887269178 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 79836483266 ps |
| CPU time | 401.21 seconds |
| Started | Sep 01 08:14:36 AM UTC 24 |
| Finished | Sep 01 08:21:21 AM UTC 24 |
| Peak memory | 211972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887269178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2887269178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/23.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_lowpower_counter.1705323151 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 41701091943 ps |
| CPU time | 102.1 seconds |
| Started | Sep 01 08:14:20 AM UTC 24 |
| Finished | Sep 01 08:16:04 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705323151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1705323151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/23.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_poweron_counter.764642245 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 4254605905 ps |
| CPU time | 3.92 seconds |
| Started | Sep 01 08:14:14 AM UTC 24 |
| Finished | Sep 01 08:14:19 AM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764642245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.764642245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/23.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_smoke.4083180296 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 6055850983 ps |
| CPU time | 7.05 seconds |
| Started | Sep 01 08:13:17 AM UTC 24 |
| Finished | Sep 01 08:13:25 AM UTC 24 |
| Peak memory | 211292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083180296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.4083180296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/23.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all.1771668496 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 727903379192 ps |
| CPU time | 1785.5 seconds |
| Started | Sep 01 08:15:00 AM UTC 24 |
| Finished | Sep 01 08:45:02 AM UTC 24 |
| Peak memory | 212480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771668496 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.1771668496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/23.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_alert_test.2665676277 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 454179097 ps |
| CPU time | 2.57 seconds |
| Started | Sep 01 08:16:20 AM UTC 24 |
| Finished | Sep 01 08:16:24 AM UTC 24 |
| Peak memory | 211480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665676277 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.2665676277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/24.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_clock_gating.3877706949 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 166792059316 ps |
| CPU time | 149.11 seconds |
| Started | Sep 01 08:15:57 AM UTC 24 |
| Finished | Sep 01 08:18:29 AM UTC 24 |
| Peak memory | 211680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877706949 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gating.3877706949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/24.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_both.2242149309 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 191824317355 ps |
| CPU time | 154.58 seconds |
| Started | Sep 01 08:16:04 AM UTC 24 |
| Finished | Sep 01 08:18:41 AM UTC 24 |
| Peak memory | 211796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242149309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.2242149309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/24.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_interrupt.398257128 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 326051109984 ps |
| CPU time | 241.3 seconds |
| Started | Sep 01 08:15:36 AM UTC 24 |
| Finished | Sep 01 08:19:41 AM UTC 24 |
| Peak memory | 211504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398257128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.398257128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/24.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_interrupt_fixed.4053570380 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 328684938223 ps |
| CPU time | 829.48 seconds |
| Started | Sep 01 08:15:43 AM UTC 24 |
| Finished | Sep 01 08:29:41 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053570380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt_fixed.4053570380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/24.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_polled.4228544199 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 169689369683 ps |
| CPU time | 305.62 seconds |
| Started | Sep 01 08:15:09 AM UTC 24 |
| Finished | Sep 01 08:20:18 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228544199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.4228544199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/24.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_polled_fixed.3981112199 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 166766401995 ps |
| CPU time | 459.6 seconds |
| Started | Sep 01 08:15:32 AM UTC 24 |
| Finished | Sep 01 08:23:17 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981112199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixed.3981112199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/24.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_wakeup.3135332488 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 262640759988 ps |
| CPU time | 484.67 seconds |
| Started | Sep 01 08:15:46 AM UTC 24 |
| Finished | Sep 01 08:23:56 AM UTC 24 |
| Peak memory | 211676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135332488 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_wakeup.3135332488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/24.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_wakeup_fixed.3476270683 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 384774157117 ps |
| CPU time | 251.81 seconds |
| Started | Sep 01 08:15:56 AM UTC 24 |
| Finished | Sep 01 08:20:11 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476270683 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_wakeup_fixed.3476270683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/24.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_fsm_reset.2283354911 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 77017192026 ps |
| CPU time | 483.88 seconds |
| Started | Sep 01 08:16:08 AM UTC 24 |
| Finished | Sep 01 08:24:17 AM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283354911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.2283354911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/24.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_lowpower_counter.2438582484 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 36336466615 ps |
| CPU time | 41.54 seconds |
| Started | Sep 01 08:16:08 AM UTC 24 |
| Finished | Sep 01 08:16:51 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438582484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.2438582484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/24.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_poweron_counter.3160639798 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 4165224684 ps |
| CPU time | 5.35 seconds |
| Started | Sep 01 08:16:05 AM UTC 24 |
| Finished | Sep 01 08:16:12 AM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160639798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.3160639798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/24.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_smoke.2048847078 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 5671263462 ps |
| CPU time | 23.31 seconds |
| Started | Sep 01 08:15:06 AM UTC 24 |
| Finished | Sep 01 08:15:31 AM UTC 24 |
| Peak memory | 211292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048847078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2048847078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/24.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_stress_all.2549503309 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 221373441258 ps |
| CPU time | 659.32 seconds |
| Started | Sep 01 08:16:17 AM UTC 24 |
| Finished | Sep 01 08:27:23 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549503309 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.2549503309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/24.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.899095604 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 17506282051 ps |
| CPU time | 25.68 seconds |
| Started | Sep 01 08:16:13 AM UTC 24 |
| Finished | Sep 01 08:16:40 AM UTC 24 |
| Peak memory | 221884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=899095604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.899095604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/24.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_alert_test.1765594382 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 505783456 ps |
| CPU time | 2.94 seconds |
| Started | Sep 01 08:17:43 AM UTC 24 |
| Finished | Sep 01 08:17:47 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765594382 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1765594382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/25.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_clock_gating.2572686842 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 516546758314 ps |
| CPU time | 230.29 seconds |
| Started | Sep 01 08:17:04 AM UTC 24 |
| Finished | Sep 01 08:20:58 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572686842 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gating.2572686842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/25.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_both.2885347912 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 165077083006 ps |
| CPU time | 467.07 seconds |
| Started | Sep 01 08:17:20 AM UTC 24 |
| Finished | Sep 01 08:25:12 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885347912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.2885347912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/25.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_interrupt.2503308777 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 160888143295 ps |
| CPU time | 667.51 seconds |
| Started | Sep 01 08:16:40 AM UTC 24 |
| Finished | Sep 01 08:27:55 AM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503308777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2503308777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/25.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1384220500 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 323713119230 ps |
| CPU time | 862.64 seconds |
| Started | Sep 01 08:16:51 AM UTC 24 |
| Finished | Sep 01 08:31:22 AM UTC 24 |
| Peak memory | 211668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384220500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt_fixed.1384220500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/25.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_polled.1097421960 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 162551256619 ps |
| CPU time | 573.66 seconds |
| Started | Sep 01 08:16:31 AM UTC 24 |
| Finished | Sep 01 08:26:11 AM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097421960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1097421960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/25.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_polled_fixed.1114840428 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 325900928260 ps |
| CPU time | 125.31 seconds |
| Started | Sep 01 08:16:36 AM UTC 24 |
| Finished | Sep 01 08:18:44 AM UTC 24 |
| Peak memory | 211472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114840428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixed.1114840428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/25.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_wakeup.2059559003 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 167400989474 ps |
| CPU time | 437.71 seconds |
| Started | Sep 01 08:16:51 AM UTC 24 |
| Finished | Sep 01 08:24:14 AM UTC 24 |
| Peak memory | 211804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059559003 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_wakeup.2059559003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/25.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_wakeup_fixed.559638932 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 410063074710 ps |
| CPU time | 332.98 seconds |
| Started | Sep 01 08:16:56 AM UTC 24 |
| Finished | Sep 01 08:22:33 AM UTC 24 |
| Peak memory | 211616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559638932 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_wakeup_fixed.559638932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/25.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_fsm_reset.41682368 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 103446094266 ps |
| CPU time | 822.95 seconds |
| Started | Sep 01 08:17:29 AM UTC 24 |
| Finished | Sep 01 08:31:20 AM UTC 24 |
| Peak memory | 211696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41682368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_ SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.41682368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/25.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_lowpower_counter.537277422 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 30210163068 ps |
| CPU time | 102.51 seconds |
| Started | Sep 01 08:17:23 AM UTC 24 |
| Finished | Sep 01 08:19:07 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537277422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.537277422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/25.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_poweron_counter.4222097612 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 3988618227 ps |
| CPU time | 9.78 seconds |
| Started | Sep 01 08:17:22 AM UTC 24 |
| Finished | Sep 01 08:17:32 AM UTC 24 |
| Peak memory | 211408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222097612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.4222097612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/25.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_smoke.2929113478 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 6118501762 ps |
| CPU time | 9.31 seconds |
| Started | Sep 01 08:16:25 AM UTC 24 |
| Finished | Sep 01 08:16:36 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929113478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.2929113478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/25.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_alert_test.2927398584 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 347009855 ps |
| CPU time | 2.39 seconds |
| Started | Sep 01 08:19:08 AM UTC 24 |
| Finished | Sep 01 08:19:12 AM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927398584 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.2927398584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/26.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_clock_gating.3221344431 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 348038573181 ps |
| CPU time | 235.98 seconds |
| Started | Sep 01 08:18:37 AM UTC 24 |
| Finished | Sep 01 08:22:36 AM UTC 24 |
| Peak memory | 211676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221344431 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gating.3221344431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/26.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_both.3750722200 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 257236999223 ps |
| CPU time | 181.8 seconds |
| Started | Sep 01 08:18:42 AM UTC 24 |
| Finished | Sep 01 08:21:46 AM UTC 24 |
| Peak memory | 211744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750722200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.3750722200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/26.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_interrupt.1938541979 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 318396143024 ps |
| CPU time | 867.59 seconds |
| Started | Sep 01 08:18:01 AM UTC 24 |
| Finished | Sep 01 08:32:38 AM UTC 24 |
| Peak memory | 211424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938541979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.1938541979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/26.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_interrupt_fixed.1424380941 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 325501647174 ps |
| CPU time | 249.03 seconds |
| Started | Sep 01 08:18:01 AM UTC 24 |
| Finished | Sep 01 08:22:14 AM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424380941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt_fixed.1424380941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/26.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_polled.2854101509 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 160265732972 ps |
| CPU time | 380.22 seconds |
| Started | Sep 01 08:17:56 AM UTC 24 |
| Finished | Sep 01 08:24:21 AM UTC 24 |
| Peak memory | 211424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854101509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.2854101509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/26.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_polled_fixed.2336592363 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 159181351571 ps |
| CPU time | 505.76 seconds |
| Started | Sep 01 08:18:00 AM UTC 24 |
| Finished | Sep 01 08:26:32 AM UTC 24 |
| Peak memory | 211680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336592363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fixed.2336592363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/26.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_wakeup.3373615171 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 517586364637 ps |
| CPU time | 1865.44 seconds |
| Started | Sep 01 08:18:30 AM UTC 24 |
| Finished | Sep 01 08:49:54 AM UTC 24 |
| Peak memory | 212488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373615171 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_wakeup.3373615171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/26.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3644094410 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 196610804457 ps |
| CPU time | 124.64 seconds |
| Started | Sep 01 08:18:36 AM UTC 24 |
| Finished | Sep 01 08:20:43 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644094410 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_wakeup_fixed.3644094410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/26.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_fsm_reset.1888831887 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 127136543810 ps |
| CPU time | 547.97 seconds |
| Started | Sep 01 08:18:59 AM UTC 24 |
| Finished | Sep 01 08:28:13 AM UTC 24 |
| Peak memory | 211780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888831887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.1888831887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/26.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_lowpower_counter.1560351433 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 45575940026 ps |
| CPU time | 33.13 seconds |
| Started | Sep 01 08:18:53 AM UTC 24 |
| Finished | Sep 01 08:19:27 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560351433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.1560351433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/26.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_poweron_counter.4044680384 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 4918005589 ps |
| CPU time | 5.77 seconds |
| Started | Sep 01 08:18:45 AM UTC 24 |
| Finished | Sep 01 08:18:52 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044680384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.4044680384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/26.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_smoke.3264171421 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 5758063940 ps |
| CPU time | 6.28 seconds |
| Started | Sep 01 08:17:48 AM UTC 24 |
| Finished | Sep 01 08:17:56 AM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264171421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.3264171421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/26.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_stress_all.1696147781 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 496909646306 ps |
| CPU time | 1151.18 seconds |
| Started | Sep 01 08:19:06 AM UTC 24 |
| Finished | Sep 01 08:38:29 AM UTC 24 |
| Peak memory | 211856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696147781 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.1696147781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/26.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_alert_test.412801898 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 333026191 ps |
| CPU time | 2.27 seconds |
| Started | Sep 01 08:20:25 AM UTC 24 |
| Finished | Sep 01 08:20:28 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412801898 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.412801898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/27.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_clock_gating.1209359485 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 171015543122 ps |
| CPU time | 559.11 seconds |
| Started | Sep 01 08:19:42 AM UTC 24 |
| Finished | Sep 01 08:29:07 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209359485 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gating.1209359485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/27.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_interrupt.2291746487 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 505511144207 ps |
| CPU time | 571.53 seconds |
| Started | Sep 01 08:19:29 AM UTC 24 |
| Finished | Sep 01 08:29:07 AM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291746487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2291746487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/27.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_interrupt_fixed.1738197880 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 329543595211 ps |
| CPU time | 1069.57 seconds |
| Started | Sep 01 08:19:34 AM UTC 24 |
| Finished | Sep 01 08:37:34 AM UTC 24 |
| Peak memory | 211588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738197880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt_fixed.1738197880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/27.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_polled.2871786233 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 324786530580 ps |
| CPU time | 918.67 seconds |
| Started | Sep 01 08:19:21 AM UTC 24 |
| Finished | Sep 01 08:34:48 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871786233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.2871786233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/27.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_polled_fixed.49890324 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 492999805697 ps |
| CPU time | 1331.4 seconds |
| Started | Sep 01 08:19:23 AM UTC 24 |
| Finished | Sep 01 08:41:47 AM UTC 24 |
| Peak memory | 212532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49890324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas e_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixed.49890324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/27.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_wakeup.414280389 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 197949629240 ps |
| CPU time | 75.3 seconds |
| Started | Sep 01 08:19:35 AM UTC 24 |
| Finished | Sep 01 08:20:52 AM UTC 24 |
| Peak memory | 211484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414280389 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_wakeup.414280389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/27.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2272723218 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 212677595623 ps |
| CPU time | 174.34 seconds |
| Started | Sep 01 08:19:39 AM UTC 24 |
| Finished | Sep 01 08:22:36 AM UTC 24 |
| Peak memory | 211812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272723218 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_wakeup_fixed.2272723218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/27.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_fsm_reset.4205931485 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 128867955887 ps |
| CPU time | 793.59 seconds |
| Started | Sep 01 08:20:12 AM UTC 24 |
| Finished | Sep 01 08:33:33 AM UTC 24 |
| Peak memory | 211896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205931485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.4205931485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/27.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_lowpower_counter.2044524400 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 42837896952 ps |
| CPU time | 12.59 seconds |
| Started | Sep 01 08:20:10 AM UTC 24 |
| Finished | Sep 01 08:20:24 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044524400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2044524400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/27.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_poweron_counter.603217544 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 4626921717 ps |
| CPU time | 18.51 seconds |
| Started | Sep 01 08:20:06 AM UTC 24 |
| Finished | Sep 01 08:20:26 AM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603217544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.603217544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/27.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_smoke.4085191775 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 6020729433 ps |
| CPU time | 24.84 seconds |
| Started | Sep 01 08:19:12 AM UTC 24 |
| Finished | Sep 01 08:19:38 AM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085191775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.4085191775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/27.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_stress_all.1070874434 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 425607543737 ps |
| CPU time | 488.28 seconds |
| Started | Sep 01 08:20:20 AM UTC 24 |
| Finished | Sep 01 08:28:33 AM UTC 24 |
| Peak memory | 211684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070874434 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all.1070874434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/27.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2796150122 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 3460751002 ps |
| CPU time | 21.64 seconds |
| Started | Sep 01 08:20:17 AM UTC 24 |
| Finished | Sep 01 08:20:40 AM UTC 24 |
| Peak memory | 222024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2796150122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 27.adc_ctrl_stress_all_with_rand_reset.2796150122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/27.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_alert_test.2401975043 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 320514493 ps |
| CPU time | 2.11 seconds |
| Started | Sep 01 08:21:32 AM UTC 24 |
| Finished | Sep 01 08:21:35 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401975043 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.2401975043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/28.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_clock_gating.475534681 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 504241049136 ps |
| CPU time | 535.14 seconds |
| Started | Sep 01 08:20:43 AM UTC 24 |
| Finished | Sep 01 08:29:45 AM UTC 24 |
| Peak memory | 211536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475534681 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gating.475534681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/28.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_both.978727971 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 165192027134 ps |
| CPU time | 273.05 seconds |
| Started | Sep 01 08:20:53 AM UTC 24 |
| Finished | Sep 01 08:25:29 AM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978727971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.978727971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/28.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_interrupt.2001818620 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 321578243255 ps |
| CPU time | 478.81 seconds |
| Started | Sep 01 08:20:33 AM UTC 24 |
| Finished | Sep 01 08:28:37 AM UTC 24 |
| Peak memory | 211484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001818620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.2001818620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/28.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2587741422 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 499166797774 ps |
| CPU time | 119.18 seconds |
| Started | Sep 01 08:20:33 AM UTC 24 |
| Finished | Sep 01 08:22:35 AM UTC 24 |
| Peak memory | 211456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587741422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt_fixed.2587741422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/28.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_polled.4241200217 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 329936278760 ps |
| CPU time | 150.89 seconds |
| Started | Sep 01 08:20:29 AM UTC 24 |
| Finished | Sep 01 08:23:02 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241200217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.4241200217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/28.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_polled_fixed.475212068 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 166023811410 ps |
| CPU time | 146.61 seconds |
| Started | Sep 01 08:20:33 AM UTC 24 |
| Finished | Sep 01 08:23:02 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475212068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixed.475212068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/28.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_wakeup.4203643052 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 532574890713 ps |
| CPU time | 549.91 seconds |
| Started | Sep 01 08:20:38 AM UTC 24 |
| Finished | Sep 01 08:29:54 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203643052 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_wakeup.4203643052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/28.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3744994683 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 402104187686 ps |
| CPU time | 1105.28 seconds |
| Started | Sep 01 08:20:41 AM UTC 24 |
| Finished | Sep 01 08:39:18 AM UTC 24 |
| Peak memory | 211424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744994683 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_wakeup_fixed.3744994683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/28.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_fsm_reset.1875187655 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 98239032329 ps |
| CPU time | 661.49 seconds |
| Started | Sep 01 08:21:04 AM UTC 24 |
| Finished | Sep 01 08:32:12 AM UTC 24 |
| Peak memory | 212032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875187655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.1875187655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/28.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_lowpower_counter.3845184912 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 40449856814 ps |
| CPU time | 28.86 seconds |
| Started | Sep 01 08:21:02 AM UTC 24 |
| Finished | Sep 01 08:21:32 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845184912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3845184912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/28.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_poweron_counter.2555984042 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 2721327137 ps |
| CPU time | 3.59 seconds |
| Started | Sep 01 08:20:59 AM UTC 24 |
| Finished | Sep 01 08:21:03 AM UTC 24 |
| Peak memory | 211472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555984042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.2555984042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/28.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_smoke.413572668 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 5601768403 ps |
| CPU time | 4 seconds |
| Started | Sep 01 08:20:27 AM UTC 24 |
| Finished | Sep 01 08:20:32 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413572668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.413572668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/28.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_stress_all.2419948531 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 91671565200 ps |
| CPU time | 520.14 seconds |
| Started | Sep 01 08:21:28 AM UTC 24 |
| Finished | Sep 01 08:30:13 AM UTC 24 |
| Peak memory | 227892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419948531 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.2419948531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/28.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.2414405040 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 2787420724 ps |
| CPU time | 18.89 seconds |
| Started | Sep 01 08:21:22 AM UTC 24 |
| Finished | Sep 01 08:21:42 AM UTC 24 |
| Peak memory | 222080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2414405040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 28.adc_ctrl_stress_all_with_rand_reset.2414405040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/28.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_alert_test.2110746412 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 467228390 ps |
| CPU time | 2.54 seconds |
| Started | Sep 01 08:22:37 AM UTC 24 |
| Finished | Sep 01 08:22:41 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110746412 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.2110746412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/29.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_clock_gating.1413510333 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 581840298730 ps |
| CPU time | 1740.73 seconds |
| Started | Sep 01 08:22:14 AM UTC 24 |
| Finished | Sep 01 08:51:32 AM UTC 24 |
| Peak memory | 212548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413510333 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gating.1413510333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/29.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_both.3554111540 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 340179832916 ps |
| CPU time | 333.98 seconds |
| Started | Sep 01 08:22:15 AM UTC 24 |
| Finished | Sep 01 08:27:54 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554111540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3554111540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/29.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_interrupt.2545464538 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 324060183821 ps |
| CPU time | 1083.09 seconds |
| Started | Sep 01 08:21:43 AM UTC 24 |
| Finished | Sep 01 08:39:57 AM UTC 24 |
| Peak memory | 211428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545464538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.2545464538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/29.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_interrupt_fixed.416239489 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 329386194051 ps |
| CPU time | 1060.68 seconds |
| Started | Sep 01 08:21:47 AM UTC 24 |
| Finished | Sep 01 08:39:38 AM UTC 24 |
| Peak memory | 211524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416239489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt_fixed.416239489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/29.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_polled.2619986985 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 162762474237 ps |
| CPU time | 50.53 seconds |
| Started | Sep 01 08:21:36 AM UTC 24 |
| Finished | Sep 01 08:22:28 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619986985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.2619986985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/29.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_polled_fixed.3941309617 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 321108471801 ps |
| CPU time | 1074.81 seconds |
| Started | Sep 01 08:21:40 AM UTC 24 |
| Finished | Sep 01 08:39:45 AM UTC 24 |
| Peak memory | 211616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941309617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixed.3941309617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/29.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3889953669 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 390929106112 ps |
| CPU time | 1179.76 seconds |
| Started | Sep 01 08:22:11 AM UTC 24 |
| Finished | Sep 01 08:42:02 AM UTC 24 |
| Peak memory | 212528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889953669 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_wakeup_fixed.3889953669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/29.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_fsm_reset.3758308821 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 85463649755 ps |
| CPU time | 389.93 seconds |
| Started | Sep 01 08:22:29 AM UTC 24 |
| Finished | Sep 01 08:29:03 AM UTC 24 |
| Peak memory | 211816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758308821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3758308821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/29.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_lowpower_counter.4246807689 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 33094057302 ps |
| CPU time | 38.92 seconds |
| Started | Sep 01 08:22:24 AM UTC 24 |
| Finished | Sep 01 08:23:05 AM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246807689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.4246807689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/29.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_poweron_counter.2677285288 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 3062035684 ps |
| CPU time | 4.24 seconds |
| Started | Sep 01 08:22:18 AM UTC 24 |
| Finished | Sep 01 08:22:23 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677285288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.2677285288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/29.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_smoke.429777804 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 5939083704 ps |
| CPU time | 25.38 seconds |
| Started | Sep 01 08:21:32 AM UTC 24 |
| Finished | Sep 01 08:21:59 AM UTC 24 |
| Peak memory | 211472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429777804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.429777804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/29.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all.3637954507 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 358419096075 ps |
| CPU time | 1338.3 seconds |
| Started | Sep 01 08:22:35 AM UTC 24 |
| Finished | Sep 01 08:45:08 AM UTC 24 |
| Peak memory | 212556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637954507 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.3637954507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/29.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.1860236624 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 3654798568 ps |
| CPU time | 11.72 seconds |
| Started | Sep 01 08:22:34 AM UTC 24 |
| Finished | Sep 01 08:22:47 AM UTC 24 |
| Peak memory | 211408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1860236624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 29.adc_ctrl_stress_all_with_rand_reset.1860236624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/29.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_alert_test.247368442 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 482692798 ps |
| CPU time | 1.17 seconds |
| Started | Sep 01 07:40:47 AM UTC 24 |
| Finished | Sep 01 07:40:49 AM UTC 24 |
| Peak memory | 209804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247368442 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.247368442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/3.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_clock_gating.705217509 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 353463388185 ps |
| CPU time | 275.14 seconds |
| Started | Sep 01 07:39:34 AM UTC 24 |
| Finished | Sep 01 07:44:13 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705217509 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gating.705217509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/3.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt.209457853 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 328625957788 ps |
| CPU time | 278.3 seconds |
| Started | Sep 01 07:39:00 AM UTC 24 |
| Finished | Sep 01 07:43:42 AM UTC 24 |
| Peak memory | 211424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209457853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.209457853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/3.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt_fixed.952122630 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 163412620895 ps |
| CPU time | 333.77 seconds |
| Started | Sep 01 07:39:03 AM UTC 24 |
| Finished | Sep 01 07:44:41 AM UTC 24 |
| Peak memory | 211484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952122630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt_fixed.952122630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/3.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled.963709807 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 492507109707 ps |
| CPU time | 1317.46 seconds |
| Started | Sep 01 07:38:58 AM UTC 24 |
| Finished | Sep 01 08:01:08 AM UTC 24 |
| Peak memory | 211740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963709807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.963709807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/3.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled_fixed.4243688759 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 496462376572 ps |
| CPU time | 1566.17 seconds |
| Started | Sep 01 07:38:59 AM UTC 24 |
| Finished | Sep 01 08:05:20 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243688759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed.4243688759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/3.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup.4203833433 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 178101844627 ps |
| CPU time | 550.78 seconds |
| Started | Sep 01 07:39:10 AM UTC 24 |
| Finished | Sep 01 07:48:27 AM UTC 24 |
| Peak memory | 211484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203833433 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_wakeup.4203833433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/3.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup_fixed.14168081 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 603835701160 ps |
| CPU time | 1794.03 seconds |
| Started | Sep 01 07:39:32 AM UTC 24 |
| Finished | Sep 01 08:09:43 AM UTC 24 |
| Peak memory | 211472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14168081 -assert nopostpro c +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_wakeup_fixed.14168081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/3.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_lowpower_counter.4158750410 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 34442975501 ps |
| CPU time | 37.45 seconds |
| Started | Sep 01 07:40:07 AM UTC 24 |
| Finished | Sep 01 07:40:46 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158750410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.4158750410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/3.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_poweron_counter.3201907777 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3943578112 ps |
| CPU time | 9.68 seconds |
| Started | Sep 01 07:39:56 AM UTC 24 |
| Finished | Sep 01 07:40:07 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201907777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3201907777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/3.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_sec_cm.1655162064 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 7707085737 ps |
| CPU time | 29.52 seconds |
| Started | Sep 01 07:40:42 AM UTC 24 |
| Finished | Sep 01 07:41:13 AM UTC 24 |
| Peak memory | 243484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655162064 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1655162064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/3.adc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_smoke.464724190 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 5883164053 ps |
| CPU time | 3.12 seconds |
| Started | Sep 01 07:38:54 AM UTC 24 |
| Finished | Sep 01 07:38:59 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464724190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.464724190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/3.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2664861602 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 8334139813 ps |
| CPU time | 15.2 seconds |
| Started | Sep 01 07:40:15 AM UTC 24 |
| Finished | Sep 01 07:40:31 AM UTC 24 |
| Peak memory | 221800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2664861602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 3.adc_ctrl_stress_all_with_rand_reset.2664861602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_alert_test.1863569913 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 391205808 ps |
| CPU time | 1.76 seconds |
| Started | Sep 01 08:23:50 AM UTC 24 |
| Finished | Sep 01 08:23:54 AM UTC 24 |
| Peak memory | 210040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863569913 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.1863569913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/30.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_both.3749352184 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 503202492117 ps |
| CPU time | 277.53 seconds |
| Started | Sep 01 08:23:17 AM UTC 24 |
| Finished | Sep 01 08:27:58 AM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749352184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.3749352184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/30.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_interrupt.2050236246 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 330501930869 ps |
| CPU time | 825.95 seconds |
| Started | Sep 01 08:23:01 AM UTC 24 |
| Finished | Sep 01 08:36:56 AM UTC 24 |
| Peak memory | 211424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050236246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2050236246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/30.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_interrupt_fixed.4123013499 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 486487208778 ps |
| CPU time | 604.32 seconds |
| Started | Sep 01 08:23:03 AM UTC 24 |
| Finished | Sep 01 08:33:14 AM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123013499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt_fixed.4123013499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/30.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_polled.3352782808 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 163011909491 ps |
| CPU time | 621.64 seconds |
| Started | Sep 01 08:22:41 AM UTC 24 |
| Finished | Sep 01 08:33:10 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352782808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.3352782808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/30.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_polled_fixed.966988852 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 331376659662 ps |
| CPU time | 103.16 seconds |
| Started | Sep 01 08:22:47 AM UTC 24 |
| Finished | Sep 01 08:24:32 AM UTC 24 |
| Peak memory | 211472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966988852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixed.966988852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/30.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_wakeup_fixed.340245876 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 609739721802 ps |
| CPU time | 846.8 seconds |
| Started | Sep 01 08:23:04 AM UTC 24 |
| Finished | Sep 01 08:37:19 AM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340245876 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_wakeup_fixed.340245876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/30.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_fsm_reset.3088702330 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 97388602281 ps |
| CPU time | 523.43 seconds |
| Started | Sep 01 08:23:44 AM UTC 24 |
| Finished | Sep 01 08:32:32 AM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088702330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.3088702330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/30.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_lowpower_counter.1170415326 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 46553663939 ps |
| CPU time | 66.76 seconds |
| Started | Sep 01 08:23:39 AM UTC 24 |
| Finished | Sep 01 08:24:47 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170415326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.1170415326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/30.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_poweron_counter.4256093384 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 3368662726 ps |
| CPU time | 16.03 seconds |
| Started | Sep 01 08:23:26 AM UTC 24 |
| Finished | Sep 01 08:23:43 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256093384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.4256093384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/30.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_smoke.2593174886 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 5705329070 ps |
| CPU time | 24.71 seconds |
| Started | Sep 01 08:22:37 AM UTC 24 |
| Finished | Sep 01 08:23:03 AM UTC 24 |
| Peak memory | 211484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593174886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2593174886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/30.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1686090292 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 35111750668 ps |
| CPU time | 37.57 seconds |
| Started | Sep 01 08:23:45 AM UTC 24 |
| Finished | Sep 01 08:24:24 AM UTC 24 |
| Peak memory | 221880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1686090292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 30.adc_ctrl_stress_all_with_rand_reset.1686090292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/30.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_alert_test.1026741587 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 503236668 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 08:25:24 AM UTC 24 |
| Finished | Sep 01 08:25:26 AM UTC 24 |
| Peak memory | 210040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026741587 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.1026741587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/31.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_clock_gating.2420832561 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 569191433896 ps |
| CPU time | 466.53 seconds |
| Started | Sep 01 08:24:33 AM UTC 24 |
| Finished | Sep 01 08:32:25 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420832561 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gating.2420832561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/31.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_both.2862007360 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 338386064282 ps |
| CPU time | 331.72 seconds |
| Started | Sep 01 08:24:48 AM UTC 24 |
| Finished | Sep 01 08:30:24 AM UTC 24 |
| Peak memory | 211472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862007360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2862007360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/31.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_interrupt.809464290 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 332373493629 ps |
| CPU time | 358.96 seconds |
| Started | Sep 01 08:24:15 AM UTC 24 |
| Finished | Sep 01 08:30:18 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809464290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.809464290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/31.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_interrupt_fixed.896129514 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 163828480024 ps |
| CPU time | 368.57 seconds |
| Started | Sep 01 08:24:18 AM UTC 24 |
| Finished | Sep 01 08:30:31 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896129514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt_fixed.896129514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/31.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_polled.4265083740 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 327243729939 ps |
| CPU time | 203.82 seconds |
| Started | Sep 01 08:23:56 AM UTC 24 |
| Finished | Sep 01 08:27:24 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265083740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.4265083740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/31.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_polled_fixed.1504554848 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 160854078210 ps |
| CPU time | 515.35 seconds |
| Started | Sep 01 08:24:04 AM UTC 24 |
| Finished | Sep 01 08:32:45 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504554848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixed.1504554848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/31.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1180709711 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 201314186902 ps |
| CPU time | 574.76 seconds |
| Started | Sep 01 08:24:25 AM UTC 24 |
| Finished | Sep 01 08:34:06 AM UTC 24 |
| Peak memory | 211748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180709711 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_wakeup_fixed.1180709711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/31.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_fsm_reset.2521660344 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 156528777692 ps |
| CPU time | 795.38 seconds |
| Started | Sep 01 08:25:00 AM UTC 24 |
| Finished | Sep 01 08:38:23 AM UTC 24 |
| Peak memory | 212024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521660344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2521660344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/31.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_lowpower_counter.2005720199 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 29829804110 ps |
| CPU time | 29.43 seconds |
| Started | Sep 01 08:24:59 AM UTC 24 |
| Finished | Sep 01 08:25:30 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005720199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2005720199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/31.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_poweron_counter.3738061425 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 4171990052 ps |
| CPU time | 10.54 seconds |
| Started | Sep 01 08:24:48 AM UTC 24 |
| Finished | Sep 01 08:25:00 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738061425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3738061425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/31.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_smoke.1997586 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 5573005307 ps |
| CPU time | 6.84 seconds |
| Started | Sep 01 08:23:54 AM UTC 24 |
| Finished | Sep 01 08:24:03 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_S EQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.1997586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/31.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_stress_all.3523118429 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 249069325333 ps |
| CPU time | 1481.09 seconds |
| Started | Sep 01 08:25:23 AM UTC 24 |
| Finished | Sep 01 08:50:18 AM UTC 24 |
| Peak memory | 223208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523118429 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.3523118429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/31.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.1235246919 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 188501028525 ps |
| CPU time | 29.27 seconds |
| Started | Sep 01 08:25:12 AM UTC 24 |
| Finished | Sep 01 08:25:43 AM UTC 24 |
| Peak memory | 221688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1235246919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 31.adc_ctrl_stress_all_with_rand_reset.1235246919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/31.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_alert_test.876162283 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 332796533 ps |
| CPU time | 2.24 seconds |
| Started | Sep 01 08:27:59 AM UTC 24 |
| Finished | Sep 01 08:28:03 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876162283 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.876162283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/32.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_clock_gating.1091108436 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 519416014570 ps |
| CPU time | 621.51 seconds |
| Started | Sep 01 08:27:17 AM UTC 24 |
| Finished | Sep 01 08:37:45 AM UTC 24 |
| Peak memory | 211680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091108436 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gating.1091108436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/32.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_both.2188860195 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 499469451865 ps |
| CPU time | 286.56 seconds |
| Started | Sep 01 08:27:24 AM UTC 24 |
| Finished | Sep 01 08:32:14 AM UTC 24 |
| Peak memory | 211480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188860195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2188860195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/32.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_interrupt.3603305696 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 328768505265 ps |
| CPU time | 176.04 seconds |
| Started | Sep 01 08:25:43 AM UTC 24 |
| Finished | Sep 01 08:28:42 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603305696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.3603305696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/32.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_interrupt_fixed.1616681900 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 332190139627 ps |
| CPU time | 855.4 seconds |
| Started | Sep 01 08:25:49 AM UTC 24 |
| Finished | Sep 01 08:40:13 AM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616681900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt_fixed.1616681900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/32.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_polled.4068498954 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 160117328976 ps |
| CPU time | 317.69 seconds |
| Started | Sep 01 08:25:30 AM UTC 24 |
| Finished | Sep 01 08:30:52 AM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068498954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.4068498954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/32.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_polled_fixed.2085976878 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 503434509853 ps |
| CPU time | 1486.07 seconds |
| Started | Sep 01 08:25:31 AM UTC 24 |
| Finished | Sep 01 08:50:32 AM UTC 24 |
| Peak memory | 212484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085976878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixed.2085976878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/32.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_wakeup.2412552621 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 429509248849 ps |
| CPU time | 1140.52 seconds |
| Started | Sep 01 08:26:12 AM UTC 24 |
| Finished | Sep 01 08:45:23 AM UTC 24 |
| Peak memory | 212548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412552621 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_wakeup.2412552621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/32.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_wakeup_fixed.1236852973 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 600889078911 ps |
| CPU time | 419.84 seconds |
| Started | Sep 01 08:26:33 AM UTC 24 |
| Finished | Sep 01 08:33:38 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236852973 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_wakeup_fixed.1236852973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/32.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_fsm_reset.3483783339 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 102116352087 ps |
| CPU time | 719.94 seconds |
| Started | Sep 01 08:27:54 AM UTC 24 |
| Finished | Sep 01 08:40:01 AM UTC 24 |
| Peak memory | 212084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483783339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.3483783339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/32.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_lowpower_counter.1357634518 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 24977386459 ps |
| CPU time | 23.15 seconds |
| Started | Sep 01 08:27:32 AM UTC 24 |
| Finished | Sep 01 08:27:57 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357634518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.1357634518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/32.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_poweron_counter.3459061286 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 4812623889 ps |
| CPU time | 5.87 seconds |
| Started | Sep 01 08:27:24 AM UTC 24 |
| Finished | Sep 01 08:27:31 AM UTC 24 |
| Peak memory | 211472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459061286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.3459061286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/32.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_smoke.2112754457 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 5761739301 ps |
| CPU time | 19.94 seconds |
| Started | Sep 01 08:25:27 AM UTC 24 |
| Finished | Sep 01 08:25:48 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112754457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2112754457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/32.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1679006305 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 15128811594 ps |
| CPU time | 24.82 seconds |
| Started | Sep 01 08:27:56 AM UTC 24 |
| Finished | Sep 01 08:28:22 AM UTC 24 |
| Peak memory | 221880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1679006305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 32.adc_ctrl_stress_all_with_rand_reset.1679006305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/32.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_alert_test.470857239 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 377880478 ps |
| CPU time | 1.58 seconds |
| Started | Sep 01 08:29:09 AM UTC 24 |
| Finished | Sep 01 08:29:11 AM UTC 24 |
| Peak memory | 209800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470857239 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.470857239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/33.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_clock_gating.4086161293 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 502120392007 ps |
| CPU time | 190.78 seconds |
| Started | Sep 01 08:28:34 AM UTC 24 |
| Finished | Sep 01 08:31:48 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086161293 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gating.4086161293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/33.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_both.1582355451 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 356952418762 ps |
| CPU time | 1057.64 seconds |
| Started | Sep 01 08:28:38 AM UTC 24 |
| Finished | Sep 01 08:46:28 AM UTC 24 |
| Peak memory | 212596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582355451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1582355451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/33.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_interrupt.1962862469 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 493336529056 ps |
| CPU time | 257.35 seconds |
| Started | Sep 01 08:28:14 AM UTC 24 |
| Finished | Sep 01 08:32:34 AM UTC 24 |
| Peak memory | 211500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962862469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.1962862469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/33.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_interrupt_fixed.657384794 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 160544366195 ps |
| CPU time | 525.53 seconds |
| Started | Sep 01 08:28:20 AM UTC 24 |
| Finished | Sep 01 08:37:11 AM UTC 24 |
| Peak memory | 211524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657384794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt_fixed.657384794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/33.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_polled.1861648067 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 332665326729 ps |
| CPU time | 272.31 seconds |
| Started | Sep 01 08:28:04 AM UTC 24 |
| Finished | Sep 01 08:32:39 AM UTC 24 |
| Peak memory | 211420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861648067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1861648067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/33.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_polled_fixed.3010010651 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 495474564029 ps |
| CPU time | 637.2 seconds |
| Started | Sep 01 08:28:06 AM UTC 24 |
| Finished | Sep 01 08:38:50 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010010651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixed.3010010651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/33.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_wakeup.1959421598 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 166852146605 ps |
| CPU time | 172.68 seconds |
| Started | Sep 01 08:28:22 AM UTC 24 |
| Finished | Sep 01 08:31:17 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959421598 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_wakeup.1959421598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/33.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1271992551 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 407380053391 ps |
| CPU time | 331.63 seconds |
| Started | Sep 01 08:28:23 AM UTC 24 |
| Finished | Sep 01 08:33:59 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271992551 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_wakeup_fixed.1271992551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/33.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_fsm_reset.1877236771 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 77828589251 ps |
| CPU time | 354.79 seconds |
| Started | Sep 01 08:28:56 AM UTC 24 |
| Finished | Sep 01 08:34:55 AM UTC 24 |
| Peak memory | 212032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877236771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1877236771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/33.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_lowpower_counter.3862958635 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 25327422150 ps |
| CPU time | 48.97 seconds |
| Started | Sep 01 08:28:52 AM UTC 24 |
| Finished | Sep 01 08:29:43 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862958635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3862958635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/33.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_poweron_counter.2856326750 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 5546953493 ps |
| CPU time | 7.09 seconds |
| Started | Sep 01 08:28:43 AM UTC 24 |
| Finished | Sep 01 08:28:52 AM UTC 24 |
| Peak memory | 211472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856326750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.2856326750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/33.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_smoke.3409243139 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 6099883390 ps |
| CPU time | 15.1 seconds |
| Started | Sep 01 08:28:03 AM UTC 24 |
| Finished | Sep 01 08:28:19 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409243139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.3409243139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/33.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_stress_all.2660957865 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 326457186148 ps |
| CPU time | 694.94 seconds |
| Started | Sep 01 08:29:08 AM UTC 24 |
| Finished | Sep 01 08:40:50 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660957865 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.2660957865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/33.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.4143120953 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 17611171091 ps |
| CPU time | 35.97 seconds |
| Started | Sep 01 08:29:04 AM UTC 24 |
| Finished | Sep 01 08:29:41 AM UTC 24 |
| Peak memory | 221964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4143120953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 33.adc_ctrl_stress_all_with_rand_reset.4143120953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/33.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_alert_test.3646126191 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 379024181 ps |
| CPU time | 1.64 seconds |
| Started | Sep 01 08:30:32 AM UTC 24 |
| Finished | Sep 01 08:30:36 AM UTC 24 |
| Peak memory | 209800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646126191 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.3646126191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/34.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_clock_gating.1458848882 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 353776026845 ps |
| CPU time | 563.32 seconds |
| Started | Sep 01 08:29:55 AM UTC 24 |
| Finished | Sep 01 08:39:25 AM UTC 24 |
| Peak memory | 211472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458848882 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gating.1458848882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/34.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_both.3796448949 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 176816776729 ps |
| CPU time | 139.9 seconds |
| Started | Sep 01 08:30:00 AM UTC 24 |
| Finished | Sep 01 08:32:22 AM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796448949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3796448949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/34.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_interrupt.4288740771 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 160375217982 ps |
| CPU time | 222.88 seconds |
| Started | Sep 01 08:29:42 AM UTC 24 |
| Finished | Sep 01 08:33:28 AM UTC 24 |
| Peak memory | 211608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288740771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.4288740771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/34.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1624669347 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 325255576742 ps |
| CPU time | 949.05 seconds |
| Started | Sep 01 08:29:42 AM UTC 24 |
| Finished | Sep 01 08:45:41 AM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624669347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt_fixed.1624669347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/34.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_polled.1312658854 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 492307238403 ps |
| CPU time | 1325.71 seconds |
| Started | Sep 01 08:29:18 AM UTC 24 |
| Finished | Sep 01 08:51:36 AM UTC 24 |
| Peak memory | 212492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312658854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1312658854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/34.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_polled_fixed.1318374316 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 489301360085 ps |
| CPU time | 1531.2 seconds |
| Started | Sep 01 08:29:33 AM UTC 24 |
| Finished | Sep 01 08:55:19 AM UTC 24 |
| Peak memory | 212488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318374316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixed.1318374316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/34.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_wakeup.2215155828 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 362351719468 ps |
| CPU time | 263.5 seconds |
| Started | Sep 01 08:29:44 AM UTC 24 |
| Finished | Sep 01 08:34:11 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215155828 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_wakeup.2215155828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/34.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3946967352 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 599400262272 ps |
| CPU time | 1561.25 seconds |
| Started | Sep 01 08:29:45 AM UTC 24 |
| Finished | Sep 01 08:56:01 AM UTC 24 |
| Peak memory | 212604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946967352 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_wakeup_fixed.3946967352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/34.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_fsm_reset.993182866 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 73395423067 ps |
| CPU time | 340.99 seconds |
| Started | Sep 01 08:30:19 AM UTC 24 |
| Finished | Sep 01 08:36:04 AM UTC 24 |
| Peak memory | 212020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993182866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.993182866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/34.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_lowpower_counter.2350709296 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 39546581442 ps |
| CPU time | 85.79 seconds |
| Started | Sep 01 08:30:19 AM UTC 24 |
| Finished | Sep 01 08:31:47 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350709296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.2350709296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/34.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_poweron_counter.440431808 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 2866395869 ps |
| CPU time | 4.23 seconds |
| Started | Sep 01 08:30:14 AM UTC 24 |
| Finished | Sep 01 08:30:19 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440431808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.440431808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/34.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_smoke.2627113610 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 6067271268 ps |
| CPU time | 3.97 seconds |
| Started | Sep 01 08:29:12 AM UTC 24 |
| Finished | Sep 01 08:29:17 AM UTC 24 |
| Peak memory | 211484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627113610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.2627113610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/34.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_stress_all.3509316441 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 447890207410 ps |
| CPU time | 554.88 seconds |
| Started | Sep 01 08:30:24 AM UTC 24 |
| Finished | Sep 01 08:39:45 AM UTC 24 |
| Peak memory | 211420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509316441 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.3509316441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/34.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_alert_test.1930877893 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 432751976 ps |
| CPU time | 1.67 seconds |
| Started | Sep 01 08:32:26 AM UTC 24 |
| Finished | Sep 01 08:32:28 AM UTC 24 |
| Peak memory | 209800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930877893 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1930877893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/35.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_clock_gating.3679730755 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 158382081992 ps |
| CPU time | 439.23 seconds |
| Started | Sep 01 08:31:47 AM UTC 24 |
| Finished | Sep 01 08:39:11 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679730755 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gating.3679730755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/35.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_both.3165547901 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 358674248737 ps |
| CPU time | 1241.4 seconds |
| Started | Sep 01 08:31:48 AM UTC 24 |
| Finished | Sep 01 08:52:42 AM UTC 24 |
| Peak memory | 212604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165547901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.3165547901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/35.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_interrupt.2135870254 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 160652676514 ps |
| CPU time | 459.72 seconds |
| Started | Sep 01 08:30:53 AM UTC 24 |
| Finished | Sep 01 08:38:38 AM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135870254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.2135870254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/35.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1156544493 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 495422036678 ps |
| CPU time | 370.68 seconds |
| Started | Sep 01 08:31:18 AM UTC 24 |
| Finished | Sep 01 08:37:33 AM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156544493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt_fixed.1156544493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/35.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_polled.3338484540 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 328131998051 ps |
| CPU time | 860.83 seconds |
| Started | Sep 01 08:30:38 AM UTC 24 |
| Finished | Sep 01 08:45:08 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338484540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.3338484540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/35.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_polled_fixed.1803040418 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 160464457122 ps |
| CPU time | 163.73 seconds |
| Started | Sep 01 08:30:52 AM UTC 24 |
| Finished | Sep 01 08:33:38 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803040418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixed.1803040418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/35.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_wakeup.3905215337 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 530180674070 ps |
| CPU time | 301.69 seconds |
| Started | Sep 01 08:31:21 AM UTC 24 |
| Finished | Sep 01 08:36:26 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905215337 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_wakeup.3905215337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/35.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_wakeup_fixed.3136853211 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 196542861060 ps |
| CPU time | 733.38 seconds |
| Started | Sep 01 08:31:23 AM UTC 24 |
| Finished | Sep 01 08:43:44 AM UTC 24 |
| Peak memory | 211484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136853211 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_wakeup_fixed.3136853211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/35.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_fsm_reset.4250957339 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 90743495260 ps |
| CPU time | 837.27 seconds |
| Started | Sep 01 08:32:12 AM UTC 24 |
| Finished | Sep 01 08:46:19 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250957339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.4250957339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/35.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_lowpower_counter.4134819866 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 29617212301 ps |
| CPU time | 105.17 seconds |
| Started | Sep 01 08:31:56 AM UTC 24 |
| Finished | Sep 01 08:33:43 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134819866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.4134819866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/35.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_poweron_counter.997621771 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 2767983480 ps |
| CPU time | 4.2 seconds |
| Started | Sep 01 08:31:50 AM UTC 24 |
| Finished | Sep 01 08:31:55 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997621771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.997621771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/35.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_smoke.3717980272 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 5933509795 ps |
| CPU time | 13.62 seconds |
| Started | Sep 01 08:30:36 AM UTC 24 |
| Finished | Sep 01 08:30:51 AM UTC 24 |
| Peak memory | 211292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717980272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.3717980272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/35.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_stress_all.3084907959 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 166434253214 ps |
| CPU time | 75.36 seconds |
| Started | Sep 01 08:32:23 AM UTC 24 |
| Finished | Sep 01 08:33:39 AM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084907959 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.3084907959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/35.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.3012913831 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 3446603554 ps |
| CPU time | 13.85 seconds |
| Started | Sep 01 08:32:14 AM UTC 24 |
| Finished | Sep 01 08:32:29 AM UTC 24 |
| Peak memory | 211596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3012913831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 35.adc_ctrl_stress_all_with_rand_reset.3012913831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/35.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_alert_test.358845223 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 350242126 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 08:33:32 AM UTC 24 |
| Finished | Sep 01 08:33:34 AM UTC 24 |
| Peak memory | 209800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358845223 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.358845223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/36.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_clock_gating.3095022819 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 169657288410 ps |
| CPU time | 13.79 seconds |
| Started | Sep 01 08:32:45 AM UTC 24 |
| Finished | Sep 01 08:33:00 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095022819 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gating.3095022819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/36.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_both.3112439976 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 599920652578 ps |
| CPU time | 414.34 seconds |
| Started | Sep 01 08:33:01 AM UTC 24 |
| Finished | Sep 01 08:40:00 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112439976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3112439976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/36.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_interrupt.2406648572 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 488709627837 ps |
| CPU time | 1595.18 seconds |
| Started | Sep 01 08:32:35 AM UTC 24 |
| Finished | Sep 01 08:59:26 AM UTC 24 |
| Peak memory | 212940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406648572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2406648572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/36.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_interrupt_fixed.1101608076 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 502312216663 ps |
| CPU time | 398.24 seconds |
| Started | Sep 01 08:32:38 AM UTC 24 |
| Finished | Sep 01 08:39:21 AM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101608076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt_fixed.1101608076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/36.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_polled.1236125389 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 328174850585 ps |
| CPU time | 263.24 seconds |
| Started | Sep 01 08:32:30 AM UTC 24 |
| Finished | Sep 01 08:36:56 AM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236125389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.1236125389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/36.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_polled_fixed.2607466036 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 164537598013 ps |
| CPU time | 238.55 seconds |
| Started | Sep 01 08:32:33 AM UTC 24 |
| Finished | Sep 01 08:36:34 AM UTC 24 |
| Peak memory | 211472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607466036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixed.2607466036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/36.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_wakeup.851790999 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 590596698737 ps |
| CPU time | 637.97 seconds |
| Started | Sep 01 08:32:39 AM UTC 24 |
| Finished | Sep 01 08:43:23 AM UTC 24 |
| Peak memory | 211472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851790999 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_wakeup.851790999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/36.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_wakeup_fixed.3387884325 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 594385708666 ps |
| CPU time | 129.42 seconds |
| Started | Sep 01 08:32:40 AM UTC 24 |
| Finished | Sep 01 08:34:52 AM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387884325 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_wakeup_fixed.3387884325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/36.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_fsm_reset.1804048584 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 95228488175 ps |
| CPU time | 443.53 seconds |
| Started | Sep 01 08:33:15 AM UTC 24 |
| Finished | Sep 01 08:40:43 AM UTC 24 |
| Peak memory | 211824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804048584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1804048584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/36.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_lowpower_counter.2538335644 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 44581063320 ps |
| CPU time | 44.63 seconds |
| Started | Sep 01 08:33:13 AM UTC 24 |
| Finished | Sep 01 08:33:59 AM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538335644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2538335644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/36.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_poweron_counter.3268708757 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 4297113300 ps |
| CPU time | 2.56 seconds |
| Started | Sep 01 08:33:10 AM UTC 24 |
| Finished | Sep 01 08:33:14 AM UTC 24 |
| Peak memory | 211536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268708757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.3268708757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/36.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_smoke.251519319 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 5740767283 ps |
| CPU time | 7.16 seconds |
| Started | Sep 01 08:32:29 AM UTC 24 |
| Finished | Sep 01 08:32:37 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251519319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.251519319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/36.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_stress_all.837327231 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 250026187286 ps |
| CPU time | 681.99 seconds |
| Started | Sep 01 08:33:29 AM UTC 24 |
| Finished | Sep 01 08:44:58 AM UTC 24 |
| Peak memory | 221868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837327231 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.837327231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/36.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2737940461 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 63712861796 ps |
| CPU time | 66.17 seconds |
| Started | Sep 01 08:33:15 AM UTC 24 |
| Finished | Sep 01 08:34:22 AM UTC 24 |
| Peak memory | 222268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2737940461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 36.adc_ctrl_stress_all_with_rand_reset.2737940461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/36.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_alert_test.1019578652 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 482150710 ps |
| CPU time | 2.89 seconds |
| Started | Sep 01 08:34:38 AM UTC 24 |
| Finished | Sep 01 08:34:42 AM UTC 24 |
| Peak memory | 211480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019578652 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.1019578652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/37.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_clock_gating.3149361451 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 332713685272 ps |
| CPU time | 73.3 seconds |
| Started | Sep 01 08:33:59 AM UTC 24 |
| Finished | Sep 01 08:35:14 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149361451 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gating.3149361451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/37.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_both.1326293365 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 341767685618 ps |
| CPU time | 221.37 seconds |
| Started | Sep 01 08:34:01 AM UTC 24 |
| Finished | Sep 01 08:37:45 AM UTC 24 |
| Peak memory | 211604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326293365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.1326293365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/37.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_interrupt.1577504535 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 163038580884 ps |
| CPU time | 157.8 seconds |
| Started | Sep 01 08:33:39 AM UTC 24 |
| Finished | Sep 01 08:36:19 AM UTC 24 |
| Peak memory | 211428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577504535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1577504535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/37.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_interrupt_fixed.242760694 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 485669977698 ps |
| CPU time | 1426.38 seconds |
| Started | Sep 01 08:33:40 AM UTC 24 |
| Finished | Sep 01 08:57:40 AM UTC 24 |
| Peak memory | 212540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242760694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt_fixed.242760694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/37.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_polled.1832723552 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 327542240388 ps |
| CPU time | 339.13 seconds |
| Started | Sep 01 08:33:35 AM UTC 24 |
| Finished | Sep 01 08:39:18 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832723552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1832723552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/37.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_polled_fixed.3959984508 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 490856615249 ps |
| CPU time | 287.11 seconds |
| Started | Sep 01 08:33:39 AM UTC 24 |
| Finished | Sep 01 08:38:30 AM UTC 24 |
| Peak memory | 211680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959984508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixed.3959984508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/37.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_wakeup.695198562 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 539413483256 ps |
| CPU time | 1623.84 seconds |
| Started | Sep 01 08:33:44 AM UTC 24 |
| Finished | Sep 01 09:01:04 AM UTC 24 |
| Peak memory | 212484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695198562 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_wakeup.695198562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/37.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2224034988 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 419270686511 ps |
| CPU time | 983.74 seconds |
| Started | Sep 01 08:33:59 AM UTC 24 |
| Finished | Sep 01 08:50:33 AM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224034988 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_wakeup_fixed.2224034988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/37.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_fsm_reset.1781193286 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 107181369381 ps |
| CPU time | 880.34 seconds |
| Started | Sep 01 08:34:12 AM UTC 24 |
| Finished | Sep 01 08:49:01 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781193286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.1781193286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/37.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_lowpower_counter.1793660310 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 46713493640 ps |
| CPU time | 55.62 seconds |
| Started | Sep 01 08:34:10 AM UTC 24 |
| Finished | Sep 01 08:35:07 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793660310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1793660310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/37.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_poweron_counter.4049901577 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 3987065002 ps |
| CPU time | 13.71 seconds |
| Started | Sep 01 08:34:07 AM UTC 24 |
| Finished | Sep 01 08:34:22 AM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049901577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.4049901577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/37.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_smoke.363121997 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 5972191796 ps |
| CPU time | 24.17 seconds |
| Started | Sep 01 08:33:34 AM UTC 24 |
| Finished | Sep 01 08:33:59 AM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363121997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.363121997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/37.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_stress_all.983074261 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 234662973300 ps |
| CPU time | 412.29 seconds |
| Started | Sep 01 08:34:23 AM UTC 24 |
| Finished | Sep 01 08:41:20 AM UTC 24 |
| Peak memory | 210928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983074261 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.983074261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/37.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.284249867 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 1369471688 ps |
| CPU time | 12.6 seconds |
| Started | Sep 01 08:34:23 AM UTC 24 |
| Finished | Sep 01 08:34:37 AM UTC 24 |
| Peak memory | 210952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=284249867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.284249867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/37.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_alert_test.2778809524 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 462549297 ps |
| CPU time | 1.69 seconds |
| Started | Sep 01 08:36:37 AM UTC 24 |
| Finished | Sep 01 08:36:40 AM UTC 24 |
| Peak memory | 209800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778809524 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.2778809524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/38.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_clock_gating.3625392378 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 527542283050 ps |
| CPU time | 993.78 seconds |
| Started | Sep 01 08:35:16 AM UTC 24 |
| Finished | Sep 01 08:52:00 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625392378 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gating.3625392378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/38.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_interrupt.1007307658 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 158258213107 ps |
| CPU time | 101.69 seconds |
| Started | Sep 01 08:34:52 AM UTC 24 |
| Finished | Sep 01 08:36:36 AM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007307658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.1007307658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/38.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1224882272 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 497930005172 ps |
| CPU time | 330.98 seconds |
| Started | Sep 01 08:34:56 AM UTC 24 |
| Finished | Sep 01 08:40:32 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224882272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt_fixed.1224882272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/38.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_polled.2868592385 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 323106079670 ps |
| CPU time | 1131.04 seconds |
| Started | Sep 01 08:34:49 AM UTC 24 |
| Finished | Sep 01 08:53:53 AM UTC 24 |
| Peak memory | 212824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868592385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.2868592385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/38.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_polled_fixed.3324823154 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 486476246120 ps |
| CPU time | 1620.54 seconds |
| Started | Sep 01 08:34:50 AM UTC 24 |
| Finished | Sep 01 09:02:08 AM UTC 24 |
| Peak memory | 212484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324823154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fixed.3324823154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/38.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_wakeup.3965483798 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 522845965804 ps |
| CPU time | 305.27 seconds |
| Started | Sep 01 08:35:08 AM UTC 24 |
| Finished | Sep 01 08:40:17 AM UTC 24 |
| Peak memory | 211740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965483798 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_wakeup.3965483798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/38.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3781327860 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 198472557237 ps |
| CPU time | 637.49 seconds |
| Started | Sep 01 08:35:08 AM UTC 24 |
| Finished | Sep 01 08:45:53 AM UTC 24 |
| Peak memory | 211748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781327860 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_wakeup_fixed.3781327860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/38.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_fsm_reset.779034328 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 96316483036 ps |
| CPU time | 531.05 seconds |
| Started | Sep 01 08:36:22 AM UTC 24 |
| Finished | Sep 01 08:45:19 AM UTC 24 |
| Peak memory | 212076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779034328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.779034328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/38.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_lowpower_counter.445489653 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 35289407043 ps |
| CPU time | 108.8 seconds |
| Started | Sep 01 08:36:20 AM UTC 24 |
| Finished | Sep 01 08:38:11 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445489653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.445489653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/38.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_poweron_counter.1410801170 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 3381891409 ps |
| CPU time | 14.8 seconds |
| Started | Sep 01 08:36:05 AM UTC 24 |
| Finished | Sep 01 08:36:21 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410801170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.1410801170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/38.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_smoke.1610736083 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 5810798987 ps |
| CPU time | 21.97 seconds |
| Started | Sep 01 08:34:43 AM UTC 24 |
| Finished | Sep 01 08:35:06 AM UTC 24 |
| Peak memory | 211484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610736083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1610736083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/38.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_stress_all.851184236 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 340788555404 ps |
| CPU time | 1098.82 seconds |
| Started | Sep 01 08:36:35 AM UTC 24 |
| Finished | Sep 01 08:55:05 AM UTC 24 |
| Peak memory | 212548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851184236 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.851184236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/38.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.2550951893 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 1749856580 ps |
| CPU time | 7.82 seconds |
| Started | Sep 01 08:36:27 AM UTC 24 |
| Finished | Sep 01 08:36:36 AM UTC 24 |
| Peak memory | 211268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2550951893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 38.adc_ctrl_stress_all_with_rand_reset.2550951893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/38.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_alert_test.4160794594 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 520595634 ps |
| CPU time | 2.74 seconds |
| Started | Sep 01 08:37:48 AM UTC 24 |
| Finished | Sep 01 08:37:52 AM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160794594 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.4160794594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/39.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_clock_gating.2900541524 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 188654133229 ps |
| CPU time | 24.01 seconds |
| Started | Sep 01 08:37:20 AM UTC 24 |
| Finished | Sep 01 08:37:45 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900541524 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gating.2900541524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/39.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_both.2306837075 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 190707324827 ps |
| CPU time | 320.33 seconds |
| Started | Sep 01 08:37:34 AM UTC 24 |
| Finished | Sep 01 08:42:58 AM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306837075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.2306837075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/39.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_interrupt.314513838 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 487886458534 ps |
| CPU time | 1009.61 seconds |
| Started | Sep 01 08:36:56 AM UTC 24 |
| Finished | Sep 01 08:53:56 AM UTC 24 |
| Peak memory | 211432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314513838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.314513838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/39.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_interrupt_fixed.1791530597 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 502261982340 ps |
| CPU time | 349.4 seconds |
| Started | Sep 01 08:36:57 AM UTC 24 |
| Finished | Sep 01 08:42:51 AM UTC 24 |
| Peak memory | 211536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791530597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt_fixed.1791530597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/39.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_polled.3040365100 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 168472510708 ps |
| CPU time | 96.58 seconds |
| Started | Sep 01 08:36:41 AM UTC 24 |
| Finished | Sep 01 08:38:20 AM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040365100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.3040365100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/39.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_polled_fixed.396804271 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 163028001641 ps |
| CPU time | 234.14 seconds |
| Started | Sep 01 08:36:44 AM UTC 24 |
| Finished | Sep 01 08:40:42 AM UTC 24 |
| Peak memory | 211544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396804271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixed.396804271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/39.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_wakeup.426149406 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 180055281565 ps |
| CPU time | 99.13 seconds |
| Started | Sep 01 08:37:04 AM UTC 24 |
| Finished | Sep 01 08:38:45 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426149406 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_wakeup.426149406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/39.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_wakeup_fixed.510274137 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 592975526347 ps |
| CPU time | 564.75 seconds |
| Started | Sep 01 08:37:13 AM UTC 24 |
| Finished | Sep 01 08:46:44 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510274137 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_wakeup_fixed.510274137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/39.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_lowpower_counter.4127849749 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 35635769461 ps |
| CPU time | 136.87 seconds |
| Started | Sep 01 08:37:45 AM UTC 24 |
| Finished | Sep 01 08:40:04 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127849749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.4127849749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/39.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_poweron_counter.1860279924 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 3311780255 ps |
| CPU time | 8.1 seconds |
| Started | Sep 01 08:37:35 AM UTC 24 |
| Finished | Sep 01 08:37:44 AM UTC 24 |
| Peak memory | 211408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860279924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1860279924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/39.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_smoke.979749369 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 5898162110 ps |
| CPU time | 5.21 seconds |
| Started | Sep 01 08:36:37 AM UTC 24 |
| Finished | Sep 01 08:36:44 AM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979749369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.979749369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/39.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_stress_all.2767845614 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 164970183283 ps |
| CPU time | 148.85 seconds |
| Started | Sep 01 08:37:46 AM UTC 24 |
| Finished | Sep 01 08:40:18 AM UTC 24 |
| Peak memory | 211684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767845614 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.2767845614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/39.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.554007582 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 6591398110 ps |
| CPU time | 8.55 seconds |
| Started | Sep 01 08:37:46 AM UTC 24 |
| Finished | Sep 01 08:37:56 AM UTC 24 |
| Peak memory | 211608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=554007582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.554007582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/39.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_alert_test.2429132187 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 477059542 ps |
| CPU time | 2.41 seconds |
| Started | Sep 01 07:43:15 AM UTC 24 |
| Finished | Sep 01 07:43:19 AM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429132187 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2429132187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/4.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_clock_gating.3071012140 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 540927121509 ps |
| CPU time | 1109.4 seconds |
| Started | Sep 01 07:41:42 AM UTC 24 |
| Finished | Sep 01 08:00:23 AM UTC 24 |
| Peak memory | 211684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071012140 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gating.3071012140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/4.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_both.1474839060 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 174101192864 ps |
| CPU time | 77.51 seconds |
| Started | Sep 01 07:42:36 AM UTC 24 |
| Finished | Sep 01 07:43:56 AM UTC 24 |
| Peak memory | 211564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474839060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.1474839060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/4.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt.2074972647 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 327713709990 ps |
| CPU time | 1141.72 seconds |
| Started | Sep 01 07:41:13 AM UTC 24 |
| Finished | Sep 01 08:00:26 AM UTC 24 |
| Peak memory | 211420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074972647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.2074972647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/4.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2465352119 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 328423604376 ps |
| CPU time | 339.68 seconds |
| Started | Sep 01 07:41:14 AM UTC 24 |
| Finished | Sep 01 07:46:57 AM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465352119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt_fixed.2465352119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/4.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled.650987358 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 503632379792 ps |
| CPU time | 1142.25 seconds |
| Started | Sep 01 07:40:50 AM UTC 24 |
| Finished | Sep 01 08:00:04 AM UTC 24 |
| Peak memory | 211680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650987358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.650987358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/4.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled_fixed.1097587695 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 328876488767 ps |
| CPU time | 244.27 seconds |
| Started | Sep 01 07:40:59 AM UTC 24 |
| Finished | Sep 01 07:45:07 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097587695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed.1097587695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/4.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3464495842 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 597134304288 ps |
| CPU time | 636.71 seconds |
| Started | Sep 01 07:41:38 AM UTC 24 |
| Finished | Sep 01 07:52:22 AM UTC 24 |
| Peak memory | 211492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464495842 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_wakeup_fixed.3464495842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/4.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_fsm_reset.1050275869 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 127455171313 ps |
| CPU time | 645.12 seconds |
| Started | Sep 01 07:42:47 AM UTC 24 |
| Finished | Sep 01 07:53:38 AM UTC 24 |
| Peak memory | 211808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050275869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.1050275869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/4.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_lowpower_counter.319133709 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 29916656247 ps |
| CPU time | 114.82 seconds |
| Started | Sep 01 07:42:46 AM UTC 24 |
| Finished | Sep 01 07:44:42 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319133709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.319133709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/4.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_poweron_counter.3781998607 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 3950805976 ps |
| CPU time | 2.91 seconds |
| Started | Sep 01 07:42:41 AM UTC 24 |
| Finished | Sep 01 07:42:45 AM UTC 24 |
| Peak memory | 211232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781998607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.3781998607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/4.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_sec_cm.972443479 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 8183450889 ps |
| CPU time | 31.17 seconds |
| Started | Sep 01 07:43:13 AM UTC 24 |
| Finished | Sep 01 07:43:46 AM UTC 24 |
| Peak memory | 243480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972443479 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.972443479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/4.adc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_smoke.2260536165 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 5951816245 ps |
| CPU time | 7.81 seconds |
| Started | Sep 01 07:40:49 AM UTC 24 |
| Finished | Sep 01 07:40:58 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260536165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2260536165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/4.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all.1196505985 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 327019995832 ps |
| CPU time | 298.44 seconds |
| Started | Sep 01 07:43:00 AM UTC 24 |
| Finished | Sep 01 07:48:03 AM UTC 24 |
| Peak memory | 211664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196505985 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.1196505985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.4195616227 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 20012272503 ps |
| CPU time | 13.38 seconds |
| Started | Sep 01 07:42:59 AM UTC 24 |
| Finished | Sep 01 07:43:14 AM UTC 24 |
| Peak memory | 221932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4195616227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 4.adc_ctrl_stress_all_with_rand_reset.4195616227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_alert_test.3537835361 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 509063565 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 08:39:19 AM UTC 24 |
| Finished | Sep 01 08:39:21 AM UTC 24 |
| Peak memory | 210040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537835361 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.3537835361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/40.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_clock_gating.3914680695 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 372592315961 ps |
| CPU time | 1100.43 seconds |
| Started | Sep 01 08:38:31 AM UTC 24 |
| Finished | Sep 01 08:57:03 AM UTC 24 |
| Peak memory | 212604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914680695 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gating.3914680695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/40.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_both.3440930101 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 324643965520 ps |
| CPU time | 966.68 seconds |
| Started | Sep 01 08:38:39 AM UTC 24 |
| Finished | Sep 01 08:54:55 AM UTC 24 |
| Peak memory | 211604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440930101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.3440930101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/40.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_interrupt.160646718 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 324848153614 ps |
| CPU time | 638.2 seconds |
| Started | Sep 01 08:38:21 AM UTC 24 |
| Finished | Sep 01 08:49:06 AM UTC 24 |
| Peak memory | 211428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160646718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.160646718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/40.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_interrupt_fixed.779186739 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 170311500406 ps |
| CPU time | 176.6 seconds |
| Started | Sep 01 08:38:21 AM UTC 24 |
| Finished | Sep 01 08:41:20 AM UTC 24 |
| Peak memory | 211740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779186739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt_fixed.779186739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/40.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_polled.163422442 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 327559021148 ps |
| CPU time | 491.39 seconds |
| Started | Sep 01 08:37:57 AM UTC 24 |
| Finished | Sep 01 08:46:14 AM UTC 24 |
| Peak memory | 211484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163422442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.163422442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/40.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_polled_fixed.2877901677 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 162214893225 ps |
| CPU time | 83.1 seconds |
| Started | Sep 01 08:38:12 AM UTC 24 |
| Finished | Sep 01 08:39:37 AM UTC 24 |
| Peak memory | 211480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877901677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixed.2877901677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/40.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_wakeup.3775978209 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 366037899476 ps |
| CPU time | 310.15 seconds |
| Started | Sep 01 08:38:24 AM UTC 24 |
| Finished | Sep 01 08:43:38 AM UTC 24 |
| Peak memory | 211684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775978209 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_wakeup.3775978209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/40.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_wakeup_fixed.3098993174 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 391879473462 ps |
| CPU time | 1313.72 seconds |
| Started | Sep 01 08:38:30 AM UTC 24 |
| Finished | Sep 01 09:00:37 AM UTC 24 |
| Peak memory | 212620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098993174 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_wakeup_fixed.3098993174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/40.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_fsm_reset.2219891544 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 117837652537 ps |
| CPU time | 775.38 seconds |
| Started | Sep 01 08:38:51 AM UTC 24 |
| Finished | Sep 01 08:51:55 AM UTC 24 |
| Peak memory | 211964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219891544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2219891544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/40.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_lowpower_counter.3707074518 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 29290928739 ps |
| CPU time | 19.95 seconds |
| Started | Sep 01 08:38:50 AM UTC 24 |
| Finished | Sep 01 08:39:11 AM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707074518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3707074518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/40.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_poweron_counter.2850050677 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 4164088107 ps |
| CPU time | 3.48 seconds |
| Started | Sep 01 08:38:45 AM UTC 24 |
| Finished | Sep 01 08:38:50 AM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850050677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.2850050677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/40.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_smoke.2677956964 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 5741795423 ps |
| CPU time | 26.19 seconds |
| Started | Sep 01 08:37:52 AM UTC 24 |
| Finished | Sep 01 08:38:20 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677956964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.2677956964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/40.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_stress_all.24523078 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 677892728787 ps |
| CPU time | 999.24 seconds |
| Started | Sep 01 08:39:12 AM UTC 24 |
| Finished | Sep 01 08:56:02 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24523078 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.24523078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/40.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.2484308015 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 5352620258 ps |
| CPU time | 32.22 seconds |
| Started | Sep 01 08:39:11 AM UTC 24 |
| Finished | Sep 01 08:39:45 AM UTC 24 |
| Peak memory | 221672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2484308015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 40.adc_ctrl_stress_all_with_rand_reset.2484308015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/40.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_alert_test.2647038832 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 379947491 ps |
| CPU time | 1.63 seconds |
| Started | Sep 01 08:40:05 AM UTC 24 |
| Finished | Sep 01 08:40:07 AM UTC 24 |
| Peak memory | 209980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647038832 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.2647038832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/41.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_both.3759446204 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 459208763066 ps |
| CPU time | 332.63 seconds |
| Started | Sep 01 08:39:46 AM UTC 24 |
| Finished | Sep 01 08:45:23 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759446204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.3759446204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/41.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_interrupt.1530940711 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 165177108946 ps |
| CPU time | 154.71 seconds |
| Started | Sep 01 08:39:26 AM UTC 24 |
| Finished | Sep 01 08:42:03 AM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530940711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.1530940711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/41.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3075587326 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 482794572590 ps |
| CPU time | 304.11 seconds |
| Started | Sep 01 08:39:38 AM UTC 24 |
| Finished | Sep 01 08:44:46 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075587326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt_fixed.3075587326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/41.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_polled.3805975724 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 161255302143 ps |
| CPU time | 456.33 seconds |
| Started | Sep 01 08:39:22 AM UTC 24 |
| Finished | Sep 01 08:47:03 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805975724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.3805975724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/41.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_polled_fixed.3605375385 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 492369411951 ps |
| CPU time | 560.56 seconds |
| Started | Sep 01 08:39:22 AM UTC 24 |
| Finished | Sep 01 08:48:48 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605375385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fixed.3605375385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/41.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_wakeup.4191679716 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 570760106068 ps |
| CPU time | 1008.44 seconds |
| Started | Sep 01 08:39:39 AM UTC 24 |
| Finished | Sep 01 08:56:38 AM UTC 24 |
| Peak memory | 211748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191679716 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_wakeup.4191679716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/41.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2839307534 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 585951830660 ps |
| CPU time | 1288.35 seconds |
| Started | Sep 01 08:39:42 AM UTC 24 |
| Finished | Sep 01 09:01:22 AM UTC 24 |
| Peak memory | 212628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839307534 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_wakeup_fixed.2839307534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/41.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_fsm_reset.3597447000 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 142640457283 ps |
| CPU time | 455.7 seconds |
| Started | Sep 01 08:39:57 AM UTC 24 |
| Finished | Sep 01 08:47:38 AM UTC 24 |
| Peak memory | 212032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597447000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3597447000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/41.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_lowpower_counter.2855322543 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 32856835594 ps |
| CPU time | 135.3 seconds |
| Started | Sep 01 08:39:51 AM UTC 24 |
| Finished | Sep 01 08:42:09 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855322543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.2855322543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/41.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_poweron_counter.3992022271 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 3858214491 ps |
| CPU time | 3.63 seconds |
| Started | Sep 01 08:39:46 AM UTC 24 |
| Finished | Sep 01 08:39:51 AM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992022271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.3992022271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/41.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_smoke.915504405 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 5838275660 ps |
| CPU time | 20.55 seconds |
| Started | Sep 01 08:39:20 AM UTC 24 |
| Finished | Sep 01 08:39:41 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915504405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.915504405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/41.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3501267347 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 4794082419 ps |
| CPU time | 19.24 seconds |
| Started | Sep 01 08:40:01 AM UTC 24 |
| Finished | Sep 01 08:40:22 AM UTC 24 |
| Peak memory | 222000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3501267347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 41.adc_ctrl_stress_all_with_rand_reset.3501267347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/41.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_alert_test.752872143 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 455543244 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 08:40:59 AM UTC 24 |
| Finished | Sep 01 08:41:01 AM UTC 24 |
| Peak memory | 209800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752872143 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.752872143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/42.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_clock_gating.2326656389 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 166996013383 ps |
| CPU time | 293.07 seconds |
| Started | Sep 01 08:40:32 AM UTC 24 |
| Finished | Sep 01 08:45:29 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326656389 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gating.2326656389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/42.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_both.1625688732 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 514956931901 ps |
| CPU time | 1506.93 seconds |
| Started | Sep 01 08:40:42 AM UTC 24 |
| Finished | Sep 01 09:06:04 AM UTC 24 |
| Peak memory | 212560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625688732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.1625688732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/42.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_interrupt_fixed.1455376648 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 492720666099 ps |
| CPU time | 1479.99 seconds |
| Started | Sep 01 08:40:19 AM UTC 24 |
| Finished | Sep 01 09:05:14 AM UTC 24 |
| Peak memory | 212664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455376648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt_fixed.1455376648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/42.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_polled.2767279051 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 491413272200 ps |
| CPU time | 377.98 seconds |
| Started | Sep 01 08:40:14 AM UTC 24 |
| Finished | Sep 01 08:46:36 AM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767279051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.2767279051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/42.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_polled_fixed.2429871286 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 163471370433 ps |
| CPU time | 129.01 seconds |
| Started | Sep 01 08:40:18 AM UTC 24 |
| Finished | Sep 01 08:42:29 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429871286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixed.2429871286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/42.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_wakeup.3116769466 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 372583108806 ps |
| CPU time | 244.23 seconds |
| Started | Sep 01 08:40:23 AM UTC 24 |
| Finished | Sep 01 08:44:31 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116769466 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_wakeup.3116769466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/42.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3710940417 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 593162567594 ps |
| CPU time | 546.22 seconds |
| Started | Sep 01 08:40:32 AM UTC 24 |
| Finished | Sep 01 08:49:45 AM UTC 24 |
| Peak memory | 211544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710940417 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_wakeup_fixed.3710940417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/42.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_fsm_reset.3826514432 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 121681301294 ps |
| CPU time | 674.13 seconds |
| Started | Sep 01 08:40:49 AM UTC 24 |
| Finished | Sep 01 08:52:10 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826514432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.3826514432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/42.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_lowpower_counter.4286690084 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 40249882989 ps |
| CPU time | 49.64 seconds |
| Started | Sep 01 08:40:43 AM UTC 24 |
| Finished | Sep 01 08:41:35 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286690084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.4286690084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/42.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_poweron_counter.3665366151 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 3173806645 ps |
| CPU time | 13.46 seconds |
| Started | Sep 01 08:40:43 AM UTC 24 |
| Finished | Sep 01 08:40:58 AM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665366151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3665366151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/42.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_smoke.3969384088 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 6066261801 ps |
| CPU time | 9.12 seconds |
| Started | Sep 01 08:40:08 AM UTC 24 |
| Finished | Sep 01 08:40:18 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969384088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3969384088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/42.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_stress_all.3635691022 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 362717251988 ps |
| CPU time | 314.47 seconds |
| Started | Sep 01 08:40:56 AM UTC 24 |
| Finished | Sep 01 08:46:14 AM UTC 24 |
| Peak memory | 211676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635691022 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.3635691022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/42.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2555229052 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 2235977669 ps |
| CPU time | 3.17 seconds |
| Started | Sep 01 08:40:51 AM UTC 24 |
| Finished | Sep 01 08:40:55 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2555229052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 42.adc_ctrl_stress_all_with_rand_reset.2555229052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/42.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_alert_test.3598021028 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 305360814 ps |
| CPU time | 1.17 seconds |
| Started | Sep 01 08:43:24 AM UTC 24 |
| Finished | Sep 01 08:43:27 AM UTC 24 |
| Peak memory | 209800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598021028 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.3598021028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/43.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_clock_gating.3050286 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 177877008476 ps |
| CPU time | 138.38 seconds |
| Started | Sep 01 08:42:04 AM UTC 24 |
| Finished | Sep 01 08:44:24 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050286 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gating.3050286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/43.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_interrupt.748271111 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 490507541562 ps |
| CPU time | 375.54 seconds |
| Started | Sep 01 08:41:21 AM UTC 24 |
| Finished | Sep 01 08:47:41 AM UTC 24 |
| Peak memory | 211756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748271111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.748271111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/43.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1573536649 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 486380930333 ps |
| CPU time | 289.72 seconds |
| Started | Sep 01 08:41:35 AM UTC 24 |
| Finished | Sep 01 08:46:29 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573536649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt_fixed.1573536649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/43.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_polled.1980524593 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 170315978692 ps |
| CPU time | 540.54 seconds |
| Started | Sep 01 08:41:16 AM UTC 24 |
| Finished | Sep 01 08:50:24 AM UTC 24 |
| Peak memory | 211748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980524593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.1980524593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/43.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_polled_fixed.3729489661 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 492357307575 ps |
| CPU time | 105.28 seconds |
| Started | Sep 01 08:41:20 AM UTC 24 |
| Finished | Sep 01 08:43:08 AM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729489661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixed.3729489661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/43.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_wakeup.2824158650 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 177551277111 ps |
| CPU time | 186.84 seconds |
| Started | Sep 01 08:41:47 AM UTC 24 |
| Finished | Sep 01 08:44:57 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824158650 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_wakeup.2824158650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/43.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1882280089 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 392567803015 ps |
| CPU time | 1208.43 seconds |
| Started | Sep 01 08:42:03 AM UTC 24 |
| Finished | Sep 01 09:02:23 AM UTC 24 |
| Peak memory | 212628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882280089 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_wakeup_fixed.1882280089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/43.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_fsm_reset.296419801 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 123703947298 ps |
| CPU time | 949.19 seconds |
| Started | Sep 01 08:42:52 AM UTC 24 |
| Finished | Sep 01 08:58:51 AM UTC 24 |
| Peak memory | 212024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296419801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.296419801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/43.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_lowpower_counter.3243354163 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 29138690904 ps |
| CPU time | 71.49 seconds |
| Started | Sep 01 08:42:40 AM UTC 24 |
| Finished | Sep 01 08:43:53 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243354163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.3243354163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/43.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_poweron_counter.3090253716 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 4745557215 ps |
| CPU time | 8.23 seconds |
| Started | Sep 01 08:42:30 AM UTC 24 |
| Finished | Sep 01 08:42:39 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090253716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3090253716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/43.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_smoke.657777621 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 5645982778 ps |
| CPU time | 12.11 seconds |
| Started | Sep 01 08:41:02 AM UTC 24 |
| Finished | Sep 01 08:41:15 AM UTC 24 |
| Peak memory | 211472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657777621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.657777621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/43.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.2965303688 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 14761048958 ps |
| CPU time | 22.62 seconds |
| Started | Sep 01 08:42:59 AM UTC 24 |
| Finished | Sep 01 08:43:23 AM UTC 24 |
| Peak memory | 227952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2965303688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 43.adc_ctrl_stress_all_with_rand_reset.2965303688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/43.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_alert_test.286217007 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 442824840 ps |
| CPU time | 1.33 seconds |
| Started | Sep 01 08:45:09 AM UTC 24 |
| Finished | Sep 01 08:45:11 AM UTC 24 |
| Peak memory | 210040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286217007 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.286217007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/44.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_both.2111381706 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 169896338396 ps |
| CPU time | 110.25 seconds |
| Started | Sep 01 08:44:47 AM UTC 24 |
| Finished | Sep 01 08:46:39 AM UTC 24 |
| Peak memory | 211480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111381706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2111381706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/44.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_interrupt.820381207 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 327911928019 ps |
| CPU time | 275.63 seconds |
| Started | Sep 01 08:43:40 AM UTC 24 |
| Finished | Sep 01 08:48:19 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820381207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.820381207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/44.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_interrupt_fixed.4026070368 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 164381534264 ps |
| CPU time | 101.08 seconds |
| Started | Sep 01 08:43:45 AM UTC 24 |
| Finished | Sep 01 08:45:28 AM UTC 24 |
| Peak memory | 211456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026070368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt_fixed.4026070368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/44.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_polled.2509623325 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 162900823840 ps |
| CPU time | 226.32 seconds |
| Started | Sep 01 08:43:27 AM UTC 24 |
| Finished | Sep 01 08:47:17 AM UTC 24 |
| Peak memory | 211748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509623325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.2509623325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/44.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_polled_fixed.932203977 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 337538642513 ps |
| CPU time | 904.93 seconds |
| Started | Sep 01 08:43:39 AM UTC 24 |
| Finished | Sep 01 08:58:53 AM UTC 24 |
| Peak memory | 211472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932203977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixed.932203977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/44.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_wakeup.3409500672 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 202812016194 ps |
| CPU time | 593.19 seconds |
| Started | Sep 01 08:43:54 AM UTC 24 |
| Finished | Sep 01 08:53:53 AM UTC 24 |
| Peak memory | 211680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409500672 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_wakeup.3409500672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/44.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_wakeup_fixed.3231772348 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 604033110756 ps |
| CPU time | 538.8 seconds |
| Started | Sep 01 08:44:25 AM UTC 24 |
| Finished | Sep 01 08:53:30 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231772348 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_wakeup_fixed.3231772348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/44.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_fsm_reset.3976122736 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 97819499810 ps |
| CPU time | 831.49 seconds |
| Started | Sep 01 08:45:02 AM UTC 24 |
| Finished | Sep 01 08:59:03 AM UTC 24 |
| Peak memory | 211892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976122736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.3976122736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/44.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_lowpower_counter.3389428016 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 28777015563 ps |
| CPU time | 83.1 seconds |
| Started | Sep 01 08:44:59 AM UTC 24 |
| Finished | Sep 01 08:46:24 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389428016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.3389428016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/44.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_poweron_counter.2108047579 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 3975756509 ps |
| CPU time | 5.13 seconds |
| Started | Sep 01 08:44:58 AM UTC 24 |
| Finished | Sep 01 08:45:04 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108047579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2108047579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/44.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_smoke.2571092570 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 5830259700 ps |
| CPU time | 13.35 seconds |
| Started | Sep 01 08:43:24 AM UTC 24 |
| Finished | Sep 01 08:43:39 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571092570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.2571092570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/44.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_stress_all.3545145301 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 174220315102 ps |
| CPU time | 525.47 seconds |
| Started | Sep 01 08:45:09 AM UTC 24 |
| Finished | Sep 01 08:54:00 AM UTC 24 |
| Peak memory | 211484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545145301 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.3545145301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/44.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.256225272 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 11193515225 ps |
| CPU time | 12.86 seconds |
| Started | Sep 01 08:45:06 AM UTC 24 |
| Finished | Sep 01 08:45:20 AM UTC 24 |
| Peak memory | 211684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=256225272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.256225272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/44.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_alert_test.937770163 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 423912062 ps |
| CPU time | 1.32 seconds |
| Started | Sep 01 08:46:20 AM UTC 24 |
| Finished | Sep 01 08:46:22 AM UTC 24 |
| Peak memory | 209800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937770163 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.937770163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/45.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_clock_gating.2906997925 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 345599279418 ps |
| CPU time | 309.28 seconds |
| Started | Sep 01 08:45:30 AM UTC 24 |
| Finished | Sep 01 08:50:44 AM UTC 24 |
| Peak memory | 211604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906997925 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gating.2906997925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/45.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_both.2744803997 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 164596094521 ps |
| CPU time | 154.36 seconds |
| Started | Sep 01 08:45:41 AM UTC 24 |
| Finished | Sep 01 08:48:18 AM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744803997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.2744803997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/45.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_interrupt_fixed.2088208889 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 325155736122 ps |
| CPU time | 261.72 seconds |
| Started | Sep 01 08:45:24 AM UTC 24 |
| Finished | Sep 01 08:49:49 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088208889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt_fixed.2088208889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/45.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_polled.3459874767 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 325915438996 ps |
| CPU time | 567.64 seconds |
| Started | Sep 01 08:45:20 AM UTC 24 |
| Finished | Sep 01 08:54:54 AM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459874767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3459874767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/45.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_polled_fixed.814390674 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 490774960843 ps |
| CPU time | 1452.92 seconds |
| Started | Sep 01 08:45:21 AM UTC 24 |
| Finished | Sep 01 09:09:48 AM UTC 24 |
| Peak memory | 212464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814390674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixed.814390674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/45.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_wakeup.554902924 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 370547463955 ps |
| CPU time | 468.7 seconds |
| Started | Sep 01 08:45:24 AM UTC 24 |
| Finished | Sep 01 08:53:18 AM UTC 24 |
| Peak memory | 211544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554902924 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_wakeup.554902924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/45.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_wakeup_fixed.3731251009 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 194783607500 ps |
| CPU time | 62.55 seconds |
| Started | Sep 01 08:45:28 AM UTC 24 |
| Finished | Sep 01 08:46:32 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731251009 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_wakeup_fixed.3731251009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/45.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_fsm_reset.3639630167 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 87213158736 ps |
| CPU time | 490.84 seconds |
| Started | Sep 01 08:46:10 AM UTC 24 |
| Finished | Sep 01 08:54:26 AM UTC 24 |
| Peak memory | 211904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639630167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.3639630167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/45.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_lowpower_counter.2606478565 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 27086798026 ps |
| CPU time | 59.63 seconds |
| Started | Sep 01 08:45:59 AM UTC 24 |
| Finished | Sep 01 08:47:00 AM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606478565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2606478565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/45.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_poweron_counter.2329729322 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 3494389446 ps |
| CPU time | 3.67 seconds |
| Started | Sep 01 08:45:53 AM UTC 24 |
| Finished | Sep 01 08:45:58 AM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329729322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2329729322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/45.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_smoke.141880177 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 5879869674 ps |
| CPU time | 9.95 seconds |
| Started | Sep 01 08:45:12 AM UTC 24 |
| Finished | Sep 01 08:45:23 AM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141880177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.141880177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/45.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_stress_all.4070186661 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 289567228906 ps |
| CPU time | 476.74 seconds |
| Started | Sep 01 08:46:15 AM UTC 24 |
| Finished | Sep 01 08:54:17 AM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070186661 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all.4070186661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/45.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.3308912898 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 2147724386 ps |
| CPU time | 10.33 seconds |
| Started | Sep 01 08:46:15 AM UTC 24 |
| Finished | Sep 01 08:46:26 AM UTC 24 |
| Peak memory | 221724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3308912898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 45.adc_ctrl_stress_all_with_rand_reset.3308912898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/45.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_alert_test.1699962592 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 404501267 ps |
| CPU time | 1.61 seconds |
| Started | Sep 01 08:47:06 AM UTC 24 |
| Finished | Sep 01 08:47:09 AM UTC 24 |
| Peak memory | 209800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699962592 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1699962592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/46.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_clock_gating.3500648473 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 187206979473 ps |
| CPU time | 244.41 seconds |
| Started | Sep 01 08:46:33 AM UTC 24 |
| Finished | Sep 01 08:50:41 AM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500648473 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gating.3500648473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/46.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_both.2066113874 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 322504668502 ps |
| CPU time | 1014.02 seconds |
| Started | Sep 01 08:46:37 AM UTC 24 |
| Finished | Sep 01 09:03:43 AM UTC 24 |
| Peak memory | 212880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066113874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.2066113874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/46.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_interrupt.2535358729 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 323325668720 ps |
| CPU time | 982.92 seconds |
| Started | Sep 01 08:46:27 AM UTC 24 |
| Finished | Sep 01 09:03:00 AM UTC 24 |
| Peak memory | 212556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535358729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.2535358729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/46.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_interrupt_fixed.2409179708 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 505184029785 ps |
| CPU time | 297.94 seconds |
| Started | Sep 01 08:46:29 AM UTC 24 |
| Finished | Sep 01 08:51:31 AM UTC 24 |
| Peak memory | 211464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409179708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt_fixed.2409179708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/46.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_polled.3638695156 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 490857399617 ps |
| CPU time | 394.57 seconds |
| Started | Sep 01 08:46:23 AM UTC 24 |
| Finished | Sep 01 08:53:02 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638695156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3638695156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/46.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_polled_fixed.23159006 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 163540095777 ps |
| CPU time | 129.47 seconds |
| Started | Sep 01 08:46:25 AM UTC 24 |
| Finished | Sep 01 08:48:37 AM UTC 24 |
| Peak memory | 211384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23159006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas e_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fixed.23159006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/46.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_wakeup_fixed.2960951197 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 381764494541 ps |
| CPU time | 645.67 seconds |
| Started | Sep 01 08:46:33 AM UTC 24 |
| Finished | Sep 01 08:57:26 AM UTC 24 |
| Peak memory | 211620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960951197 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_wakeup_fixed.2960951197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/46.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_fsm_reset.4194633078 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 97542577803 ps |
| CPU time | 804.58 seconds |
| Started | Sep 01 08:46:57 AM UTC 24 |
| Finished | Sep 01 09:00:30 AM UTC 24 |
| Peak memory | 211816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194633078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.4194633078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/46.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_lowpower_counter.2431752311 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 35057660780 ps |
| CPU time | 10.39 seconds |
| Started | Sep 01 08:46:45 AM UTC 24 |
| Finished | Sep 01 08:46:56 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431752311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2431752311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/46.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_poweron_counter.2718851140 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 5212730896 ps |
| CPU time | 23.16 seconds |
| Started | Sep 01 08:46:41 AM UTC 24 |
| Finished | Sep 01 08:47:05 AM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718851140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2718851140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/46.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_smoke.2269552202 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 6055208303 ps |
| CPU time | 11.48 seconds |
| Started | Sep 01 08:46:20 AM UTC 24 |
| Finished | Sep 01 08:46:32 AM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269552202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.2269552202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/46.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_stress_all.1763395075 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 350772354923 ps |
| CPU time | 824.64 seconds |
| Started | Sep 01 08:47:04 AM UTC 24 |
| Finished | Sep 01 09:00:57 AM UTC 24 |
| Peak memory | 221728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763395075 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.1763395075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/46.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_alert_test.453826188 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 478517617 ps |
| CPU time | 1.37 seconds |
| Started | Sep 01 08:49:06 AM UTC 24 |
| Finished | Sep 01 08:49:09 AM UTC 24 |
| Peak memory | 210340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453826188 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.453826188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/47.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_clock_gating.2809168429 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 586148553229 ps |
| CPU time | 293.63 seconds |
| Started | Sep 01 08:48:20 AM UTC 24 |
| Finished | Sep 01 08:53:17 AM UTC 24 |
| Peak memory | 211604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809168429 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gating.2809168429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/47.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_both.2998131817 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 498908301546 ps |
| CPU time | 1398.67 seconds |
| Started | Sep 01 08:48:36 AM UTC 24 |
| Finished | Sep 01 09:12:09 AM UTC 24 |
| Peak memory | 212748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998131817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.2998131817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/47.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_interrupt.1334552153 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 491064855360 ps |
| CPU time | 1322.17 seconds |
| Started | Sep 01 08:47:35 AM UTC 24 |
| Finished | Sep 01 09:09:51 AM UTC 24 |
| Peak memory | 212540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334552153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.1334552153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/47.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_interrupt_fixed.3409714247 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 162151826520 ps |
| CPU time | 173.44 seconds |
| Started | Sep 01 08:47:38 AM UTC 24 |
| Finished | Sep 01 08:50:34 AM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409714247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt_fixed.3409714247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/47.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_polled.2094009202 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 326872455305 ps |
| CPU time | 448.92 seconds |
| Started | Sep 01 08:47:18 AM UTC 24 |
| Finished | Sep 01 08:54:52 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094009202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2094009202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/47.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_polled_fixed.470943636 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 497470082381 ps |
| CPU time | 1494.18 seconds |
| Started | Sep 01 08:47:35 AM UTC 24 |
| Finished | Sep 01 09:12:45 AM UTC 24 |
| Peak memory | 212616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470943636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixed.470943636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/47.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_wakeup.3234805000 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 370474985242 ps |
| CPU time | 798.69 seconds |
| Started | Sep 01 08:47:42 AM UTC 24 |
| Finished | Sep 01 09:01:09 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234805000 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_wakeup.3234805000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/47.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1879645603 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 194866437794 ps |
| CPU time | 208.68 seconds |
| Started | Sep 01 08:48:19 AM UTC 24 |
| Finished | Sep 01 08:51:50 AM UTC 24 |
| Peak memory | 211392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879645603 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_wakeup_fixed.1879645603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/47.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_fsm_reset.2407367813 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 102125421569 ps |
| CPU time | 775.03 seconds |
| Started | Sep 01 08:48:49 AM UTC 24 |
| Finished | Sep 01 09:01:52 AM UTC 24 |
| Peak memory | 211824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407367813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.2407367813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/47.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_lowpower_counter.3334796 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 42202312494 ps |
| CPU time | 47.41 seconds |
| Started | Sep 01 08:48:43 AM UTC 24 |
| Finished | Sep 01 08:49:32 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_S EQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3334796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/47.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_poweron_counter.186879975 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 3960684912 ps |
| CPU time | 3.01 seconds |
| Started | Sep 01 08:48:38 AM UTC 24 |
| Finished | Sep 01 08:48:42 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186879975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.186879975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/47.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_smoke.90326592 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 5644873915 ps |
| CPU time | 24.44 seconds |
| Started | Sep 01 08:47:09 AM UTC 24 |
| Finished | Sep 01 08:47:35 AM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90326592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_ SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.90326592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/47.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_stress_all.2372911406 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 816871977692 ps |
| CPU time | 1075.37 seconds |
| Started | Sep 01 08:49:02 AM UTC 24 |
| Finished | Sep 01 09:07:09 AM UTC 24 |
| Peak memory | 212592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372911406 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.2372911406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/47.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.3119895816 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 3858097984 ps |
| CPU time | 4.74 seconds |
| Started | Sep 01 08:49:00 AM UTC 24 |
| Finished | Sep 01 08:49:06 AM UTC 24 |
| Peak memory | 211332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3119895816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 47.adc_ctrl_stress_all_with_rand_reset.3119895816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/47.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_alert_test.752992732 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 303658234 ps |
| CPU time | 2.11 seconds |
| Started | Sep 01 08:50:48 AM UTC 24 |
| Finished | Sep 01 08:50:51 AM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752992732 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.752992732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/48.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_clock_gating.2423887757 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 360037557953 ps |
| CPU time | 569.92 seconds |
| Started | Sep 01 08:50:19 AM UTC 24 |
| Finished | Sep 01 08:59:55 AM UTC 24 |
| Peak memory | 211544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423887757 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gating.2423887757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/48.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_both.3767529407 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 166865252799 ps |
| CPU time | 525.5 seconds |
| Started | Sep 01 08:50:24 AM UTC 24 |
| Finished | Sep 01 08:59:16 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767529407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.3767529407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/48.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_interrupt.2477446832 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 165505661324 ps |
| CPU time | 380.71 seconds |
| Started | Sep 01 08:49:33 AM UTC 24 |
| Finished | Sep 01 08:55:58 AM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477446832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.2477446832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/48.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_interrupt_fixed.4066361371 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 497051332190 ps |
| CPU time | 714.46 seconds |
| Started | Sep 01 08:49:46 AM UTC 24 |
| Finished | Sep 01 09:01:48 AM UTC 24 |
| Peak memory | 211588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066361371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt_fixed.4066361371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/48.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_polled.1538795740 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 166048950398 ps |
| CPU time | 431.5 seconds |
| Started | Sep 01 08:49:09 AM UTC 24 |
| Finished | Sep 01 08:56:26 AM UTC 24 |
| Peak memory | 211424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538795740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.1538795740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/48.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_polled_fixed.3197194570 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 165217168984 ps |
| CPU time | 317.37 seconds |
| Started | Sep 01 08:49:14 AM UTC 24 |
| Finished | Sep 01 08:54:35 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197194570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixed.3197194570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/48.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_wakeup.564531816 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 393576565859 ps |
| CPU time | 117.42 seconds |
| Started | Sep 01 08:49:50 AM UTC 24 |
| Finished | Sep 01 08:51:50 AM UTC 24 |
| Peak memory | 211484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564531816 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_wakeup.564531816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/48.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3719428031 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 395469606122 ps |
| CPU time | 152.87 seconds |
| Started | Sep 01 08:49:55 AM UTC 24 |
| Finished | Sep 01 08:52:30 AM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719428031 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_wakeup_fixed.3719428031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/48.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_fsm_reset.3618025510 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 101986588005 ps |
| CPU time | 449.52 seconds |
| Started | Sep 01 08:50:35 AM UTC 24 |
| Finished | Sep 01 08:58:10 AM UTC 24 |
| Peak memory | 211972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618025510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3618025510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/48.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_lowpower_counter.3954987278 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 33813789525 ps |
| CPU time | 56.89 seconds |
| Started | Sep 01 08:50:34 AM UTC 24 |
| Finished | Sep 01 08:51:33 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954987278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3954987278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/48.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_poweron_counter.3866831455 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 3040138102 ps |
| CPU time | 12.97 seconds |
| Started | Sep 01 08:50:33 AM UTC 24 |
| Finished | Sep 01 08:50:47 AM UTC 24 |
| Peak memory | 211472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866831455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.3866831455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/48.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_smoke.1260700365 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 5778100043 ps |
| CPU time | 5.19 seconds |
| Started | Sep 01 08:49:06 AM UTC 24 |
| Finished | Sep 01 08:49:13 AM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260700365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1260700365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/48.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_stress_all.2324540999 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 120290032188 ps |
| CPU time | 547.3 seconds |
| Started | Sep 01 08:50:45 AM UTC 24 |
| Finished | Sep 01 08:59:58 AM UTC 24 |
| Peak memory | 221868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324540999 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.2324540999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/48.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.4078029350 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 1521610424 ps |
| CPU time | 17.69 seconds |
| Started | Sep 01 08:50:42 AM UTC 24 |
| Finished | Sep 01 08:51:01 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4078029350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 48.adc_ctrl_stress_all_with_rand_reset.4078029350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/48.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_alert_test.2908731993 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 482734111 ps |
| CPU time | 1.81 seconds |
| Started | Sep 01 08:52:31 AM UTC 24 |
| Finished | Sep 01 08:52:34 AM UTC 24 |
| Peak memory | 209800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908731993 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.2908731993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/49.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_clock_gating.3962280233 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 160376310950 ps |
| CPU time | 121.05 seconds |
| Started | Sep 01 08:51:50 AM UTC 24 |
| Finished | Sep 01 08:53:53 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962280233 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gating.3962280233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/49.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_both.2174382735 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 489167059827 ps |
| CPU time | 476.82 seconds |
| Started | Sep 01 08:51:51 AM UTC 24 |
| Finished | Sep 01 08:59:54 AM UTC 24 |
| Peak memory | 211536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174382735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2174382735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/49.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt.2217545851 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 490944937412 ps |
| CPU time | 144.6 seconds |
| Started | Sep 01 08:51:32 AM UTC 24 |
| Finished | Sep 01 08:53:59 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217545851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.2217545851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/49.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3069093514 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 487854220034 ps |
| CPU time | 1406.84 seconds |
| Started | Sep 01 08:51:33 AM UTC 24 |
| Finished | Sep 01 09:15:14 AM UTC 24 |
| Peak memory | 212468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069093514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt_fixed.3069093514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/49.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_polled.3663726983 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 171283212901 ps |
| CPU time | 175.1 seconds |
| Started | Sep 01 08:51:02 AM UTC 24 |
| Finished | Sep 01 08:54:00 AM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663726983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.3663726983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/49.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_polled_fixed.4116366252 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 487791959390 ps |
| CPU time | 1546.73 seconds |
| Started | Sep 01 08:51:02 AM UTC 24 |
| Finished | Sep 01 09:17:06 AM UTC 24 |
| Peak memory | 212812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116366252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixed.4116366252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/49.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_wakeup.980468216 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 163330319075 ps |
| CPU time | 149.35 seconds |
| Started | Sep 01 08:51:33 AM UTC 24 |
| Finished | Sep 01 08:54:05 AM UTC 24 |
| Peak memory | 211676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980468216 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_wakeup.980468216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/49.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1820438390 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 201619423842 ps |
| CPU time | 93.12 seconds |
| Started | Sep 01 08:51:37 AM UTC 24 |
| Finished | Sep 01 08:53:12 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820438390 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_wakeup_fixed.1820438390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/49.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_fsm_reset.4183403900 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 116151098677 ps |
| CPU time | 537.92 seconds |
| Started | Sep 01 08:52:02 AM UTC 24 |
| Finished | Sep 01 09:01:06 AM UTC 24 |
| Peak memory | 211840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183403900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.4183403900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/49.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_lowpower_counter.2958152001 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 29598415137 ps |
| CPU time | 30.91 seconds |
| Started | Sep 01 08:52:01 AM UTC 24 |
| Finished | Sep 01 08:52:33 AM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958152001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.2958152001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/49.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_poweron_counter.2652689808 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 4508241629 ps |
| CPU time | 4.65 seconds |
| Started | Sep 01 08:51:56 AM UTC 24 |
| Finished | Sep 01 08:52:01 AM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652689808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2652689808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/49.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_smoke.580986505 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 5742126233 ps |
| CPU time | 7.36 seconds |
| Started | Sep 01 08:50:52 AM UTC 24 |
| Finished | Sep 01 08:51:01 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580986505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.580986505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/49.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_stress_all.1255268025 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 170925889238 ps |
| CPU time | 163.15 seconds |
| Started | Sep 01 08:52:27 AM UTC 24 |
| Finished | Sep 01 08:55:13 AM UTC 24 |
| Peak memory | 211408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255268025 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.1255268025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/49.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_alert_test.3477494377 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 297225263 ps |
| CPU time | 1.56 seconds |
| Started | Sep 01 07:45:08 AM UTC 24 |
| Finished | Sep 01 07:45:11 AM UTC 24 |
| Peak memory | 210336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477494377 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.3477494377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/5.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_both.253615067 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 181842634946 ps |
| CPU time | 577.29 seconds |
| Started | Sep 01 07:44:21 AM UTC 24 |
| Finished | Sep 01 07:54:05 AM UTC 24 |
| Peak memory | 211536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253615067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.253615067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/5.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt.2528905678 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 495110135624 ps |
| CPU time | 749.97 seconds |
| Started | Sep 01 07:43:27 AM UTC 24 |
| Finished | Sep 01 07:56:05 AM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528905678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.2528905678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/5.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3125481862 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 482839310802 ps |
| CPU time | 1020.2 seconds |
| Started | Sep 01 07:43:42 AM UTC 24 |
| Finished | Sep 01 08:00:54 AM UTC 24 |
| Peak memory | 211408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125481862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt_fixed.3125481862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/5.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled.1327788113 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 327681458950 ps |
| CPU time | 555.6 seconds |
| Started | Sep 01 07:43:19 AM UTC 24 |
| Finished | Sep 01 07:52:41 AM UTC 24 |
| Peak memory | 211500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327788113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.1327788113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/5.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled_fixed.2106913542 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 494894164582 ps |
| CPU time | 1692.61 seconds |
| Started | Sep 01 07:43:26 AM UTC 24 |
| Finished | Sep 01 08:11:55 AM UTC 24 |
| Peak memory | 211616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106913542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed.2106913542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/5.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup.1836086793 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 161577160083 ps |
| CPU time | 343.81 seconds |
| Started | Sep 01 07:43:47 AM UTC 24 |
| Finished | Sep 01 07:49:35 AM UTC 24 |
| Peak memory | 211544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836086793 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_wakeup.1836086793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/5.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1729073526 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 202742087823 ps |
| CPU time | 787.18 seconds |
| Started | Sep 01 07:43:57 AM UTC 24 |
| Finished | Sep 01 07:57:12 AM UTC 24 |
| Peak memory | 211492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729073526 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_wakeup_fixed.1729073526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/5.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_fsm_reset.1539664087 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 103269004105 ps |
| CPU time | 523.7 seconds |
| Started | Sep 01 07:44:43 AM UTC 24 |
| Finished | Sep 01 07:53:32 AM UTC 24 |
| Peak memory | 212020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539664087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.1539664087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/5.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_lowpower_counter.1900252478 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 37776857940 ps |
| CPU time | 61.98 seconds |
| Started | Sep 01 07:44:42 AM UTC 24 |
| Finished | Sep 01 07:45:45 AM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900252478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1900252478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/5.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_poweron_counter.3819977508 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 4499077290 ps |
| CPU time | 13.38 seconds |
| Started | Sep 01 07:44:40 AM UTC 24 |
| Finished | Sep 01 07:44:55 AM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819977508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3819977508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/5.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_smoke.818728869 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 5689227244 ps |
| CPU time | 6.8 seconds |
| Started | Sep 01 07:43:17 AM UTC 24 |
| Finished | Sep 01 07:43:25 AM UTC 24 |
| Peak memory | 211472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818728869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.818728869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/5.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all.1900952853 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 79988827905 ps |
| CPU time | 61.55 seconds |
| Started | Sep 01 07:45:07 AM UTC 24 |
| Finished | Sep 01 07:46:10 AM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900952853 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.1900952853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1904331140 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 2898446737 ps |
| CPU time | 16.35 seconds |
| Started | Sep 01 07:44:55 AM UTC 24 |
| Finished | Sep 01 07:45:13 AM UTC 24 |
| Peak memory | 222008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1904331140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 5.adc_ctrl_stress_all_with_rand_reset.1904331140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_alert_test.140937479 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 289011808 ps |
| CPU time | 2.2 seconds |
| Started | Sep 01 07:46:27 AM UTC 24 |
| Finished | Sep 01 07:46:30 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140937479 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.140937479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/6.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_clock_gating.769212570 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 191735091271 ps |
| CPU time | 92.29 seconds |
| Started | Sep 01 07:45:39 AM UTC 24 |
| Finished | Sep 01 07:47:13 AM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769212570 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gating.769212570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/6.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.4029884200 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 161809173865 ps |
| CPU time | 126.52 seconds |
| Started | Sep 01 07:45:14 AM UTC 24 |
| Finished | Sep 01 07:47:22 AM UTC 24 |
| Peak memory | 211420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029884200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.4029884200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/6.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt_fixed.2824218135 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 162599838883 ps |
| CPU time | 259.36 seconds |
| Started | Sep 01 07:45:19 AM UTC 24 |
| Finished | Sep 01 07:49:42 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824218135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt_fixed.2824218135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/6.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled.993063403 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 167191735249 ps |
| CPU time | 110.87 seconds |
| Started | Sep 01 07:45:12 AM UTC 24 |
| Finished | Sep 01 07:47:04 AM UTC 24 |
| Peak memory | 211744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993063403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.993063403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/6.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled_fixed.913779584 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 330424169320 ps |
| CPU time | 312.56 seconds |
| Started | Sep 01 07:45:13 AM UTC 24 |
| Finished | Sep 01 07:50:29 AM UTC 24 |
| Peak memory | 211464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913779584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixed.913779584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/6.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup.209412764 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 668409683670 ps |
| CPU time | 841.57 seconds |
| Started | Sep 01 07:45:38 AM UTC 24 |
| Finished | Sep 01 07:59:48 AM UTC 24 |
| Peak memory | 211484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209412764 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_wakeup.209412764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/6.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup_fixed.3567570184 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 191757242227 ps |
| CPU time | 587.7 seconds |
| Started | Sep 01 07:45:39 AM UTC 24 |
| Finished | Sep 01 07:55:33 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567570184 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_wakeup_fixed.3567570184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/6.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_fsm_reset.853761135 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 122519520516 ps |
| CPU time | 941.68 seconds |
| Started | Sep 01 07:46:02 AM UTC 24 |
| Finished | Sep 01 08:01:55 AM UTC 24 |
| Peak memory | 211968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853761135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.853761135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/6.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_lowpower_counter.2271083211 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 23612727297 ps |
| CPU time | 51.08 seconds |
| Started | Sep 01 07:45:52 AM UTC 24 |
| Finished | Sep 01 07:46:45 AM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271083211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.2271083211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/6.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_poweron_counter.535353026 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 2984094514 ps |
| CPU time | 13.43 seconds |
| Started | Sep 01 07:45:46 AM UTC 24 |
| Finished | Sep 01 07:46:02 AM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535353026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.535353026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/6.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_smoke.2164443413 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 6032383955 ps |
| CPU time | 7.91 seconds |
| Started | Sep 01 07:45:09 AM UTC 24 |
| Finished | Sep 01 07:45:18 AM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164443413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2164443413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/6.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all.3164327523 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 32483254864 ps |
| CPU time | 36.32 seconds |
| Started | Sep 01 07:46:12 AM UTC 24 |
| Finished | Sep 01 07:46:49 AM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164327523 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.3164327523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/6.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.2391865230 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 16991110925 ps |
| CPU time | 37.26 seconds |
| Started | Sep 01 07:46:03 AM UTC 24 |
| Finished | Sep 01 07:46:42 AM UTC 24 |
| Peak memory | 228164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2391865230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 6.adc_ctrl_stress_all_with_rand_reset.2391865230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/6.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_alert_test.1510884563 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 516975641 ps |
| CPU time | 2.89 seconds |
| Started | Sep 01 07:47:21 AM UTC 24 |
| Finished | Sep 01 07:47:25 AM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510884563 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.1510884563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/7.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt.3356154791 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 163906249933 ps |
| CPU time | 307.12 seconds |
| Started | Sep 01 07:46:43 AM UTC 24 |
| Finished | Sep 01 07:51:54 AM UTC 24 |
| Peak memory | 211420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356154791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.3356154791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/7.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2513712790 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 162815579138 ps |
| CPU time | 197.16 seconds |
| Started | Sep 01 07:46:46 AM UTC 24 |
| Finished | Sep 01 07:50:06 AM UTC 24 |
| Peak memory | 211420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513712790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt_fixed.2513712790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/7.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled.1897614122 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 337960403262 ps |
| CPU time | 508.35 seconds |
| Started | Sep 01 07:46:41 AM UTC 24 |
| Finished | Sep 01 07:55:15 AM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897614122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.1897614122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/7.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled_fixed.2367271574 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 162739460140 ps |
| CPU time | 340.13 seconds |
| Started | Sep 01 07:46:43 AM UTC 24 |
| Finished | Sep 01 07:52:27 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367271574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed.2367271574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/7.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup.4289049879 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 171280436984 ps |
| CPU time | 242.44 seconds |
| Started | Sep 01 07:46:50 AM UTC 24 |
| Finished | Sep 01 07:50:56 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289049879 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_wakeup.4289049879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/7.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1225449676 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 601216304635 ps |
| CPU time | 1997.65 seconds |
| Started | Sep 01 07:46:55 AM UTC 24 |
| Finished | Sep 01 08:20:33 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225449676 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_wakeup_fixed.1225449676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/7.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_fsm_reset.2169994489 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 81355649839 ps |
| CPU time | 479.79 seconds |
| Started | Sep 01 07:47:14 AM UTC 24 |
| Finished | Sep 01 07:55:19 AM UTC 24 |
| Peak memory | 212028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169994489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.2169994489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/7.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_lowpower_counter.3204932337 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 36339349720 ps |
| CPU time | 24.96 seconds |
| Started | Sep 01 07:47:09 AM UTC 24 |
| Finished | Sep 01 07:47:35 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204932337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.3204932337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/7.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_poweron_counter.3406576960 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 3156369841 ps |
| CPU time | 13.96 seconds |
| Started | Sep 01 07:47:06 AM UTC 24 |
| Finished | Sep 01 07:47:22 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406576960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.3406576960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/7.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_smoke.3430166995 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 5792869693 ps |
| CPU time | 8.16 seconds |
| Started | Sep 01 07:46:31 AM UTC 24 |
| Finished | Sep 01 07:46:40 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430166995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.3430166995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/7.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all.1508745171 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 331576636053 ps |
| CPU time | 839.23 seconds |
| Started | Sep 01 07:47:20 AM UTC 24 |
| Finished | Sep 01 08:01:27 AM UTC 24 |
| Peak memory | 211480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508745171 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.1508745171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.233797471 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 19228177936 ps |
| CPU time | 30.22 seconds |
| Started | Sep 01 07:47:19 AM UTC 24 |
| Finished | Sep 01 07:47:50 AM UTC 24 |
| Peak memory | 228356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=233797471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.233797471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_alert_test.1037373557 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 495690517 ps |
| CPU time | 2.86 seconds |
| Started | Sep 01 07:48:53 AM UTC 24 |
| Finished | Sep 01 07:48:57 AM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037373557 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1037373557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/8.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_clock_gating.1034048919 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 189379772648 ps |
| CPU time | 50.45 seconds |
| Started | Sep 01 07:48:01 AM UTC 24 |
| Finished | Sep 01 07:48:52 AM UTC 24 |
| Peak memory | 211744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034048919 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gating.1034048919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/8.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_both.456457324 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 541363555899 ps |
| CPU time | 1642.94 seconds |
| Started | Sep 01 07:48:04 AM UTC 24 |
| Finished | Sep 01 08:15:42 AM UTC 24 |
| Peak memory | 211480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456457324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.456457324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/8.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt.1467157167 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 330305699190 ps |
| CPU time | 1125.38 seconds |
| Started | Sep 01 07:47:26 AM UTC 24 |
| Finished | Sep 01 08:06:23 AM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467157167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1467157167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/8.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2261006904 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 497745207686 ps |
| CPU time | 1634.05 seconds |
| Started | Sep 01 07:47:33 AM UTC 24 |
| Finished | Sep 01 08:15:03 AM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261006904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt_fixed.2261006904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/8.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled.82756661 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 334115949855 ps |
| CPU time | 503.56 seconds |
| Started | Sep 01 07:47:23 AM UTC 24 |
| Finished | Sep 01 07:55:53 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82756661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_ SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.82756661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/8.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled_fixed.1400027820 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 324179524569 ps |
| CPU time | 589.11 seconds |
| Started | Sep 01 07:47:23 AM UTC 24 |
| Finished | Sep 01 07:57:19 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400027820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed.1400027820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/8.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup.4154912642 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 184964455709 ps |
| CPU time | 331.81 seconds |
| Started | Sep 01 07:47:36 AM UTC 24 |
| Finished | Sep 01 07:53:12 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154912642 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_wakeup.4154912642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/8.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1083258927 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 408957830186 ps |
| CPU time | 728.94 seconds |
| Started | Sep 01 07:47:52 AM UTC 24 |
| Finished | Sep 01 08:00:09 AM UTC 24 |
| Peak memory | 211464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083258927 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_wakeup_fixed.1083258927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/8.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_fsm_reset.2291108915 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 76051731987 ps |
| CPU time | 255.54 seconds |
| Started | Sep 01 07:48:28 AM UTC 24 |
| Finished | Sep 01 07:52:47 AM UTC 24 |
| Peak memory | 211744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291108915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2291108915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/8.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_lowpower_counter.1721103030 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 46250897392 ps |
| CPU time | 29.42 seconds |
| Started | Sep 01 07:48:26 AM UTC 24 |
| Finished | Sep 01 07:48:57 AM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721103030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.1721103030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/8.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_poweron_counter.1774825979 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 3117170994 ps |
| CPU time | 4.76 seconds |
| Started | Sep 01 07:48:24 AM UTC 24 |
| Finished | Sep 01 07:48:30 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774825979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.1774825979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/8.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_smoke.2121943334 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 5594368768 ps |
| CPU time | 8.85 seconds |
| Started | Sep 01 07:47:22 AM UTC 24 |
| Finished | Sep 01 07:47:32 AM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121943334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.2121943334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/8.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all.515336205 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 190551838734 ps |
| CPU time | 614.22 seconds |
| Started | Sep 01 07:48:48 AM UTC 24 |
| Finished | Sep 01 07:59:09 AM UTC 24 |
| Peak memory | 211668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515336205 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.515336205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/8.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3455598690 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 3214956311 ps |
| CPU time | 14.83 seconds |
| Started | Sep 01 07:48:31 AM UTC 24 |
| Finished | Sep 01 07:48:47 AM UTC 24 |
| Peak memory | 222024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3455598690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 8.adc_ctrl_stress_all_with_rand_reset.3455598690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/8.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_alert_test.3324081022 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 320976725 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 07:52:02 AM UTC 24 |
| Finished | Sep 01 07:52:04 AM UTC 24 |
| Peak memory | 209796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324081022 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3324081022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/9.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_clock_gating.2302605216 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 633201467781 ps |
| CPU time | 1022.73 seconds |
| Started | Sep 01 07:50:30 AM UTC 24 |
| Finished | Sep 01 08:07:43 AM UTC 24 |
| Peak memory | 211420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302605216 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gating.2302605216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/9.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_both.2732351672 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 190087900179 ps |
| CPU time | 143.63 seconds |
| Started | Sep 01 07:50:56 AM UTC 24 |
| Finished | Sep 01 07:53:22 AM UTC 24 |
| Peak memory | 211536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732351672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2732351672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/9.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt.3379344047 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 496011249491 ps |
| CPU time | 1578.23 seconds |
| Started | Sep 01 07:49:33 AM UTC 24 |
| Finished | Sep 01 08:16:06 AM UTC 24 |
| Peak memory | 211736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379344047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3379344047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/9.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2346941320 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 484701394226 ps |
| CPU time | 941.41 seconds |
| Started | Sep 01 07:49:36 AM UTC 24 |
| Finished | Sep 01 08:05:26 AM UTC 24 |
| Peak memory | 211408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346941320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt_fixed.2346941320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/9.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled.2132051802 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 163721567487 ps |
| CPU time | 500.38 seconds |
| Started | Sep 01 07:48:58 AM UTC 24 |
| Finished | Sep 01 07:57:24 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132051802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2132051802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/9.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled_fixed.2623502602 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 327790748548 ps |
| CPU time | 554.44 seconds |
| Started | Sep 01 07:49:08 AM UTC 24 |
| Finished | Sep 01 07:58:28 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623502602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed.2623502602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/9.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup.279985462 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 167553771292 ps |
| CPU time | 110.31 seconds |
| Started | Sep 01 07:49:42 AM UTC 24 |
| Finished | Sep 01 07:51:34 AM UTC 24 |
| Peak memory | 211420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279985462 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_wakeup.279985462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/9.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1525685546 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 588605452625 ps |
| CPU time | 138.39 seconds |
| Started | Sep 01 07:50:07 AM UTC 24 |
| Finished | Sep 01 07:52:28 AM UTC 24 |
| Peak memory | 211492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525685546 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_wakeup_fixed.1525685546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/9.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.1486689852 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 124867766469 ps |
| CPU time | 751.64 seconds |
| Started | Sep 01 07:51:35 AM UTC 24 |
| Finished | Sep 01 08:04:15 AM UTC 24 |
| Peak memory | 211736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486689852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.1486689852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/9.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_lowpower_counter.1737799789 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 26212184393 ps |
| CPU time | 24.8 seconds |
| Started | Sep 01 07:51:35 AM UTC 24 |
| Finished | Sep 01 07:52:01 AM UTC 24 |
| Peak memory | 211144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737799789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.1737799789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/9.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_poweron_counter.2728989361 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 2969133389 ps |
| CPU time | 2.4 seconds |
| Started | Sep 01 07:51:31 AM UTC 24 |
| Finished | Sep 01 07:51:34 AM UTC 24 |
| Peak memory | 211224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728989361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.2728989361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/9.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_smoke.677699781 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 5569066742 ps |
| CPU time | 8.08 seconds |
| Started | Sep 01 07:48:57 AM UTC 24 |
| Finished | Sep 01 07:49:07 AM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677699781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.677699781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/9.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all.1531920091 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 332765538763 ps |
| CPU time | 583.27 seconds |
| Started | Sep 01 07:51:55 AM UTC 24 |
| Finished | Sep 01 08:01:45 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531920091 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.1531920091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |