Unified Coverage Report :: Module :: adc_ctrl_reg_top

Module : adc_ctrl_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.85	100.00	99.40			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.96	98.97	96.02	100.00		98.76	96.05

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_chn0_filter_ctl_0_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn0_filter_ctl_0_cond_0	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_0_en_0	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_0_max_v_0	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_0_min_v_0	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_1_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn0_filter_ctl_1_cond_1	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_1_en_1	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_1_max_v_1	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_1_min_v_1	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_2_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn0_filter_ctl_2_cond_2	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_2_en_2	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_2_max_v_2	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_2_min_v_2	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_3_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn0_filter_ctl_3_cond_3	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_3_en_3	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_3_max_v_3	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_3_min_v_3	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_4_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn0_filter_ctl_4_cond_4	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_4_en_4	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_4_max_v_4	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_4_min_v_4	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_5_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn0_filter_ctl_5_cond_5	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_5_en_5	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_5_max_v_5	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_5_min_v_5	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_6_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn0_filter_ctl_6_cond_6	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_6_en_6	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_6_max_v_6	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_6_min_v_6	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_7_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn0_filter_ctl_7_cond_7	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_7_en_7	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_7_max_v_7	100.00	100.00	100.00			100.00
u_adc_chn0_filter_ctl_7_min_v_7	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_0_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn1_filter_ctl_0_cond_0	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_0_en_0	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_0_max_v_0	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_0_min_v_0	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_1_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn1_filter_ctl_1_cond_1	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_1_en_1	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_1_max_v_1	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_1_min_v_1	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_2_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn1_filter_ctl_2_cond_2	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_2_en_2	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_2_max_v_2	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_2_min_v_2	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_3_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn1_filter_ctl_3_cond_3	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_3_en_3	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_3_max_v_3	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_3_min_v_3	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_4_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn1_filter_ctl_4_cond_4	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_4_en_4	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_4_max_v_4	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_4_min_v_4	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_5_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn1_filter_ctl_5_cond_5	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_5_en_5	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_5_max_v_5	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_5_min_v_5	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_6_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn1_filter_ctl_6_cond_6	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_6_en_6	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_6_max_v_6	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_6_min_v_6	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_7_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_chn1_filter_ctl_7_cond_7	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_7_en_7	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_7_max_v_7	100.00	100.00	100.00			100.00
u_adc_chn1_filter_ctl_7_min_v_7	100.00	100.00	100.00			100.00
u_adc_chn_val_0_adc_chn_value_0	100.00	100.00	100.00			100.00
u_adc_chn_val_0_adc_chn_value_ext_0	87.50	62.50	100.00			100.00
u_adc_chn_val_0_adc_chn_value_intr_0	100.00	100.00	100.00			100.00
u_adc_chn_val_0_adc_chn_value_intr_ext_0	87.50	62.50	100.00			100.00
u_adc_chn_val_0_cdc	78.01	95.31	67.24			89.47	60.00
u_adc_chn_val_1_adc_chn_value_1	100.00	100.00	100.00			100.00
u_adc_chn_val_1_adc_chn_value_ext_1	87.50	62.50	100.00			100.00
u_adc_chn_val_1_adc_chn_value_intr_1	100.00	100.00	100.00			100.00
u_adc_chn_val_1_adc_chn_value_intr_ext_1	87.50	62.50	100.00			100.00
u_adc_chn_val_1_cdc	78.01	95.31	67.24			89.47	60.00
u_adc_en_ctl_adc_enable	100.00	100.00	100.00			100.00
u_adc_en_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_en_ctl_oneshot_mode	100.00	100.00	100.00			100.00
u_adc_fsm_rst	100.00	100.00	100.00			100.00
u_adc_fsm_rst_cdc	99.22	100.00	96.88			100.00	100.00
u_adc_fsm_state	100.00	100.00
u_adc_fsm_state_cdc	90.72	98.44	79.69			94.74	90.00
u_adc_intr_ctl_match_en	100.00	100.00	100.00			100.00
u_adc_intr_ctl_oneshot_en	100.00	100.00	100.00			100.00
u_adc_intr_ctl_trans_en	100.00	100.00	100.00			100.00
u_adc_intr_status_match	100.00	100.00	100.00			100.00
u_adc_intr_status_oneshot	100.00	100.00	100.00			100.00
u_adc_intr_status_trans	100.00	100.00	100.00			100.00
u_adc_lp_sample_ctl	100.00	100.00	100.00			100.00
u_adc_lp_sample_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_pd_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_pd_ctl_lp_mode	100.00	100.00	100.00			100.00
u_adc_pd_ctl_pwrup_time	100.00	100.00	100.00			100.00
u_adc_pd_ctl_wakeup_time	100.00	100.00	100.00			100.00
u_adc_sample_ctl	100.00	100.00	100.00			100.00
u_adc_sample_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_wakeup_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_adc_wakeup_ctl_match_en	100.00	100.00	100.00			100.00
u_adc_wakeup_ctl_trans_en	100.00	100.00	100.00			100.00
u_alert_test	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_filter_status_cdc	97.74	100.00	92.65			98.31	100.00
u_filter_status_match	100.00	100.00	100.00			100.00
u_filter_status_trans	100.00	100.00	100.00			100.00
u_intr_enable	100.00	100.00	100.00			100.00
u_intr_state	62.59	77.78	50.00			60.00
u_intr_test	100.00	100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.98	97.14	98.80			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00

Line Coverage for Module : adc_ctrl_reg_top

	Line No.	Total	Covered	Percent
TOTAL		340	340	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
ALWAYS	235	3	3	100.00
CONT_ASSIGN	264	1	1	100.00
ALWAYS	276	4	4	100.00
CONT_ASSIGN	306	1	1	100.00
ALWAYS	316	2	2	100.00
CONT_ASSIGN	344	1	1	100.00
ALWAYS	354	2	2	100.00
CONT_ASSIGN	382	1	1	100.00
ALWAYS	392	2	2	100.00
CONT_ASSIGN	420	1	1	100.00
ALWAYS	433	5	5	100.00
CONT_ASSIGN	464	1	1	100.00
ALWAYS	477	5	5	100.00
CONT_ASSIGN	508	1	1	100.00
ALWAYS	521	5	5	100.00
CONT_ASSIGN	552	1	1	100.00
ALWAYS	565	5	5	100.00
CONT_ASSIGN	596	1	1	100.00
ALWAYS	609	5	5	100.00
CONT_ASSIGN	640	1	1	100.00
ALWAYS	653	5	5	100.00
CONT_ASSIGN	684	1	1	100.00
ALWAYS	697	5	5	100.00
CONT_ASSIGN	728	1	1	100.00
ALWAYS	741	5	5	100.00
CONT_ASSIGN	772	1	1	100.00
ALWAYS	785	5	5	100.00
CONT_ASSIGN	816	1	1	100.00
ALWAYS	829	5	5	100.00
CONT_ASSIGN	860	1	1	100.00
ALWAYS	873	5	5	100.00
CONT_ASSIGN	904	1	1	100.00
ALWAYS	917	5	5	100.00
CONT_ASSIGN	948	1	1	100.00
ALWAYS	961	5	5	100.00
CONT_ASSIGN	992	1	1	100.00
ALWAYS	1005	5	5	100.00
CONT_ASSIGN	1036	1	1	100.00
ALWAYS	1049	5	5	100.00
CONT_ASSIGN	1080	1	1	100.00
ALWAYS	1093	5	5	100.00
CONT_ASSIGN	1124	1	1	100.00
ALWAYS	1140	10	10	100.00
ALWAYS	1190	10	10	100.00
ALWAYS	1235	3	3	100.00
CONT_ASSIGN	1264	1	1	100.00
ALWAYS	1279	6	6	100.00
CONT_ASSIGN	1311	1	1	100.00
ALWAYS	1322	4	4	100.00
CONT_ASSIGN	1413	1	1	100.00
CONT_ASSIGN	1427	1	1	100.00
CONT_ASSIGN	1433	1	1	100.00
CONT_ASSIGN	1447	1	1	100.00
CONT_ASSIGN	3452	1	1	100.00
CONT_ASSIGN	3565	1	1	100.00
CONT_ASSIGN	3733	1	1	100.00
CONT_ASSIGN	3957	0	0
ALWAYS	3976	33	33	100.00
CONT_ASSIGN	4011	1	1	100.00
ALWAYS	4015	1	1	100.00
CONT_ASSIGN	4051	1	1	100.00
CONT_ASSIGN	4053	1	1	100.00
CONT_ASSIGN	4054	1	1	100.00
CONT_ASSIGN	4056	1	1	100.00
CONT_ASSIGN	4057	1	1	100.00
CONT_ASSIGN	4059	1	1	100.00
CONT_ASSIGN	4060	1	1	100.00
CONT_ASSIGN	4063	1	1	100.00
CONT_ASSIGN	4067	1	1	100.00
CONT_ASSIGN	4069	1	1	100.00
CONT_ASSIGN	4071	1	1	100.00
CONT_ASSIGN	4073	1	1	100.00
CONT_ASSIGN	4078	1	1	100.00
CONT_ASSIGN	4083	1	1	100.00
CONT_ASSIGN	4088	1	1	100.00
CONT_ASSIGN	4093	1	1	100.00
CONT_ASSIGN	4098	1	1	100.00
CONT_ASSIGN	4103	1	1	100.00
CONT_ASSIGN	4108	1	1	100.00
CONT_ASSIGN	4113	1	1	100.00
CONT_ASSIGN	4118	1	1	100.00
CONT_ASSIGN	4123	1	1	100.00
CONT_ASSIGN	4128	1	1	100.00
CONT_ASSIGN	4133	1	1	100.00
CONT_ASSIGN	4138	1	1	100.00
CONT_ASSIGN	4143	1	1	100.00
CONT_ASSIGN	4148	1	1	100.00
CONT_ASSIGN	4153	1	1	100.00
CONT_ASSIGN	4156	1	1	100.00
CONT_ASSIGN	4159	1	1	100.00
CONT_ASSIGN	4161	1	1	100.00
CONT_ASSIGN	4163	1	1	100.00
CONT_ASSIGN	4165	1	1	100.00
CONT_ASSIGN	4166	1	1	100.00
CONT_ASSIGN	4168	1	1	100.00
CONT_ASSIGN	4170	1	1	100.00
CONT_ASSIGN	4172	1	1	100.00
CONT_ASSIGN	4173	1	1	100.00
ALWAYS	4177	33	33	100.00
ALWAYS	4214	38	38	100.00
CONT_ASSIGN	4334	1	1	100.00
ALWAYS	4336	28	28	100.00
CONT_ASSIGN	4429	1	1	100.00
CONT_ASSIGN	4430	1	1	100.00

Click here to see the source line report.

---

Cond Coverage for Module : adc_ctrl_reg_top

	Total	Covered	Percent
Conditions	333	331	99.40
Logical	333	331	99.40
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
60-4148	99.36
4153-4334	100.00

---

Branch Coverage for Module : adc_ctrl_reg_top

	Line No.	Total	Covered	Percent
Branches		65	65	100.00
TERNARY	4011	2	2	100.00
IF	70	3	3	100.00
CASE	4215	33	33	100.00
CASE	4337	27	27	100.00

4011         assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

70             if (!rst_ni) begin
               -1-  
71               err_q <= '0;
                 ==>
72             end else if (intg_err || reg_we_err) begin
                        -2-  
73               err_q <= 1'b1;
                 ==>
74             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T21,T23,T25
0	0	Covered	T1,T2,T3

4215           unique case (1'b1)
                      -1-  
4216             addr_hit[0]: begin
4217               reg_rdata_next[0] = intr_state_qs;
                   ==>
4218             end
4219       
4220             addr_hit[1]: begin
4221               reg_rdata_next[0] = intr_enable_qs;
                   ==>
4222             end
4223       
4224             addr_hit[2]: begin
4225               reg_rdata_next[0] = '0;
                   ==>
4226             end
4227       
4228             addr_hit[3]: begin
4229               reg_rdata_next[0] = '0;
                   ==>
4230             end
4231       
4232             addr_hit[4]: begin
4233               reg_rdata_next = DW'(adc_en_ctl_qs);
                   ==>
4234             end
4235             addr_hit[5]: begin
4236               reg_rdata_next = DW'(adc_pd_ctl_qs);
                   ==>
4237             end
4238             addr_hit[6]: begin
4239               reg_rdata_next = DW'(adc_lp_sample_ctl_qs);
                   ==>
4240             end
4241             addr_hit[7]: begin
4242               reg_rdata_next = DW'(adc_sample_ctl_qs);
                   ==>
4243             end
4244             addr_hit[8]: begin
4245               reg_rdata_next = DW'(adc_fsm_rst_qs);
                   ==>
4246             end
4247             addr_hit[9]: begin
4248               reg_rdata_next = DW'(adc_chn0_filter_ctl_0_qs);
                   ==>
4249             end
4250             addr_hit[10]: begin
4251               reg_rdata_next = DW'(adc_chn0_filter_ctl_1_qs);
                   ==>
4252             end
4253             addr_hit[11]: begin
4254               reg_rdata_next = DW'(adc_chn0_filter_ctl_2_qs);
                   ==>
4255             end
4256             addr_hit[12]: begin
4257               reg_rdata_next = DW'(adc_chn0_filter_ctl_3_qs);
                   ==>
4258             end
4259             addr_hit[13]: begin
4260               reg_rdata_next = DW'(adc_chn0_filter_ctl_4_qs);
                   ==>
4261             end
4262             addr_hit[14]: begin
4263               reg_rdata_next = DW'(adc_chn0_filter_ctl_5_qs);
                   ==>
4264             end
4265             addr_hit[15]: begin
4266               reg_rdata_next = DW'(adc_chn0_filter_ctl_6_qs);
                   ==>
4267             end
4268             addr_hit[16]: begin
4269               reg_rdata_next = DW'(adc_chn0_filter_ctl_7_qs);
                   ==>
4270             end
4271             addr_hit[17]: begin
4272               reg_rdata_next = DW'(adc_chn1_filter_ctl_0_qs);
                   ==>
4273             end
4274             addr_hit[18]: begin
4275               reg_rdata_next = DW'(adc_chn1_filter_ctl_1_qs);
                   ==>
4276             end
4277             addr_hit[19]: begin
4278               reg_rdata_next = DW'(adc_chn1_filter_ctl_2_qs);
                   ==>
4279             end
4280             addr_hit[20]: begin
4281               reg_rdata_next = DW'(adc_chn1_filter_ctl_3_qs);
                   ==>
4282             end
4283             addr_hit[21]: begin
4284               reg_rdata_next = DW'(adc_chn1_filter_ctl_4_qs);
                   ==>
4285             end
4286             addr_hit[22]: begin
4287               reg_rdata_next = DW'(adc_chn1_filter_ctl_5_qs);
                   ==>
4288             end
4289             addr_hit[23]: begin
4290               reg_rdata_next = DW'(adc_chn1_filter_ctl_6_qs);
                   ==>
4291             end
4292             addr_hit[24]: begin
4293               reg_rdata_next = DW'(adc_chn1_filter_ctl_7_qs);
                   ==>
4294             end
4295             addr_hit[25]: begin
4296               reg_rdata_next = DW'(adc_chn_val_0_qs);
                   ==>
4297             end
4298             addr_hit[26]: begin
4299               reg_rdata_next = DW'(adc_chn_val_1_qs);
                   ==>
4300             end
4301             addr_hit[27]: begin
4302               reg_rdata_next = DW'(adc_wakeup_ctl_qs);
                   ==>
4303             end
4304             addr_hit[28]: begin
4305               reg_rdata_next = DW'(filter_status_qs);
                   ==>
4306             end
4307             addr_hit[29]: begin
4308               reg_rdata_next[7:0] = adc_intr_ctl_match_en_qs;
                   ==>
4309               reg_rdata_next[8] = adc_intr_ctl_trans_en_qs;
4310               reg_rdata_next[9] = adc_intr_ctl_oneshot_en_qs;
4311             end
4312       
4313             addr_hit[30]: begin
4314               reg_rdata_next[7:0] = adc_intr_status_match_qs;
                   ==>
4315               reg_rdata_next[8] = adc_intr_status_trans_qs;
4316               reg_rdata_next[9] = adc_intr_status_oneshot_qs;
4317             end
4318       
4319             addr_hit[31]: begin
4320               reg_rdata_next = DW'(adc_fsm_state_qs);
                   ==>
4321             end
4322             default: begin
4323               reg_rdata_next = '1;
                   ==>

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T4
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T21
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T4
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T4
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T4
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T21
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T4
addr_hit[29]	Covered	T1,T2,T4
addr_hit[30]	Covered	T1,T2,T3
addr_hit[31]	Covered	T1,T2,T3
default	Covered	T1,T2,T4

4337           unique case (1'b1)
                      -1-  
4338             addr_hit[4]: begin
4339               reg_busy_sel = adc_en_ctl_busy;
                   ==>
4340             end
4341             addr_hit[5]: begin
4342               reg_busy_sel = adc_pd_ctl_busy;
                   ==>
4343             end
4344             addr_hit[6]: begin
4345               reg_busy_sel = adc_lp_sample_ctl_busy;
                   ==>
4346             end
4347             addr_hit[7]: begin
4348               reg_busy_sel = adc_sample_ctl_busy;
                   ==>
4349             end
4350             addr_hit[8]: begin
4351               reg_busy_sel = adc_fsm_rst_busy;
                   ==>
4352             end
4353             addr_hit[9]: begin
4354               reg_busy_sel = adc_chn0_filter_ctl_0_busy;
                   ==>
4355             end
4356             addr_hit[10]: begin
4357               reg_busy_sel = adc_chn0_filter_ctl_1_busy;
                   ==>
4358             end
4359             addr_hit[11]: begin
4360               reg_busy_sel = adc_chn0_filter_ctl_2_busy;
                   ==>
4361             end
4362             addr_hit[12]: begin
4363               reg_busy_sel = adc_chn0_filter_ctl_3_busy;
                   ==>
4364             end
4365             addr_hit[13]: begin
4366               reg_busy_sel = adc_chn0_filter_ctl_4_busy;
                   ==>
4367             end
4368             addr_hit[14]: begin
4369               reg_busy_sel = adc_chn0_filter_ctl_5_busy;
                   ==>
4370             end
4371             addr_hit[15]: begin
4372               reg_busy_sel = adc_chn0_filter_ctl_6_busy;
                   ==>
4373             end
4374             addr_hit[16]: begin
4375               reg_busy_sel = adc_chn0_filter_ctl_7_busy;
                   ==>
4376             end
4377             addr_hit[17]: begin
4378               reg_busy_sel = adc_chn1_filter_ctl_0_busy;
                   ==>
4379             end
4380             addr_hit[18]: begin
4381               reg_busy_sel = adc_chn1_filter_ctl_1_busy;
                   ==>
4382             end
4383             addr_hit[19]: begin
4384               reg_busy_sel = adc_chn1_filter_ctl_2_busy;
                   ==>
4385             end
4386             addr_hit[20]: begin
4387               reg_busy_sel = adc_chn1_filter_ctl_3_busy;
                   ==>
4388             end
4389             addr_hit[21]: begin
4390               reg_busy_sel = adc_chn1_filter_ctl_4_busy;
                   ==>
4391             end
4392             addr_hit[22]: begin
4393               reg_busy_sel = adc_chn1_filter_ctl_5_busy;
                   ==>
4394             end
4395             addr_hit[23]: begin
4396               reg_busy_sel = adc_chn1_filter_ctl_6_busy;
                   ==>
4397             end
4398             addr_hit[24]: begin
4399               reg_busy_sel = adc_chn1_filter_ctl_7_busy;
                   ==>
4400             end
4401             addr_hit[25]: begin
4402               reg_busy_sel = adc_chn_val_0_busy;
                   ==>
4403             end
4404             addr_hit[26]: begin
4405               reg_busy_sel = adc_chn_val_1_busy;
                   ==>
4406             end
4407             addr_hit[27]: begin
4408               reg_busy_sel = adc_wakeup_ctl_busy;
                   ==>
4409             end
4410             addr_hit[28]: begin
4411               reg_busy_sel = filter_status_busy;
                   ==>
4412             end
4413             addr_hit[31]: begin
4414               reg_busy_sel = adc_fsm_state_busy;
                   ==>
4415             end
4416             default: begin
4417               reg_busy_sel  = '0;
                   ==>

Branches:

-1-	Status	Tests
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T21
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T4
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T4
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T4
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T21
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T4
addr_hit[31]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : adc_ctrl_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	2147483647	2416942	0	0
reAfterRv	2147483647	2416941	0	0
rePulse	2147483647	2145762	0	0
wePulse	2147483647	271179	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2416942	0	0
T1	299630	144	0	0
T2	25763	8	0	0
T3	179799	43	0	0
T4	105974	144	0	0
T5	308670	204	0	0
T6	327577	37	0	0
T7	144286	144	0	0
T21	108025	3	0	0
T22	9439	7	0	0
T23	71080	3	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2416941	0	0
T1	299630	144	0	0
T2	25763	8	0	0
T3	179799	43	0	0
T4	105974	144	0	0
T5	308670	204	0	0
T6	327577	37	0	0
T7	144286	144	0	0
T21	108025	3	0	0
T22	9439	7	0	0
T23	71080	3	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2145762	0	0
T1	299630	81	0	0
T2	25763	1	0	0
T3	179799	0	0	0
T4	105974	81	0	0
T5	308670	168	0	0
T6	327577	0	0	0
T7	144286	81	0	0
T11	0	217	0	0
T21	108025	1	0	0
T22	9439	1	0	0
T23	71080	1	0	0
T24	0	1	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	271179	0	0
T1	299630	63	0	0
T2	25763	7	0	0
T3	179799	43	0	0
T4	105974	63	0	0
T5	308670	36	0	0
T6	327577	37	0	0
T7	144286	63	0	0
T21	108025	2	0	0
T22	9439	6	0	0
T23	71080	2	0	0

Line Coverage for Instance : tb.dut.u_reg

	Line No.	Total	Covered	Percent
TOTAL		340	340	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
ALWAYS	235	3	3	100.00
CONT_ASSIGN	264	1	1	100.00
ALWAYS	276	4	4	100.00
CONT_ASSIGN	306	1	1	100.00
ALWAYS	316	2	2	100.00
CONT_ASSIGN	344	1	1	100.00
ALWAYS	354	2	2	100.00
CONT_ASSIGN	382	1	1	100.00
ALWAYS	392	2	2	100.00
CONT_ASSIGN	420	1	1	100.00
ALWAYS	433	5	5	100.00
CONT_ASSIGN	464	1	1	100.00
ALWAYS	477	5	5	100.00
CONT_ASSIGN	508	1	1	100.00
ALWAYS	521	5	5	100.00
CONT_ASSIGN	552	1	1	100.00
ALWAYS	565	5	5	100.00
CONT_ASSIGN	596	1	1	100.00
ALWAYS	609	5	5	100.00
CONT_ASSIGN	640	1	1	100.00
ALWAYS	653	5	5	100.00
CONT_ASSIGN	684	1	1	100.00
ALWAYS	697	5	5	100.00
CONT_ASSIGN	728	1	1	100.00
ALWAYS	741	5	5	100.00
CONT_ASSIGN	772	1	1	100.00
ALWAYS	785	5	5	100.00
CONT_ASSIGN	816	1	1	100.00
ALWAYS	829	5	5	100.00
CONT_ASSIGN	860	1	1	100.00
ALWAYS	873	5	5	100.00
CONT_ASSIGN	904	1	1	100.00
ALWAYS	917	5	5	100.00
CONT_ASSIGN	948	1	1	100.00
ALWAYS	961	5	5	100.00
CONT_ASSIGN	992	1	1	100.00
ALWAYS	1005	5	5	100.00
CONT_ASSIGN	1036	1	1	100.00
ALWAYS	1049	5	5	100.00
CONT_ASSIGN	1080	1	1	100.00
ALWAYS	1093	5	5	100.00
CONT_ASSIGN	1124	1	1	100.00
ALWAYS	1140	10	10	100.00
ALWAYS	1190	10	10	100.00
ALWAYS	1235	3	3	100.00
CONT_ASSIGN	1264	1	1	100.00
ALWAYS	1279	6	6	100.00
CONT_ASSIGN	1311	1	1	100.00
ALWAYS	1322	4	4	100.00
CONT_ASSIGN	1413	1	1	100.00
CONT_ASSIGN	1427	1	1	100.00
CONT_ASSIGN	1433	1	1	100.00
CONT_ASSIGN	1447	1	1	100.00
CONT_ASSIGN	3452	1	1	100.00
CONT_ASSIGN	3565	1	1	100.00
CONT_ASSIGN	3733	1	1	100.00
CONT_ASSIGN	3957	0	0
ALWAYS	3976	33	33	100.00
CONT_ASSIGN	4011	1	1	100.00
ALWAYS	4015	1	1	100.00
CONT_ASSIGN	4051	1	1	100.00
CONT_ASSIGN	4053	1	1	100.00
CONT_ASSIGN	4054	1	1	100.00
CONT_ASSIGN	4056	1	1	100.00
CONT_ASSIGN	4057	1	1	100.00
CONT_ASSIGN	4059	1	1	100.00
CONT_ASSIGN	4060	1	1	100.00
CONT_ASSIGN	4063	1	1	100.00
CONT_ASSIGN	4067	1	1	100.00
CONT_ASSIGN	4069	1	1	100.00
CONT_ASSIGN	4071	1	1	100.00
CONT_ASSIGN	4073	1	1	100.00
CONT_ASSIGN	4078	1	1	100.00
CONT_ASSIGN	4083	1	1	100.00
CONT_ASSIGN	4088	1	1	100.00
CONT_ASSIGN	4093	1	1	100.00
CONT_ASSIGN	4098	1	1	100.00
CONT_ASSIGN	4103	1	1	100.00
CONT_ASSIGN	4108	1	1	100.00
CONT_ASSIGN	4113	1	1	100.00
CONT_ASSIGN	4118	1	1	100.00
CONT_ASSIGN	4123	1	1	100.00
CONT_ASSIGN	4128	1	1	100.00
CONT_ASSIGN	4133	1	1	100.00
CONT_ASSIGN	4138	1	1	100.00
CONT_ASSIGN	4143	1	1	100.00
CONT_ASSIGN	4148	1	1	100.00
CONT_ASSIGN	4153	1	1	100.00
CONT_ASSIGN	4156	1	1	100.00
CONT_ASSIGN	4159	1	1	100.00
CONT_ASSIGN	4161	1	1	100.00
CONT_ASSIGN	4163	1	1	100.00
CONT_ASSIGN	4165	1	1	100.00
CONT_ASSIGN	4166	1	1	100.00
CONT_ASSIGN	4168	1	1	100.00
CONT_ASSIGN	4170	1	1	100.00
CONT_ASSIGN	4172	1	1	100.00
CONT_ASSIGN	4173	1	1	100.00
ALWAYS	4177	33	33	100.00
ALWAYS	4214	38	38	100.00
CONT_ASSIGN	4334	1	1	100.00
ALWAYS	4336	28	28	100.00
CONT_ASSIGN	4429	1	1	100.00
CONT_ASSIGN	4430	1	1	100.00

Click here to see the source line report.

---

Cond Coverage for Instance : tb.dut.u_reg

	Total	Covered	Percent
Conditions	331	331	100.00
Logical	331	331	100.00
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
60-4148	100.00
4153-4334	100.00

---

Branch Coverage for Instance : tb.dut.u_reg

	Line No.	Total	Covered	Percent
Branches		65	65	100.00
TERNARY	4011	2	2	100.00
IF	70	3	3	100.00
CASE	4215	33	33	100.00
CASE	4337	27	27	100.00

4011         assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

70             if (!rst_ni) begin
               -1-  
71               err_q <= '0;
                 ==>
72             end else if (intg_err || reg_we_err) begin
                        -2-  
73               err_q <= 1'b1;
                 ==>
74             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T21,T23,T25
0	0	Covered	T1,T2,T3

4215           unique case (1'b1)
                      -1-  
4216             addr_hit[0]: begin
4217               reg_rdata_next[0] = intr_state_qs;
                   ==>
4218             end
4219       
4220             addr_hit[1]: begin
4221               reg_rdata_next[0] = intr_enable_qs;
                   ==>
4222             end
4223       
4224             addr_hit[2]: begin
4225               reg_rdata_next[0] = '0;
                   ==>
4226             end
4227       
4228             addr_hit[3]: begin
4229               reg_rdata_next[0] = '0;
                   ==>
4230             end
4231       
4232             addr_hit[4]: begin
4233               reg_rdata_next = DW'(adc_en_ctl_qs);
                   ==>
4234             end
4235             addr_hit[5]: begin
4236               reg_rdata_next = DW'(adc_pd_ctl_qs);
                   ==>
4237             end
4238             addr_hit[6]: begin
4239               reg_rdata_next = DW'(adc_lp_sample_ctl_qs);
                   ==>
4240             end
4241             addr_hit[7]: begin
4242               reg_rdata_next = DW'(adc_sample_ctl_qs);
                   ==>
4243             end
4244             addr_hit[8]: begin
4245               reg_rdata_next = DW'(adc_fsm_rst_qs);
                   ==>
4246             end
4247             addr_hit[9]: begin
4248               reg_rdata_next = DW'(adc_chn0_filter_ctl_0_qs);
                   ==>
4249             end
4250             addr_hit[10]: begin
4251               reg_rdata_next = DW'(adc_chn0_filter_ctl_1_qs);
                   ==>
4252             end
4253             addr_hit[11]: begin
4254               reg_rdata_next = DW'(adc_chn0_filter_ctl_2_qs);
                   ==>
4255             end
4256             addr_hit[12]: begin
4257               reg_rdata_next = DW'(adc_chn0_filter_ctl_3_qs);
                   ==>
4258             end
4259             addr_hit[13]: begin
4260               reg_rdata_next = DW'(adc_chn0_filter_ctl_4_qs);
                   ==>
4261             end
4262             addr_hit[14]: begin
4263               reg_rdata_next = DW'(adc_chn0_filter_ctl_5_qs);
                   ==>
4264             end
4265             addr_hit[15]: begin
4266               reg_rdata_next = DW'(adc_chn0_filter_ctl_6_qs);
                   ==>
4267             end
4268             addr_hit[16]: begin
4269               reg_rdata_next = DW'(adc_chn0_filter_ctl_7_qs);
                   ==>
4270             end
4271             addr_hit[17]: begin
4272               reg_rdata_next = DW'(adc_chn1_filter_ctl_0_qs);
                   ==>
4273             end
4274             addr_hit[18]: begin
4275               reg_rdata_next = DW'(adc_chn1_filter_ctl_1_qs);
                   ==>
4276             end
4277             addr_hit[19]: begin
4278               reg_rdata_next = DW'(adc_chn1_filter_ctl_2_qs);
                   ==>
4279             end
4280             addr_hit[20]: begin
4281               reg_rdata_next = DW'(adc_chn1_filter_ctl_3_qs);
                   ==>
4282             end
4283             addr_hit[21]: begin
4284               reg_rdata_next = DW'(adc_chn1_filter_ctl_4_qs);
                   ==>
4285             end
4286             addr_hit[22]: begin
4287               reg_rdata_next = DW'(adc_chn1_filter_ctl_5_qs);
                   ==>
4288             end
4289             addr_hit[23]: begin
4290               reg_rdata_next = DW'(adc_chn1_filter_ctl_6_qs);
                   ==>
4291             end
4292             addr_hit[24]: begin
4293               reg_rdata_next = DW'(adc_chn1_filter_ctl_7_qs);
                   ==>
4294             end
4295             addr_hit[25]: begin
4296               reg_rdata_next = DW'(adc_chn_val_0_qs);
                   ==>
4297             end
4298             addr_hit[26]: begin
4299               reg_rdata_next = DW'(adc_chn_val_1_qs);
                   ==>
4300             end
4301             addr_hit[27]: begin
4302               reg_rdata_next = DW'(adc_wakeup_ctl_qs);
                   ==>
4303             end
4304             addr_hit[28]: begin
4305               reg_rdata_next = DW'(filter_status_qs);
                   ==>
4306             end
4307             addr_hit[29]: begin
4308               reg_rdata_next[7:0] = adc_intr_ctl_match_en_qs;
                   ==>
4309               reg_rdata_next[8] = adc_intr_ctl_trans_en_qs;
4310               reg_rdata_next[9] = adc_intr_ctl_oneshot_en_qs;
4311             end
4312       
4313             addr_hit[30]: begin
4314               reg_rdata_next[7:0] = adc_intr_status_match_qs;
                   ==>
4315               reg_rdata_next[8] = adc_intr_status_trans_qs;
4316               reg_rdata_next[9] = adc_intr_status_oneshot_qs;
4317             end
4318       
4319             addr_hit[31]: begin
4320               reg_rdata_next = DW'(adc_fsm_state_qs);
                   ==>
4321             end
4322             default: begin
4323               reg_rdata_next = '1;
                   ==>

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T4
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T21
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T4
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T4
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T4
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T21
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T4
addr_hit[29]	Covered	T1,T2,T4
addr_hit[30]	Covered	T1,T2,T3
addr_hit[31]	Covered	T1,T2,T3
default	Covered	T1,T2,T4

4337           unique case (1'b1)
                      -1-  
4338             addr_hit[4]: begin
4339               reg_busy_sel = adc_en_ctl_busy;
                   ==>
4340             end
4341             addr_hit[5]: begin
4342               reg_busy_sel = adc_pd_ctl_busy;
                   ==>
4343             end
4344             addr_hit[6]: begin
4345               reg_busy_sel = adc_lp_sample_ctl_busy;
                   ==>
4346             end
4347             addr_hit[7]: begin
4348               reg_busy_sel = adc_sample_ctl_busy;
                   ==>
4349             end
4350             addr_hit[8]: begin
4351               reg_busy_sel = adc_fsm_rst_busy;
                   ==>
4352             end
4353             addr_hit[9]: begin
4354               reg_busy_sel = adc_chn0_filter_ctl_0_busy;
                   ==>
4355             end
4356             addr_hit[10]: begin
4357               reg_busy_sel = adc_chn0_filter_ctl_1_busy;
                   ==>
4358             end
4359             addr_hit[11]: begin
4360               reg_busy_sel = adc_chn0_filter_ctl_2_busy;
                   ==>
4361             end
4362             addr_hit[12]: begin
4363               reg_busy_sel = adc_chn0_filter_ctl_3_busy;
                   ==>
4364             end
4365             addr_hit[13]: begin
4366               reg_busy_sel = adc_chn0_filter_ctl_4_busy;
                   ==>
4367             end
4368             addr_hit[14]: begin
4369               reg_busy_sel = adc_chn0_filter_ctl_5_busy;
                   ==>
4370             end
4371             addr_hit[15]: begin
4372               reg_busy_sel = adc_chn0_filter_ctl_6_busy;
                   ==>
4373             end
4374             addr_hit[16]: begin
4375               reg_busy_sel = adc_chn0_filter_ctl_7_busy;
                   ==>
4376             end
4377             addr_hit[17]: begin
4378               reg_busy_sel = adc_chn1_filter_ctl_0_busy;
                   ==>
4379             end
4380             addr_hit[18]: begin
4381               reg_busy_sel = adc_chn1_filter_ctl_1_busy;
                   ==>
4382             end
4383             addr_hit[19]: begin
4384               reg_busy_sel = adc_chn1_filter_ctl_2_busy;
                   ==>
4385             end
4386             addr_hit[20]: begin
4387               reg_busy_sel = adc_chn1_filter_ctl_3_busy;
                   ==>
4388             end
4389             addr_hit[21]: begin
4390               reg_busy_sel = adc_chn1_filter_ctl_4_busy;
                   ==>
4391             end
4392             addr_hit[22]: begin
4393               reg_busy_sel = adc_chn1_filter_ctl_5_busy;
                   ==>
4394             end
4395             addr_hit[23]: begin
4396               reg_busy_sel = adc_chn1_filter_ctl_6_busy;
                   ==>
4397             end
4398             addr_hit[24]: begin
4399               reg_busy_sel = adc_chn1_filter_ctl_7_busy;
                   ==>
4400             end
4401             addr_hit[25]: begin
4402               reg_busy_sel = adc_chn_val_0_busy;
                   ==>
4403             end
4404             addr_hit[26]: begin
4405               reg_busy_sel = adc_chn_val_1_busy;
                   ==>
4406             end
4407             addr_hit[27]: begin
4408               reg_busy_sel = adc_wakeup_ctl_busy;
                   ==>
4409             end
4410             addr_hit[28]: begin
4411               reg_busy_sel = filter_status_busy;
                   ==>
4412             end
4413             addr_hit[31]: begin
4414               reg_busy_sel = adc_fsm_state_busy;
                   ==>
4415             end
4416             default: begin
4417               reg_busy_sel  = '0;
                   ==>

Branches:

-1-	Status	Tests
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T21
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T4
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T4
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T4
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T21
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T4
addr_hit[31]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	2147483647	2416942	0	0
reAfterRv	2147483647	2416941	0	0
rePulse	2147483647	2145762	0	0
wePulse	2147483647	271179	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2416942	0	0
T1	299630	144	0	0
T2	25763	8	0	0
T3	179799	43	0	0
T4	105974	144	0	0
T5	308670	204	0	0
T6	327577	37	0	0
T7	144286	144	0	0
T21	108025	3	0	0
T22	9439	7	0	0
T23	71080	3	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2416941	0	0
T1	299630	144	0	0
T2	25763	8	0	0
T3	179799	43	0	0
T4	105974	144	0	0
T5	308670	204	0	0
T6	327577	37	0	0
T7	144286	144	0	0
T21	108025	3	0	0
T22	9439	7	0	0
T23	71080	3	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2145762	0	0
T1	299630	81	0	0
T2	25763	1	0	0
T3	179799	0	0	0
T4	105974	81	0	0
T5	308670	168	0	0
T6	327577	0	0	0
T7	144286	81	0	0
T11	0	217	0	0
T21	108025	1	0	0
T22	9439	1	0	0
T23	71080	1	0	0
T24	0	1	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	271179	0	0
T1	299630	63	0	0
T2	25763	7	0	0
T3	179799	43	0	0
T4	105974	63	0	0
T5	308670	36	0	0
T6	327577	37	0	0
T7	144286	63	0	0
T21	108025	2	0	0
T22	9439	6	0	0
T23	71080	2	0	0