| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.78 | 99.07 | 96.67 | 100.00 | 100.00 | 98.82 | 98.33 | 91.54 |
| T365 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_stress_all.1350643106 | Sep 24 08:06:27 AM UTC 24 | Sep 24 08:25:39 AM UTC 24 | 1349030199747 ps | ||
| T797 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3107111866 | Sep 24 08:05:53 AM UTC 24 | Sep 24 08:26:52 AM UTC 24 | 416065949899 ps | ||
| T798 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_wakeup_fixed.3552036382 | Sep 24 08:07:33 AM UTC 24 | Sep 24 08:33:08 AM UTC 24 | 607311547999 ps | ||
| T341 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt.3400750149 | Sep 24 08:07:01 AM UTC 24 | Sep 24 08:33:09 AM UTC 24 | 493340796359 ps | ||
| T799 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all.592794191 | Sep 24 07:38:13 AM UTC 24 | Sep 24 08:35:47 AM UTC 24 | 844489177211 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.516327234 | Sep 24 08:08:23 AM UTC 24 | Sep 24 08:08:31 AM UTC 24 | 573968752 ps | ||
| T800 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.4036073032 | Sep 24 08:08:31 AM UTC 24 | Sep 24 08:08:34 AM UTC 24 | 542758063 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2389644823 | Sep 24 08:08:35 AM UTC 24 | Sep 24 08:08:37 AM UTC 24 | 623060239 ps | ||
| T104 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2490190698 | Sep 24 08:08:34 AM UTC 24 | Sep 24 08:08:38 AM UTC 24 | 864911827 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1973646057 | Sep 24 08:08:40 AM UTC 24 | Sep 24 08:08:44 AM UTC 24 | 391685608 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.4198512351 | Sep 24 08:08:35 AM UTC 24 | Sep 24 08:08:47 AM UTC 24 | 6742174251 ps | ||
| T105 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.591357807 | Sep 24 08:08:38 AM UTC 24 | Sep 24 08:08:48 AM UTC 24 | 1054892289 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2586669252 | Sep 24 08:08:24 AM UTC 24 | Sep 24 08:08:49 AM UTC 24 | 8428268257 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2810751614 | Sep 24 08:08:45 AM UTC 24 | Sep 24 08:08:49 AM UTC 24 | 799742054 ps | ||
| T801 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.3877182227 | Sep 24 08:08:49 AM UTC 24 | Sep 24 08:08:51 AM UTC 24 | 584481673 ps | ||
| T125 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.672053626 | Sep 24 08:08:50 AM UTC 24 | Sep 24 08:08:53 AM UTC 24 | 891846267 ps | ||
| T106 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1521520438 | Sep 24 08:08:50 AM UTC 24 | Sep 24 08:08:55 AM UTC 24 | 491423111 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.741434059 | Sep 24 08:08:39 AM UTC 24 | Sep 24 08:08:55 AM UTC 24 | 4253602941 ps | ||
| T107 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3650933454 | Sep 24 08:08:53 AM UTC 24 | Sep 24 08:08:57 AM UTC 24 | 872496735 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2159872530 | Sep 24 08:08:55 AM UTC 24 | Sep 24 08:09:00 AM UTC 24 | 427018689 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2080172293 | Sep 24 08:08:48 AM UTC 24 | Sep 24 08:09:00 AM UTC 24 | 4222244576 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1899968523 | Sep 24 08:08:56 AM UTC 24 | Sep 24 08:09:00 AM UTC 24 | 469709287 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1811316524 | Sep 24 08:08:54 AM UTC 24 | Sep 24 08:09:01 AM UTC 24 | 5120934371 ps | ||
| T108 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.519869028 | Sep 24 08:09:01 AM UTC 24 | Sep 24 08:09:04 AM UTC 24 | 545288692 ps | ||
| T802 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.1977809137 | Sep 24 08:09:01 AM UTC 24 | Sep 24 08:09:05 AM UTC 24 | 480175445 ps | ||
| T803 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.273973649 | Sep 24 08:09:01 AM UTC 24 | Sep 24 08:09:05 AM UTC 24 | 998617991 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3278924715 | Sep 24 08:08:59 AM UTC 24 | Sep 24 08:09:07 AM UTC 24 | 4659348641 ps | ||
| T109 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.678841275 | Sep 24 08:09:01 AM UTC 24 | Sep 24 08:09:08 AM UTC 24 | 1315973949 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.82143998 | Sep 24 08:09:05 AM UTC 24 | Sep 24 08:09:08 AM UTC 24 | 323569783 ps | ||
| T110 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.4179699421 | Sep 24 08:09:01 AM UTC 24 | Sep 24 08:09:10 AM UTC 24 | 903824520 ps | ||
| T804 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.1305168053 | Sep 24 08:09:08 AM UTC 24 | Sep 24 08:09:11 AM UTC 24 | 469400551 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.653279469 | Sep 24 08:09:06 AM UTC 24 | Sep 24 08:09:11 AM UTC 24 | 1000884353 ps | ||
| T111 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2122071343 | Sep 24 08:09:09 AM UTC 24 | Sep 24 08:09:12 AM UTC 24 | 913887504 ps | ||
| T112 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.754874200 | Sep 24 08:08:52 AM UTC 24 | Sep 24 08:09:12 AM UTC 24 | 7211353393 ps | ||
| T113 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.733369639 | Sep 24 08:09:09 AM UTC 24 | Sep 24 08:09:14 AM UTC 24 | 530723600 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3608175207 | Sep 24 08:09:02 AM UTC 24 | Sep 24 08:09:14 AM UTC 24 | 4542695233 ps | ||
| T85 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.4107624736 | Sep 24 08:09:12 AM UTC 24 | Sep 24 08:09:16 AM UTC 24 | 529618668 ps | ||
| T114 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3789100495 | Sep 24 08:09:11 AM UTC 24 | Sep 24 08:09:16 AM UTC 24 | 810345553 ps | ||
| T805 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1406250644 | Sep 24 08:09:14 AM UTC 24 | Sep 24 08:09:18 AM UTC 24 | 374063074 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1162043982 | Sep 24 08:09:06 AM UTC 24 | Sep 24 08:09:18 AM UTC 24 | 8225279603 ps | ||
| T115 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1320297061 | Sep 24 08:09:11 AM UTC 24 | Sep 24 08:09:19 AM UTC 24 | 2205209244 ps | ||
| T806 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_intr_test.3189680868 | Sep 24 08:09:16 AM UTC 24 | Sep 24 08:09:19 AM UTC 24 | 280967687 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1395848953 | Sep 24 08:09:17 AM UTC 24 | Sep 24 08:09:20 AM UTC 24 | 1185187477 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_rw.543832296 | Sep 24 08:09:17 AM UTC 24 | Sep 24 08:09:21 AM UTC 24 | 545930572 ps | ||
| T119 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.578870863 | Sep 24 08:09:20 AM UTC 24 | Sep 24 08:09:23 AM UTC 24 | 2802329359 ps | ||
| T807 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.429845291 | Sep 24 08:09:19 AM UTC 24 | Sep 24 08:09:24 AM UTC 24 | 417265551 ps | ||
| T808 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.246569264 | Sep 24 08:09:20 AM UTC 24 | Sep 24 08:09:24 AM UTC 24 | 407910423 ps | ||
| T809 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1426525864 | Sep 24 08:09:21 AM UTC 24 | Sep 24 08:09:26 AM UTC 24 | 349632335 ps | ||
| T120 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1216877549 | Sep 24 08:09:24 AM UTC 24 | Sep 24 08:09:27 AM UTC 24 | 619559830 ps | ||
| T810 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_intr_test.1741052106 | Sep 24 08:09:24 AM UTC 24 | Sep 24 08:09:28 AM UTC 24 | 308033369 ps | ||
| T811 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2479847916 | Sep 24 08:09:25 AM UTC 24 | Sep 24 08:09:28 AM UTC 24 | 376846537 ps | ||
| T812 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_intr_test.3055202980 | Sep 24 08:09:27 AM UTC 24 | Sep 24 08:09:30 AM UTC 24 | 564336072 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1582699801 | Sep 24 08:09:29 AM UTC 24 | Sep 24 08:09:31 AM UTC 24 | 463143089 ps | ||
| T368 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2289107751 | Sep 24 08:09:15 AM UTC 24 | Sep 24 08:09:32 AM UTC 24 | 3851487924 ps | ||
| T78 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2464426615 | Sep 24 08:09:26 AM UTC 24 | Sep 24 08:09:33 AM UTC 24 | 501152887 ps | ||
| T813 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1629638978 | Sep 24 08:09:31 AM UTC 24 | Sep 24 08:09:34 AM UTC 24 | 544898018 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3963574670 | Sep 24 08:09:12 AM UTC 24 | Sep 24 08:09:35 AM UTC 24 | 4856973985 ps | ||
| T814 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3460147236 | Sep 24 08:09:31 AM UTC 24 | Sep 24 08:09:35 AM UTC 24 | 710373533 ps | ||
| T815 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_intr_test.1719389129 | Sep 24 08:09:33 AM UTC 24 | Sep 24 08:09:35 AM UTC 24 | 595103487 ps | ||
| T123 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_rw.947118502 | Sep 24 08:09:33 AM UTC 24 | Sep 24 08:09:35 AM UTC 24 | 425404788 ps | ||
| T816 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2926960799 | Sep 24 08:09:30 AM UTC 24 | Sep 24 08:09:37 AM UTC 24 | 2626730044 ps | ||
| T817 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3023861221 | Sep 24 08:09:35 AM UTC 24 | Sep 24 08:09:38 AM UTC 24 | 518665029 ps | ||
| T366 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2191441273 | Sep 24 08:09:26 AM UTC 24 | Sep 24 08:09:38 AM UTC 24 | 8866985166 ps | ||
| T818 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_intr_test.3961994181 | Sep 24 08:09:36 AM UTC 24 | Sep 24 08:09:39 AM UTC 24 | 430455656 ps | ||
| T819 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2287060698 | Sep 24 08:09:25 AM UTC 24 | Sep 24 08:09:39 AM UTC 24 | 2975625675 ps | ||
| T820 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1520458435 | Sep 24 08:09:36 AM UTC 24 | Sep 24 08:09:40 AM UTC 24 | 503257062 ps | ||
| T821 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1738971812 | Sep 24 08:09:19 AM UTC 24 | Sep 24 08:09:40 AM UTC 24 | 20965485152 ps | ||
| T822 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.384925398 | Sep 24 08:09:37 AM UTC 24 | Sep 24 08:09:40 AM UTC 24 | 2376472126 ps | ||
| T823 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2844614420 | Sep 24 08:09:36 AM UTC 24 | Sep 24 08:09:41 AM UTC 24 | 353086148 ps | ||
| T824 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.4148490328 | Sep 24 08:09:38 AM UTC 24 | Sep 24 08:09:41 AM UTC 24 | 423319152 ps | ||
| T825 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_intr_test.2505609879 | Sep 24 08:09:39 AM UTC 24 | Sep 24 08:09:42 AM UTC 24 | 374234255 ps | ||
| T79 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.741664484 | Sep 24 08:09:32 AM UTC 24 | Sep 24 08:09:43 AM UTC 24 | 7673595510 ps | ||
| T826 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3595928517 | Sep 24 08:09:34 AM UTC 24 | Sep 24 08:09:43 AM UTC 24 | 2298710734 ps | ||
| T827 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2881021645 | Sep 24 08:09:39 AM UTC 24 | Sep 24 08:09:44 AM UTC 24 | 445635908 ps | ||
| T828 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1767640697 | Sep 24 08:09:41 AM UTC 24 | Sep 24 08:09:44 AM UTC 24 | 435514778 ps | ||
| T829 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1573810320 | Sep 24 08:09:41 AM UTC 24 | Sep 24 08:09:44 AM UTC 24 | 330731519 ps | ||
| T830 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.776189994 | Sep 24 08:09:43 AM UTC 24 | Sep 24 08:09:45 AM UTC 24 | 351171239 ps | ||
| T831 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.311433659 | Sep 24 08:09:42 AM UTC 24 | Sep 24 08:09:46 AM UTC 24 | 558265708 ps | ||
| T832 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2163118913 | Sep 24 08:09:44 AM UTC 24 | Sep 24 08:09:47 AM UTC 24 | 2450229139 ps | ||
| T833 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2778432901 | Sep 24 08:09:45 AM UTC 24 | Sep 24 08:09:48 AM UTC 24 | 380935185 ps | ||
| T369 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2102457222 | Sep 24 08:09:22 AM UTC 24 | Sep 24 08:09:48 AM UTC 24 | 9019436450 ps | ||
| T834 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2258189363 | Sep 24 08:09:44 AM UTC 24 | Sep 24 08:09:49 AM UTC 24 | 563688636 ps | ||
| T835 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.3651604557 | Sep 24 08:09:46 AM UTC 24 | Sep 24 08:09:49 AM UTC 24 | 366488159 ps | ||
| T367 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1239969066 | Sep 24 08:09:36 AM UTC 24 | Sep 24 08:09:50 AM UTC 24 | 8432466145 ps | ||
| T836 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.371781165 | Sep 24 08:09:45 AM UTC 24 | Sep 24 08:09:50 AM UTC 24 | 1148270245 ps | ||
| T837 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1289847563 | Sep 24 08:09:46 AM UTC 24 | Sep 24 08:09:50 AM UTC 24 | 445720707 ps | ||
| T838 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1141393299 | Sep 24 08:09:48 AM UTC 24 | Sep 24 08:09:52 AM UTC 24 | 869339864 ps | ||
| T839 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.539599119 | Sep 24 08:09:48 AM UTC 24 | Sep 24 08:09:52 AM UTC 24 | 482270320 ps | ||
| T840 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2065621854 | Sep 24 08:09:43 AM UTC 24 | Sep 24 08:09:53 AM UTC 24 | 8437729578 ps | ||
| T841 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.3986510587 | Sep 24 08:09:50 AM UTC 24 | Sep 24 08:09:53 AM UTC 24 | 354364005 ps | ||
| T842 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1875150720 | Sep 24 08:09:51 AM UTC 24 | Sep 24 08:09:54 AM UTC 24 | 364344892 ps | ||
| T843 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.119948989 | Sep 24 08:09:48 AM UTC 24 | Sep 24 08:09:55 AM UTC 24 | 2112852111 ps | ||
| T844 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3736726744 | Sep 24 08:09:52 AM UTC 24 | Sep 24 08:09:55 AM UTC 24 | 590059418 ps | ||
| T845 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.2686048878 | Sep 24 08:09:54 AM UTC 24 | Sep 24 08:09:57 AM UTC 24 | 316082711 ps | ||
| T846 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1980398921 | Sep 24 08:09:53 AM UTC 24 | Sep 24 08:09:57 AM UTC 24 | 571961691 ps | ||
| T847 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1578462283 | Sep 24 08:09:45 AM UTC 24 | Sep 24 08:09:58 AM UTC 24 | 4327315962 ps | ||
| T848 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1789682461 | Sep 24 08:09:54 AM UTC 24 | Sep 24 08:09:58 AM UTC 24 | 463877018 ps | ||
| T849 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2852407652 | Sep 24 08:09:54 AM UTC 24 | Sep 24 08:09:58 AM UTC 24 | 2024598455 ps | ||
| T850 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2302558758 | Sep 24 08:09:53 AM UTC 24 | Sep 24 08:09:59 AM UTC 24 | 4118070173 ps | ||
| T851 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2193485340 | Sep 24 08:09:55 AM UTC 24 | Sep 24 08:10:00 AM UTC 24 | 571122740 ps | ||
| T852 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3606026347 | Sep 24 08:09:51 AM UTC 24 | Sep 24 08:10:00 AM UTC 24 | 2168827458 ps | ||
| T853 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.2741506940 | Sep 24 08:09:57 AM UTC 24 | Sep 24 08:10:01 AM UTC 24 | 341377842 ps | ||
| T854 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2359879876 | Sep 24 08:09:50 AM UTC 24 | Sep 24 08:10:01 AM UTC 24 | 8009980278 ps | ||
| T855 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2800225272 | Sep 24 08:09:58 AM UTC 24 | Sep 24 08:10:02 AM UTC 24 | 330409077 ps | ||
| T856 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1576407238 | Sep 24 08:09:56 AM UTC 24 | Sep 24 08:10:02 AM UTC 24 | 425956721 ps | ||
| T857 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.178326696 | Sep 24 08:09:59 AM UTC 24 | Sep 24 08:10:02 AM UTC 24 | 399483476 ps | ||
| T858 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.2501384302 | Sep 24 08:10:01 AM UTC 24 | Sep 24 08:10:03 AM UTC 24 | 338934033 ps | ||
| T859 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.261259883 | Sep 24 08:10:02 AM UTC 24 | Sep 24 08:10:05 AM UTC 24 | 347698196 ps | ||
| T860 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.485819288 | Sep 24 08:09:59 AM UTC 24 | Sep 24 08:10:05 AM UTC 24 | 476329873 ps | ||
| T861 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3296814705 | Sep 24 08:09:39 AM UTC 24 | Sep 24 08:10:05 AM UTC 24 | 4500980515 ps | ||
| T862 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.4153816607 | Sep 24 08:10:02 AM UTC 24 | Sep 24 08:10:05 AM UTC 24 | 460462324 ps | ||
| T863 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.4287328448 | Sep 24 08:10:03 AM UTC 24 | Sep 24 08:10:06 AM UTC 24 | 408043431 ps | ||
| T864 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3679664291 | Sep 24 08:10:03 AM UTC 24 | Sep 24 08:10:06 AM UTC 24 | 871991322 ps | ||
| T865 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/43.adc_ctrl_intr_test.387203246 | Sep 24 08:10:23 AM UTC 24 | Sep 24 08:10:27 AM UTC 24 | 316289019 ps | ||
| T866 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1121690896 | Sep 24 08:09:59 AM UTC 24 | Sep 24 08:10:08 AM UTC 24 | 2155967116 ps | ||
| T867 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1375465390 | Sep 24 08:10:04 AM UTC 24 | Sep 24 08:10:08 AM UTC 24 | 370451441 ps | ||
| T868 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1159908112 | Sep 24 08:10:01 AM UTC 24 | Sep 24 08:10:09 AM UTC 24 | 4516084113 ps | ||
| T869 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2584901531 | Sep 24 08:09:41 AM UTC 24 | Sep 24 08:10:09 AM UTC 24 | 4831851078 ps | ||
| T870 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1678885637 | Sep 24 08:10:06 AM UTC 24 | Sep 24 08:10:10 AM UTC 24 | 558778842 ps | ||
| T871 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.455647981 | Sep 24 08:10:07 AM UTC 24 | Sep 24 08:10:10 AM UTC 24 | 326631230 ps | ||
| T872 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.512812641 | Sep 24 08:10:07 AM UTC 24 | Sep 24 08:10:10 AM UTC 24 | 364921661 ps | ||
| T873 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.267392183 | Sep 24 08:10:05 AM UTC 24 | Sep 24 08:10:11 AM UTC 24 | 2444492947 ps | ||
| T874 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.885329105 | Sep 24 08:10:06 AM UTC 24 | Sep 24 08:10:12 AM UTC 24 | 477136743 ps | ||
| T875 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.565503292 | Sep 24 08:10:08 AM UTC 24 | Sep 24 08:10:12 AM UTC 24 | 718059436 ps | ||
| T876 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.293628069 | Sep 24 08:10:11 AM UTC 24 | Sep 24 08:10:13 AM UTC 24 | 320798915 ps | ||
| T877 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.128764448 | Sep 24 08:10:09 AM UTC 24 | Sep 24 08:10:14 AM UTC 24 | 593798697 ps | ||
| T878 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3063740696 | Sep 24 08:10:12 AM UTC 24 | Sep 24 08:10:15 AM UTC 24 | 500909770 ps | ||
| T879 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.2027953952 | Sep 24 08:10:13 AM UTC 24 | Sep 24 08:10:15 AM UTC 24 | 400482569 ps | ||
| T880 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.4078745714 | Sep 24 08:10:07 AM UTC 24 | Sep 24 08:10:15 AM UTC 24 | 4887425009 ps | ||
| T881 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2838525584 | Sep 24 08:10:11 AM UTC 24 | Sep 24 08:10:16 AM UTC 24 | 543165127 ps | ||
| T882 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3110661059 | Sep 24 08:10:02 AM UTC 24 | Sep 24 08:10:17 AM UTC 24 | 5617524962 ps | ||
| T883 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1249368621 | Sep 24 08:10:14 AM UTC 24 | Sep 24 08:10:17 AM UTC 24 | 427218698 ps | ||
| T80 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.262422485 | Sep 24 08:10:03 AM UTC 24 | Sep 24 08:10:17 AM UTC 24 | 8698126373 ps | ||
| T884 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3117506481 | Sep 24 08:10:12 AM UTC 24 | Sep 24 08:10:18 AM UTC 24 | 419037580 ps | ||
| T885 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.716360925 | Sep 24 08:10:16 AM UTC 24 | Sep 24 08:10:18 AM UTC 24 | 516991706 ps | ||
| T886 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1322885822 | Sep 24 08:10:11 AM UTC 24 | Sep 24 08:10:19 AM UTC 24 | 4611278803 ps | ||
| T887 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.1897756775 | Sep 24 08:10:16 AM UTC 24 | Sep 24 08:10:19 AM UTC 24 | 552394685 ps | ||
| T888 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.377294710 | Sep 24 08:10:16 AM UTC 24 | Sep 24 08:10:19 AM UTC 24 | 461237900 ps | ||
| T889 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.4181088913 | Sep 24 08:10:16 AM UTC 24 | Sep 24 08:10:19 AM UTC 24 | 423866498 ps | ||
| T890 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.4088075477 | Sep 24 08:10:17 AM UTC 24 | Sep 24 08:10:21 AM UTC 24 | 350478195 ps | ||
| T891 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.4186508448 | Sep 24 08:10:18 AM UTC 24 | Sep 24 08:10:21 AM UTC 24 | 396598770 ps | ||
| T892 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.1191987720 | Sep 24 08:10:17 AM UTC 24 | Sep 24 08:10:21 AM UTC 24 | 394097318 ps | ||
| T893 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2991567814 | Sep 24 08:09:56 AM UTC 24 | Sep 24 08:10:21 AM UTC 24 | 7692154731 ps | ||
| T894 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.2238493502 | Sep 24 08:10:19 AM UTC 24 | Sep 24 08:10:21 AM UTC 24 | 364754675 ps | ||
| T895 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1006325693 | Sep 24 08:10:15 AM UTC 24 | Sep 24 08:10:22 AM UTC 24 | 4853590519 ps | ||
| T896 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.79464739 | Sep 24 08:10:20 AM UTC 24 | Sep 24 08:10:22 AM UTC 24 | 422953128 ps | ||
| T897 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.3998012516 | Sep 24 08:10:18 AM UTC 24 | Sep 24 08:10:22 AM UTC 24 | 456962047 ps | ||
| T898 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/30.adc_ctrl_intr_test.516785888 | Sep 24 08:10:20 AM UTC 24 | Sep 24 08:10:22 AM UTC 24 | 466415639 ps | ||
| T899 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.1491133455 | Sep 24 08:10:20 AM UTC 24 | Sep 24 08:10:22 AM UTC 24 | 523092892 ps | ||
| T900 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/32.adc_ctrl_intr_test.179803950 | Sep 24 08:10:21 AM UTC 24 | Sep 24 08:10:23 AM UTC 24 | 348078201 ps | ||
| T901 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/31.adc_ctrl_intr_test.1522431239 | Sep 24 08:10:21 AM UTC 24 | Sep 24 08:10:24 AM UTC 24 | 476411899 ps | ||
| T902 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/41.adc_ctrl_intr_test.2900622714 | Sep 24 08:10:23 AM UTC 24 | Sep 24 08:10:27 AM UTC 24 | 359151310 ps | ||
| T903 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.496988746 | Sep 24 08:10:13 AM UTC 24 | Sep 24 08:10:24 AM UTC 24 | 8426675320 ps | ||
| T904 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/35.adc_ctrl_intr_test.273877399 | Sep 24 08:10:22 AM UTC 24 | Sep 24 08:10:24 AM UTC 24 | 326428123 ps | ||
| T905 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/36.adc_ctrl_intr_test.3218453945 | Sep 24 08:10:22 AM UTC 24 | Sep 24 08:10:25 AM UTC 24 | 349258873 ps | ||
| T906 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/37.adc_ctrl_intr_test.93393754 | Sep 24 08:10:22 AM UTC 24 | Sep 24 08:10:25 AM UTC 24 | 371353546 ps | ||
| T907 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/38.adc_ctrl_intr_test.3271623024 | Sep 24 08:10:22 AM UTC 24 | Sep 24 08:10:25 AM UTC 24 | 376324922 ps | ||
| T908 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/40.adc_ctrl_intr_test.1314605768 | Sep 24 08:10:23 AM UTC 24 | Sep 24 08:10:25 AM UTC 24 | 407130627 ps | ||
| T909 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/33.adc_ctrl_intr_test.3642995100 | Sep 24 08:10:22 AM UTC 24 | Sep 24 08:10:26 AM UTC 24 | 381033981 ps | ||
| T910 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/39.adc_ctrl_intr_test.2980967790 | Sep 24 08:10:23 AM UTC 24 | Sep 24 08:10:26 AM UTC 24 | 530856506 ps | ||
| T911 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/42.adc_ctrl_intr_test.1189762905 | Sep 24 08:10:23 AM UTC 24 | Sep 24 08:10:26 AM UTC 24 | 469387035 ps | ||
| T912 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/34.adc_ctrl_intr_test.2537783590 | Sep 24 08:10:22 AM UTC 24 | Sep 24 08:10:26 AM UTC 24 | 401076209 ps | ||
| T913 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/47.adc_ctrl_intr_test.2343088154 | Sep 24 08:10:25 AM UTC 24 | Sep 24 08:10:27 AM UTC 24 | 438140286 ps | ||
| T914 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/44.adc_ctrl_intr_test.889882348 | Sep 24 08:10:23 AM UTC 24 | Sep 24 08:10:28 AM UTC 24 | 400311636 ps | ||
| T915 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/46.adc_ctrl_intr_test.664732690 | Sep 24 08:10:25 AM UTC 24 | Sep 24 08:10:28 AM UTC 24 | 502909351 ps | ||
| T916 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/45.adc_ctrl_intr_test.1343894579 | Sep 24 08:10:24 AM UTC 24 | Sep 24 08:10:28 AM UTC 24 | 361133766 ps | ||
| T917 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/48.adc_ctrl_intr_test.995723274 | Sep 24 08:10:25 AM UTC 24 | Sep 24 08:10:29 AM UTC 24 | 413651912 ps | ||
| T918 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/49.adc_ctrl_intr_test.3782903756 | Sep 24 08:10:26 AM UTC 24 | Sep 24 08:10:30 AM UTC 24 | 430978583 ps | ||
| T919 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2677240825 | Sep 24 08:10:06 AM UTC 24 | Sep 24 08:10:35 AM UTC 24 | 8408810413 ps | ||
| T920 | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3298916611 | Sep 24 08:10:09 AM UTC 24 | Sep 24 08:10:43 AM UTC 24 | 8571513272 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.1348795866 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 192144008170 ps |
| CPU time | 37.76 seconds |
| Started | Sep 24 06:57:59 AM UTC 24 |
| Finished | Sep 24 06:58:38 AM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1348795866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.adc_ctrl_stress_all_with_rand_reset.1348795866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.95329295 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4157886818 ps |
| CPU time | 6.06 seconds |
| Started | Sep 24 06:58:18 AM UTC 24 |
| Finished | Sep 24 06:58:25 AM UTC 24 |
| Peak memory | 210760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95329295 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.95329295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.403876494 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 367705089099 ps |
| CPU time | 212.44 seconds |
| Started | Sep 24 06:58:07 AM UTC 24 |
| Finished | Sep 24 07:01:43 AM UTC 24 |
| Peak memory | 210720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403876494 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gating.403876494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/1.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.2776475148 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 102469781287 ps |
| CPU time | 430.99 seconds |
| Started | Sep 24 06:58:53 AM UTC 24 |
| Finished | Sep 24 07:06:08 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776475148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.2776475148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/3.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.2816056199 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 183396473410 ps |
| CPU time | 129.2 seconds |
| Started | Sep 24 06:58:48 AM UTC 24 |
| Finished | Sep 24 07:01:00 AM UTC 24 |
| Peak memory | 210768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816056199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.2816056199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/3.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_both.3360669066 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 501656315225 ps |
| CPU time | 388.08 seconds |
| Started | Sep 24 07:01:04 AM UTC 24 |
| Finished | Sep 24 07:07:38 AM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360669066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3360669066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/6.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_both.3654152234 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 531154678559 ps |
| CPU time | 276.52 seconds |
| Started | Sep 24 07:08:24 AM UTC 24 |
| Finished | Sep 24 07:13:04 AM UTC 24 |
| Peak memory | 210780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654152234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3654152234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/11.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_clock_gating.1566986655 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 497002000682 ps |
| CPU time | 1072.45 seconds |
| Started | Sep 24 06:57:54 AM UTC 24 |
| Finished | Sep 24 07:15:58 AM UTC 24 |
| Peak memory | 213496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566986655 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gating.1566986655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_fsm_reset.3343748651 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 111206821951 ps |
| CPU time | 483.49 seconds |
| Started | Sep 24 07:01:17 AM UTC 24 |
| Finished | Sep 24 07:09:26 AM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343748651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3343748651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/6.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1260232341 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 50820246432 ps |
| CPU time | 35.88 seconds |
| Started | Sep 24 06:58:17 AM UTC 24 |
| Finished | Sep 24 06:58:54 AM UTC 24 |
| Peak memory | 221740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1260232341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.adc_ctrl_stress_all_with_rand_reset.1260232341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all.3958550614 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 500004858954 ps |
| CPU time | 381.29 seconds |
| Started | Sep 24 07:03:17 AM UTC 24 |
| Finished | Sep 24 07:09:43 AM UTC 24 |
| Peak memory | 210784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958550614 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.3958550614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_clock_gating.891892447 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 531559009958 ps |
| CPU time | 737.76 seconds |
| Started | Sep 24 06:58:46 AM UTC 24 |
| Finished | Sep 24 07:11:12 AM UTC 24 |
| Peak memory | 210720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891892447 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gating.891892447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/3.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup.2062994201 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 555061212174 ps |
| CPU time | 588.5 seconds |
| Started | Sep 24 06:58:25 AM UTC 24 |
| Finished | Sep 24 07:08:22 AM UTC 24 |
| Peak memory | 211032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062994201 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_wakeup.2062994201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/2.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1899968523 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 469709287 ps |
| CPU time | 2.81 seconds |
| Started | Sep 24 08:08:56 AM UTC 24 |
| Finished | Sep 24 08:09:00 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899968523 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1899968523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/2.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_sec_cm.475441067 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 7926236898 ps |
| CPU time | 20.69 seconds |
| Started | Sep 24 06:58:37 AM UTC 24 |
| Finished | Sep 24 06:58:59 AM UTC 24 |
| Peak memory | 242720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475441067 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.475441067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/2.adc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_clock_gating.2558637720 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 348924550054 ps |
| CPU time | 729.15 seconds |
| Started | Sep 24 07:11:30 AM UTC 24 |
| Finished | Sep 24 07:23:47 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558637720 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gating.2558637720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/13.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1034189639 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 163053114364 ps |
| CPU time | 119.35 seconds |
| Started | Sep 24 06:58:03 AM UTC 24 |
| Finished | Sep 24 07:00:05 AM UTC 24 |
| Peak memory | 211032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034189639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt_fixed.1034189639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/1.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.3179522301 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 548227635512 ps |
| CPU time | 715.3 seconds |
| Started | Sep 24 07:09:50 AM UTC 24 |
| Finished | Sep 24 07:21:53 AM UTC 24 |
| Peak memory | 210772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179522301 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gating.3179522301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/12.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_clock_gating.2349694353 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 329880916974 ps |
| CPU time | 492.9 seconds |
| Started | Sep 24 07:17:10 AM UTC 24 |
| Finished | Sep 24 07:25:29 AM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349694353 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gating.2349694353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/16.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_clock_gating.2655033924 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 589921777365 ps |
| CPU time | 368.79 seconds |
| Started | Sep 24 07:08:23 AM UTC 24 |
| Finished | Sep 24 07:14:36 AM UTC 24 |
| Peak memory | 210772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655033924 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gating.2655033924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/11.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.4198512351 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 6742174251 ps |
| CPU time | 11.19 seconds |
| Started | Sep 24 08:08:35 AM UTC 24 |
| Finished | Sep 24 08:08:47 AM UTC 24 |
| Peak memory | 211504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198512351 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_bash.4198512351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/0.adc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all.2305618412 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 383106039588 ps |
| CPU time | 241.41 seconds |
| Started | Sep 24 07:06:10 AM UTC 24 |
| Finished | Sep 24 07:10:15 AM UTC 24 |
| Peak memory | 210776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305618412 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.2305618412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.2853981346 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 485775644865 ps |
| CPU time | 400.14 seconds |
| Started | Sep 24 07:00:40 AM UTC 24 |
| Finished | Sep 24 07:07:25 AM UTC 24 |
| Peak memory | 210796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853981346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.2853981346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/6.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup.1665349100 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 542354073278 ps |
| CPU time | 442.86 seconds |
| Started | Sep 24 07:00:55 AM UTC 24 |
| Finished | Sep 24 07:08:23 AM UTC 24 |
| Peak memory | 210708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665349100 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_wakeup.1665349100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/6.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt.3655973461 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 499402428150 ps |
| CPU time | 805.44 seconds |
| Started | Sep 24 07:11:01 AM UTC 24 |
| Finished | Sep 24 07:24:34 AM UTC 24 |
| Peak memory | 210796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655973461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3655973461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/13.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt.2812829941 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 493339923067 ps |
| CPU time | 669.87 seconds |
| Started | Sep 24 07:12:39 AM UTC 24 |
| Finished | Sep 24 07:23:56 AM UTC 24 |
| Peak memory | 210720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812829941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.2812829941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/14.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_clock_gating.474682087 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 357008336475 ps |
| CPU time | 602.15 seconds |
| Started | Sep 24 07:02:26 AM UTC 24 |
| Finished | Sep 24 07:12:35 AM UTC 24 |
| Peak memory | 210780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474682087 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gating.474682087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/7.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all.1026739506 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 677692132114 ps |
| CPU time | 1047.46 seconds |
| Started | Sep 24 07:09:01 AM UTC 24 |
| Finished | Sep 24 07:26:40 AM UTC 24 |
| Peak memory | 213420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026739506 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.1026739506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/11.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3940426565 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 125346630028 ps |
| CPU time | 33.1 seconds |
| Started | Sep 24 07:10:25 AM UTC 24 |
| Finished | Sep 24 07:11:00 AM UTC 24 |
| Peak memory | 225500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3940426565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 12.adc_ctrl_stress_all_with_rand_reset.3940426565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/12.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_interrupt.3078170530 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 490275051201 ps |
| CPU time | 686.81 seconds |
| Started | Sep 24 07:40:07 AM UTC 24 |
| Finished | Sep 24 07:51:42 AM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078170530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.3078170530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/32.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_clock_gating.2589938647 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 566251724906 ps |
| CPU time | 213.33 seconds |
| Started | Sep 24 07:48:08 AM UTC 24 |
| Finished | Sep 24 07:51:45 AM UTC 24 |
| Peak memory | 210772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589938647 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gating.2589938647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/37.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_both.1967364930 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 529923650426 ps |
| CPU time | 336.22 seconds |
| Started | Sep 24 07:42:04 AM UTC 24 |
| Finished | Sep 24 07:47:44 AM UTC 24 |
| Peak memory | 210784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967364930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1967364930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/33.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.741664484 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 7673595510 ps |
| CPU time | 9.41 seconds |
| Started | Sep 24 08:09:32 AM UTC 24 |
| Finished | Sep 24 08:09:43 AM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741664484 -assert nopostproc +UVM_TEST NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_intg_err.741664484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/7.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.2015835003 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 506586650 ps |
| CPU time | 3.44 seconds |
| Started | Sep 24 06:58:02 AM UTC 24 |
| Finished | Sep 24 06:58:06 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015835003 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2015835003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/0.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup.4209351053 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 538512255280 ps |
| CPU time | 254.35 seconds |
| Started | Sep 24 07:08:06 AM UTC 24 |
| Finished | Sep 24 07:12:23 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209351053 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_wakeup.4209351053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/11.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1038984486 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 6209211524 ps |
| CPU time | 9.96 seconds |
| Started | Sep 24 07:22:23 AM UTC 24 |
| Finished | Sep 24 07:22:34 AM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1038984486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 19.adc_ctrl_stress_all_with_rand_reset.1038984486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/19.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_smoke.3576500012 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5608858887 ps |
| CPU time | 28.6 seconds |
| Started | Sep 24 06:57:44 AM UTC 24 |
| Finished | Sep 24 06:58:14 AM UTC 24 |
| Peak memory | 210580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576500012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3576500012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/0.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_clock_gating.2540664816 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 564499850090 ps |
| CPU time | 677.2 seconds |
| Started | Sep 24 08:06:01 AM UTC 24 |
| Finished | Sep 24 08:17:25 AM UTC 24 |
| Peak memory | 210688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540664816 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gating.2540664816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/48.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_both.3669538988 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 527160483635 ps |
| CPU time | 1400.96 seconds |
| Started | Sep 24 07:30:27 AM UTC 24 |
| Finished | Sep 24 07:54:02 AM UTC 24 |
| Peak memory | 213488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669538988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.3669538988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/26.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_stress_all.3944877147 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 336667139129 ps |
| CPU time | 225.94 seconds |
| Started | Sep 24 07:53:53 AM UTC 24 |
| Finished | Sep 24 07:57:42 AM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944877147 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.3944877147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/40.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_stress_all.2030528111 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 371882015769 ps |
| CPU time | 212.49 seconds |
| Started | Sep 24 07:24:35 AM UTC 24 |
| Finished | Sep 24 07:28:10 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030528111 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.2030528111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/21.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_clock_gating.3368959785 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 160452490389 ps |
| CPU time | 195.05 seconds |
| Started | Sep 24 07:23:56 AM UTC 24 |
| Finished | Sep 24 07:27:14 AM UTC 24 |
| Peak memory | 210844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368959785 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gating.3368959785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/21.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup.3990458069 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 365298436324 ps |
| CPU time | 398 seconds |
| Started | Sep 24 07:14:04 AM UTC 24 |
| Finished | Sep 24 07:20:47 AM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990458069 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_wakeup.3990458069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/15.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_wakeup.3245952556 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 351161135462 ps |
| CPU time | 857.1 seconds |
| Started | Sep 24 07:26:15 AM UTC 24 |
| Finished | Sep 24 07:40:41 AM UTC 24 |
| Peak memory | 213424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245952556 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_wakeup.3245952556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/23.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt.3372975573 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 488539023071 ps |
| CPU time | 1337.61 seconds |
| Started | Sep 24 06:58:03 AM UTC 24 |
| Finished | Sep 24 07:20:34 AM UTC 24 |
| Peak memory | 213368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372975573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.3372975573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/1.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.3838627031 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 535144763289 ps |
| CPU time | 92.12 seconds |
| Started | Sep 24 07:07:08 AM UTC 24 |
| Finished | Sep 24 07:08:43 AM UTC 24 |
| Peak memory | 211036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838627031 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gating.3838627031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/10.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_clock_gating.3107309473 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 556753689718 ps |
| CPU time | 1322.54 seconds |
| Started | Sep 24 07:43:15 AM UTC 24 |
| Finished | Sep 24 08:05:30 AM UTC 24 |
| Peak memory | 213364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107309473 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gating.3107309473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/34.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all.2936253891 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 470026756917 ps |
| CPU time | 1707.13 seconds |
| Started | Sep 24 07:27:29 AM UTC 24 |
| Finished | Sep 24 07:56:13 AM UTC 24 |
| Peak memory | 213748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936253891 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.2936253891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/23.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.561667105 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 6663310365 ps |
| CPU time | 8.89 seconds |
| Started | Sep 24 07:58:34 AM UTC 24 |
| Finished | Sep 24 07:58:44 AM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=561667105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.561667105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/44.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_interrupt.1003227145 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 492825033843 ps |
| CPU time | 467.11 seconds |
| Started | Sep 24 07:21:30 AM UTC 24 |
| Finished | Sep 24 07:29:23 AM UTC 24 |
| Peak memory | 210728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003227145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.1003227145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/19.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.741434059 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 4253602941 ps |
| CPU time | 15.38 seconds |
| Started | Sep 24 08:08:39 AM UTC 24 |
| Finished | Sep 24 08:08:55 AM UTC 24 |
| Peak memory | 211408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741434059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_same_csr_outstanding.741434059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/0.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all.723115280 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 280463721018 ps |
| CPU time | 665.41 seconds |
| Started | Sep 24 07:07:41 AM UTC 24 |
| Finished | Sep 24 07:18:54 AM UTC 24 |
| Peak memory | 223512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723115280 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.723115280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/10.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3426907203 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 405244455472 ps |
| CPU time | 239.43 seconds |
| Started | Sep 24 07:09:49 AM UTC 24 |
| Finished | Sep 24 07:13:51 AM UTC 24 |
| Peak memory | 210832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426907203 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_wakeup_fixed.3426907203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/12.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all.2023670900 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 328234949102 ps |
| CPU time | 1010.82 seconds |
| Started | Sep 24 07:19:47 AM UTC 24 |
| Finished | Sep 24 07:36:48 AM UTC 24 |
| Peak memory | 213688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023670900 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.2023670900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.406045539 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 9409935643 ps |
| CPU time | 5.88 seconds |
| Started | Sep 24 07:07:40 AM UTC 24 |
| Finished | Sep 24 07:07:47 AM UTC 24 |
| Peak memory | 221072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=406045539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.406045539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/10.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_clock_gating.1291806265 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 498639819076 ps |
| CPU time | 1562.13 seconds |
| Started | Sep 24 07:14:27 AM UTC 24 |
| Finished | Sep 24 07:40:45 AM UTC 24 |
| Peak memory | 213424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291806265 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gating.1291806265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/15.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_clock_gating.1314447183 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 493171946067 ps |
| CPU time | 603.79 seconds |
| Started | Sep 24 07:22:54 AM UTC 24 |
| Finished | Sep 24 07:33:05 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314447183 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gating.1314447183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/20.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_wakeup.1272121717 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 552563340361 ps |
| CPU time | 634.22 seconds |
| Started | Sep 24 07:33:18 AM UTC 24 |
| Finished | Sep 24 07:43:59 AM UTC 24 |
| Peak memory | 210784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272121717 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_wakeup.1272121717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/28.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_polled.4290343939 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 330291917667 ps |
| CPU time | 204.33 seconds |
| Started | Sep 24 08:00:07 AM UTC 24 |
| Finished | Sep 24 08:03:34 AM UTC 24 |
| Peak memory | 210792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290343939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.4290343939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/46.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_both.2026500017 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 164373484064 ps |
| CPU time | 120.79 seconds |
| Started | Sep 24 07:11:31 AM UTC 24 |
| Finished | Sep 24 07:13:34 AM UTC 24 |
| Peak memory | 210780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026500017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.2026500017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/13.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all.524403780 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 278882213502 ps |
| CPU time | 677.42 seconds |
| Started | Sep 24 07:36:26 AM UTC 24 |
| Finished | Sep 24 07:47:51 AM UTC 24 |
| Peak memory | 223320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524403780 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.524403780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/29.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_stress_all.3031994008 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 604974588572 ps |
| CPU time | 2153.18 seconds |
| Started | Sep 24 07:42:29 AM UTC 24 |
| Finished | Sep 24 08:18:44 AM UTC 24 |
| Peak memory | 225956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031994008 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.3031994008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/33.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2586669252 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 8428268257 ps |
| CPU time | 23.68 seconds |
| Started | Sep 24 08:08:24 AM UTC 24 |
| Finished | Sep 24 08:08:49 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586669252 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_intg_err.2586669252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/0.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt.2534403075 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 162968700670 ps |
| CPU time | 282.02 seconds |
| Started | Sep 24 07:13:42 AM UTC 24 |
| Finished | Sep 24 07:18:27 AM UTC 24 |
| Peak memory | 210780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534403075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.2534403075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/15.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_clock_gating.3095065015 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 355894467818 ps |
| CPU time | 420.65 seconds |
| Started | Sep 24 07:21:53 AM UTC 24 |
| Finished | Sep 24 07:28:58 AM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095065015 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gating.3095065015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/19.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3967236688 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 33738473113 ps |
| CPU time | 28.62 seconds |
| Started | Sep 24 07:39:38 AM UTC 24 |
| Finished | Sep 24 07:40:08 AM UTC 24 |
| Peak memory | 221056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3967236688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 31.adc_ctrl_stress_all_with_rand_reset.3967236688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/31.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_wakeup.4069117738 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 457672893504 ps |
| CPU time | 1341.74 seconds |
| Started | Sep 24 07:52:21 AM UTC 24 |
| Finished | Sep 24 08:14:57 AM UTC 24 |
| Peak memory | 213496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069117738 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_wakeup.4069117738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/40.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_fsm_reset.151313398 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 83343127943 ps |
| CPU time | 340.96 seconds |
| Started | Sep 24 07:07:37 AM UTC 24 |
| Finished | Sep 24 07:13:22 AM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151313398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.151313398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/10.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled.2070274901 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 491363350651 ps |
| CPU time | 1142.67 seconds |
| Started | Sep 24 07:09:24 AM UTC 24 |
| Finished | Sep 24 07:28:39 AM UTC 24 |
| Peak memory | 213364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070274901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.2070274901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/12.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.103082370 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 2600447541 ps |
| CPU time | 8.15 seconds |
| Started | Sep 24 07:15:31 AM UTC 24 |
| Finished | Sep 24 07:15:41 AM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=103082370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.103082370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled.1137407254 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 163432014512 ps |
| CPU time | 217.58 seconds |
| Started | Sep 24 07:21:13 AM UTC 24 |
| Finished | Sep 24 07:24:54 AM UTC 24 |
| Peak memory | 210716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137407254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1137407254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/19.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all.3468915809 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 172270678740 ps |
| CPU time | 133.4 seconds |
| Started | Sep 24 07:22:23 AM UTC 24 |
| Finished | Sep 24 07:24:39 AM UTC 24 |
| Peak memory | 210708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468915809 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.3468915809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/19.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_wakeup.3348574943 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 512013981224 ps |
| CPU time | 436.17 seconds |
| Started | Sep 24 07:23:53 AM UTC 24 |
| Finished | Sep 24 07:31:15 AM UTC 24 |
| Peak memory | 210772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348574943 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_wakeup.3348574943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/21.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_both.3926768317 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 342704655833 ps |
| CPU time | 551.29 seconds |
| Started | Sep 24 07:28:59 AM UTC 24 |
| Finished | Sep 24 07:38:16 AM UTC 24 |
| Peak memory | 210800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926768317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3926768317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/25.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_clock_gating.1915668551 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 524103118877 ps |
| CPU time | 772.28 seconds |
| Started | Sep 24 07:38:42 AM UTC 24 |
| Finished | Sep 24 07:51:43 AM UTC 24 |
| Peak memory | 210868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915668551 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gating.1915668551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/31.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_stress_all.3115810103 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 665288126978 ps |
| CPU time | 1661.67 seconds |
| Started | Sep 24 07:39:42 AM UTC 24 |
| Finished | Sep 24 08:07:40 AM UTC 24 |
| Peak memory | 213692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115810103 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.3115810103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/31.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_fsm_reset.2485942238 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 70047696314 ps |
| CPU time | 448.73 seconds |
| Started | Sep 24 07:40:55 AM UTC 24 |
| Finished | Sep 24 07:48:29 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485942238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.2485942238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/32.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_clock_gating.1807200448 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 490239640327 ps |
| CPU time | 1246.66 seconds |
| Started | Sep 24 07:55:02 AM UTC 24 |
| Finished | Sep 24 08:16:01 AM UTC 24 |
| Peak memory | 213388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807200448 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gating.1807200448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/41.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all.2363501005 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 1760353084764 ps |
| CPU time | 3315.64 seconds |
| Started | Sep 24 07:01:34 AM UTC 24 |
| Finished | Sep 24 07:57:22 AM UTC 24 |
| Peak memory | 230304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363501005 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.2363501005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/6.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_both.723983724 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 168276115219 ps |
| CPU time | 116.92 seconds |
| Started | Sep 24 06:57:55 AM UTC 24 |
| Finished | Sep 24 06:59:54 AM UTC 24 |
| Peak memory | 210776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723983724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.723983724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/0.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup.4276935096 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 596681172586 ps |
| CPU time | 1564.84 seconds |
| Started | Sep 24 06:58:05 AM UTC 24 |
| Finished | Sep 24 07:24:25 AM UTC 24 |
| Peak memory | 213772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276935096 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_wakeup.4276935096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/1.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all.133161735 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 283286408661 ps |
| CPU time | 694.03 seconds |
| Started | Sep 24 07:10:28 AM UTC 24 |
| Finished | Sep 24 07:22:10 AM UTC 24 |
| Peak memory | 223320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133161735 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.133161735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/12.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup.2527727513 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 185725501087 ps |
| CPU time | 109.84 seconds |
| Started | Sep 24 07:11:13 AM UTC 24 |
| Finished | Sep 24 07:13:05 AM UTC 24 |
| Peak memory | 210772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527727513 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_wakeup.2527727513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/13.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all.2271105125 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 593267646978 ps |
| CPU time | 712.4 seconds |
| Started | Sep 24 07:13:21 AM UTC 24 |
| Finished | Sep 24 07:25:21 AM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271105125 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.2271105125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/14.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all.164788299 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 347617489940 ps |
| CPU time | 514.66 seconds |
| Started | Sep 24 07:18:28 AM UTC 24 |
| Finished | Sep 24 07:27:08 AM UTC 24 |
| Peak memory | 210680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164788299 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.164788299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/16.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_fsm_reset.3602107728 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 99162461846 ps |
| CPU time | 699.69 seconds |
| Started | Sep 24 07:24:28 AM UTC 24 |
| Finished | Sep 24 07:36:15 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602107728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.3602107728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/21.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_both.2536281102 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 323907430921 ps |
| CPU time | 594.25 seconds |
| Started | Sep 24 07:27:09 AM UTC 24 |
| Finished | Sep 24 07:37:09 AM UTC 24 |
| Peak memory | 210788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536281102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2536281102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/23.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_fsm_reset.156239943 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 124589951932 ps |
| CPU time | 554.93 seconds |
| Started | Sep 24 07:32:41 AM UTC 24 |
| Finished | Sep 24 07:42:03 AM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156239943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.156239943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/27.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_fsm_reset.916755129 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 71199626736 ps |
| CPU time | 516.02 seconds |
| Started | Sep 24 07:39:28 AM UTC 24 |
| Finished | Sep 24 07:48:10 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916755129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.916755129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/31.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_stress_all.1620171170 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 336698445908 ps |
| CPU time | 333.34 seconds |
| Started | Sep 24 07:41:14 AM UTC 24 |
| Finished | Sep 24 07:46:51 AM UTC 24 |
| Peak memory | 210848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620171170 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all.1620171170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/32.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_interrupt.3187875674 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 324964709805 ps |
| CPU time | 734.61 seconds |
| Started | Sep 24 07:46:12 AM UTC 24 |
| Finished | Sep 24 07:58:34 AM UTC 24 |
| Peak memory | 210804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187875674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3187875674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/36.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_stress_all.3654210500 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 372598783502 ps |
| CPU time | 877.25 seconds |
| Started | Sep 24 07:58:42 AM UTC 24 |
| Finished | Sep 24 08:13:28 AM UTC 24 |
| Peak memory | 221272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654210500 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.3654210500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/44.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_both.2223799298 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 361609427279 ps |
| CPU time | 287.12 seconds |
| Started | Sep 24 08:06:04 AM UTC 24 |
| Finished | Sep 24 08:10:55 AM UTC 24 |
| Peak memory | 210860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223799298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2223799298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/48.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.591357807 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 1054892289 ps |
| CPU time | 8.93 seconds |
| Started | Sep 24 08:08:38 AM UTC 24 |
| Finished | Sep 24 08:08:48 AM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591357807 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_aliasing.591357807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/0.adc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2490190698 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 864911827 ps |
| CPU time | 3.21 seconds |
| Started | Sep 24 08:08:34 AM UTC 24 |
| Finished | Sep 24 08:08:38 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490190698 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_reset.2490190698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/0.adc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1973646057 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 391685608 ps |
| CPU time | 3.16 seconds |
| Started | Sep 24 08:08:40 AM UTC 24 |
| Finished | Sep 24 08:08:44 AM UTC 24 |
| Peak memory | 211268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1973646057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_cs r_mem_rw_with_rand_reset.1973646057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2389644823 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 623060239 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 08:08:35 AM UTC 24 |
| Finished | Sep 24 08:08:37 AM UTC 24 |
| Peak memory | 210032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389644823 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2389644823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/0.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.4036073032 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 542758063 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:08:31 AM UTC 24 |
| Finished | Sep 24 08:08:34 AM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036073032 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.4036073032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/0.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.516327234 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 573968752 ps |
| CPU time | 6.05 seconds |
| Started | Sep 24 08:08:23 AM UTC 24 |
| Finished | Sep 24 08:08:31 AM UTC 24 |
| Peak memory | 227568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516327234 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.516327234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/0.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3650933454 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 872496735 ps |
| CPU time | 3.02 seconds |
| Started | Sep 24 08:08:53 AM UTC 24 |
| Finished | Sep 24 08:08:57 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650933454 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_aliasing.3650933454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/1.adc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.754874200 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 7211353393 ps |
| CPU time | 18.71 seconds |
| Started | Sep 24 08:08:52 AM UTC 24 |
| Finished | Sep 24 08:09:12 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754874200 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_bash.754874200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/1.adc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.672053626 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 891846267 ps |
| CPU time | 2.04 seconds |
| Started | Sep 24 08:08:50 AM UTC 24 |
| Finished | Sep 24 08:08:53 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672053626 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_reset.672053626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/1.adc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2159872530 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 427018689 ps |
| CPU time | 3.26 seconds |
| Started | Sep 24 08:08:55 AM UTC 24 |
| Finished | Sep 24 08:09:00 AM UTC 24 |
| Peak memory | 211260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2159872530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_cs r_mem_rw_with_rand_reset.2159872530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1521520438 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 491423111 ps |
| CPU time | 3.53 seconds |
| Started | Sep 24 08:08:50 AM UTC 24 |
| Finished | Sep 24 08:08:55 AM UTC 24 |
| Peak memory | 211328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521520438 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.1521520438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/1.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.3877182227 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 584481673 ps |
| CPU time | 1.12 seconds |
| Started | Sep 24 08:08:49 AM UTC 24 |
| Finished | Sep 24 08:08:51 AM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877182227 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3877182227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/1.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1811316524 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 5120934371 ps |
| CPU time | 5.22 seconds |
| Started | Sep 24 08:08:54 AM UTC 24 |
| Finished | Sep 24 08:09:01 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811316524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_same_csr_outstanding.1811316524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/1.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2810751614 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 799742054 ps |
| CPU time | 3.49 seconds |
| Started | Sep 24 08:08:45 AM UTC 24 |
| Finished | Sep 24 08:08:49 AM UTC 24 |
| Peak memory | 227480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810751614 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2810751614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/1.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2080172293 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 4222244576 ps |
| CPU time | 10.83 seconds |
| Started | Sep 24 08:08:48 AM UTC 24 |
| Finished | Sep 24 08:09:00 AM UTC 24 |
| Peak memory | 211456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080172293 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_intg_err.2080172293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/1.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2778432901 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 380935185 ps |
| CPU time | 1.7 seconds |
| Started | Sep 24 08:09:45 AM UTC 24 |
| Finished | Sep 24 08:09:48 AM UTC 24 |
| Peak memory | 209916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2778432901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_c sr_mem_rw_with_rand_reset.2778432901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2258189363 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 563688636 ps |
| CPU time | 3.72 seconds |
| Started | Sep 24 08:09:44 AM UTC 24 |
| Finished | Sep 24 08:09:49 AM UTC 24 |
| Peak memory | 211192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258189363 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.2258189363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/10.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.776189994 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 351171239 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 08:09:43 AM UTC 24 |
| Finished | Sep 24 08:09:45 AM UTC 24 |
| Peak memory | 209968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776189994 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.776189994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/10.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2163118913 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 2450229139 ps |
| CPU time | 2.25 seconds |
| Started | Sep 24 08:09:44 AM UTC 24 |
| Finished | Sep 24 08:09:47 AM UTC 24 |
| Peak memory | 211332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163118913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_same_csr_outstanding.2163118913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/10.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.311433659 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 558265708 ps |
| CPU time | 2.66 seconds |
| Started | Sep 24 08:09:42 AM UTC 24 |
| Finished | Sep 24 08:09:46 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311433659 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.311433659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/10.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2065621854 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 8437729578 ps |
| CPU time | 8.77 seconds |
| Started | Sep 24 08:09:43 AM UTC 24 |
| Finished | Sep 24 08:09:53 AM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065621854 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_intg_err.2065621854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/10.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.539599119 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 482270320 ps |
| CPU time | 2.8 seconds |
| Started | Sep 24 08:09:48 AM UTC 24 |
| Finished | Sep 24 08:09:52 AM UTC 24 |
| Peak memory | 211200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=539599119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_cs r_mem_rw_with_rand_reset.539599119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1289847563 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 445720707 ps |
| CPU time | 3.1 seconds |
| Started | Sep 24 08:09:46 AM UTC 24 |
| Finished | Sep 24 08:09:50 AM UTC 24 |
| Peak memory | 211192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289847563 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1289847563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/11.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.3651604557 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 366488159 ps |
| CPU time | 1.78 seconds |
| Started | Sep 24 08:09:46 AM UTC 24 |
| Finished | Sep 24 08:09:49 AM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651604557 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3651604557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/11.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.119948989 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 2112852111 ps |
| CPU time | 5.35 seconds |
| Started | Sep 24 08:09:48 AM UTC 24 |
| Finished | Sep 24 08:09:55 AM UTC 24 |
| Peak memory | 211192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119948989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_same_csr_outstanding.119948989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/11.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.371781165 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 1148270245 ps |
| CPU time | 3.83 seconds |
| Started | Sep 24 08:09:45 AM UTC 24 |
| Finished | Sep 24 08:09:50 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371781165 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.371781165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/11.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1578462283 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 4327315962 ps |
| CPU time | 11.73 seconds |
| Started | Sep 24 08:09:45 AM UTC 24 |
| Finished | Sep 24 08:09:58 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578462283 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_intg_err.1578462283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/11.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3736726744 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 590059418 ps |
| CPU time | 2.13 seconds |
| Started | Sep 24 08:09:52 AM UTC 24 |
| Finished | Sep 24 08:09:55 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3736726744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_c sr_mem_rw_with_rand_reset.3736726744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1875150720 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 364344892 ps |
| CPU time | 1.91 seconds |
| Started | Sep 24 08:09:51 AM UTC 24 |
| Finished | Sep 24 08:09:54 AM UTC 24 |
| Peak memory | 209992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875150720 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.1875150720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/12.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.3986510587 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 354364005 ps |
| CPU time | 2.41 seconds |
| Started | Sep 24 08:09:50 AM UTC 24 |
| Finished | Sep 24 08:09:53 AM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986510587 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3986510587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/12.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3606026347 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 2168827458 ps |
| CPU time | 8.58 seconds |
| Started | Sep 24 08:09:51 AM UTC 24 |
| Finished | Sep 24 08:10:00 AM UTC 24 |
| Peak memory | 211244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606026347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_same_csr_outstanding.3606026347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/12.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1141393299 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 869339864 ps |
| CPU time | 2.36 seconds |
| Started | Sep 24 08:09:48 AM UTC 24 |
| Finished | Sep 24 08:09:52 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141393299 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.1141393299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/12.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2359879876 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 8009980278 ps |
| CPU time | 10.29 seconds |
| Started | Sep 24 08:09:50 AM UTC 24 |
| Finished | Sep 24 08:10:01 AM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359879876 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_intg_err.2359879876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/12.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2193485340 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 571122740 ps |
| CPU time | 3.47 seconds |
| Started | Sep 24 08:09:55 AM UTC 24 |
| Finished | Sep 24 08:10:00 AM UTC 24 |
| Peak memory | 211268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2193485340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_c sr_mem_rw_with_rand_reset.2193485340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1789682461 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 463877018 ps |
| CPU time | 3.04 seconds |
| Started | Sep 24 08:09:54 AM UTC 24 |
| Finished | Sep 24 08:09:58 AM UTC 24 |
| Peak memory | 211128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789682461 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.1789682461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/13.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.2686048878 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 316082711 ps |
| CPU time | 1.6 seconds |
| Started | Sep 24 08:09:54 AM UTC 24 |
| Finished | Sep 24 08:09:57 AM UTC 24 |
| Peak memory | 210384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686048878 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.2686048878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/13.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2852407652 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 2024598455 ps |
| CPU time | 3.38 seconds |
| Started | Sep 24 08:09:54 AM UTC 24 |
| Finished | Sep 24 08:09:58 AM UTC 24 |
| Peak memory | 211200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852407652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_same_csr_outstanding.2852407652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/13.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1980398921 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 571961691 ps |
| CPU time | 3.21 seconds |
| Started | Sep 24 08:09:53 AM UTC 24 |
| Finished | Sep 24 08:09:57 AM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980398921 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.1980398921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/13.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2302558758 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 4118070173 ps |
| CPU time | 5.58 seconds |
| Started | Sep 24 08:09:53 AM UTC 24 |
| Finished | Sep 24 08:09:59 AM UTC 24 |
| Peak memory | 211464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302558758 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_intg_err.2302558758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/13.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.178326696 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 399483476 ps |
| CPU time | 1.62 seconds |
| Started | Sep 24 08:09:59 AM UTC 24 |
| Finished | Sep 24 08:10:02 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=178326696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_cs r_mem_rw_with_rand_reset.178326696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2800225272 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 330409077 ps |
| CPU time | 2.43 seconds |
| Started | Sep 24 08:09:58 AM UTC 24 |
| Finished | Sep 24 08:10:02 AM UTC 24 |
| Peak memory | 211192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800225272 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2800225272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/14.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.2741506940 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 341377842 ps |
| CPU time | 2.36 seconds |
| Started | Sep 24 08:09:57 AM UTC 24 |
| Finished | Sep 24 08:10:01 AM UTC 24 |
| Peak memory | 211264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741506940 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.2741506940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/14.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1121690896 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 2155967116 ps |
| CPU time | 7.34 seconds |
| Started | Sep 24 08:09:59 AM UTC 24 |
| Finished | Sep 24 08:10:08 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121690896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_same_csr_outstanding.1121690896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/14.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1576407238 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 425956721 ps |
| CPU time | 4.62 seconds |
| Started | Sep 24 08:09:56 AM UTC 24 |
| Finished | Sep 24 08:10:02 AM UTC 24 |
| Peak memory | 221332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576407238 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1576407238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/14.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2991567814 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 7692154731 ps |
| CPU time | 23.79 seconds |
| Started | Sep 24 08:09:56 AM UTC 24 |
| Finished | Sep 24 08:10:21 AM UTC 24 |
| Peak memory | 211616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991567814 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_intg_err.2991567814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/14.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.4153816607 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 460462324 ps |
| CPU time | 2.06 seconds |
| Started | Sep 24 08:10:02 AM UTC 24 |
| Finished | Sep 24 08:10:05 AM UTC 24 |
| Peak memory | 211268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4153816607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_c sr_mem_rw_with_rand_reset.4153816607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.261259883 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 347698196 ps |
| CPU time | 1.92 seconds |
| Started | Sep 24 08:10:02 AM UTC 24 |
| Finished | Sep 24 08:10:05 AM UTC 24 |
| Peak memory | 209848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261259883 -assert nopostproc +UVM_TESTNAME=adc_ ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.261259883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/15.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.2501384302 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 338934033 ps |
| CPU time | 1.28 seconds |
| Started | Sep 24 08:10:01 AM UTC 24 |
| Finished | Sep 24 08:10:03 AM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501384302 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.2501384302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/15.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3110661059 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 5617524962 ps |
| CPU time | 13.72 seconds |
| Started | Sep 24 08:10:02 AM UTC 24 |
| Finished | Sep 24 08:10:17 AM UTC 24 |
| Peak memory | 211608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110661059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_same_csr_outstanding.3110661059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/15.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.485819288 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 476329873 ps |
| CPU time | 4.27 seconds |
| Started | Sep 24 08:09:59 AM UTC 24 |
| Finished | Sep 24 08:10:05 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485819288 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.485819288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/15.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1159908112 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 4516084113 ps |
| CPU time | 7.53 seconds |
| Started | Sep 24 08:10:01 AM UTC 24 |
| Finished | Sep 24 08:10:09 AM UTC 24 |
| Peak memory | 211408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159908112 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_intg_err.1159908112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/15.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1678885637 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 558778842 ps |
| CPU time | 2.73 seconds |
| Started | Sep 24 08:10:06 AM UTC 24 |
| Finished | Sep 24 08:10:10 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1678885637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_c sr_mem_rw_with_rand_reset.1678885637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1375465390 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 370451441 ps |
| CPU time | 2.62 seconds |
| Started | Sep 24 08:10:04 AM UTC 24 |
| Finished | Sep 24 08:10:08 AM UTC 24 |
| Peak memory | 211120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375465390 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.1375465390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/16.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.4287328448 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 408043431 ps |
| CPU time | 1.85 seconds |
| Started | Sep 24 08:10:03 AM UTC 24 |
| Finished | Sep 24 08:10:06 AM UTC 24 |
| Peak memory | 209848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287328448 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.4287328448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/16.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.267392183 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 2444492947 ps |
| CPU time | 4.63 seconds |
| Started | Sep 24 08:10:05 AM UTC 24 |
| Finished | Sep 24 08:10:11 AM UTC 24 |
| Peak memory | 211392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267392183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_same_csr_outstanding.267392183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/16.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3679664291 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 871991322 ps |
| CPU time | 2.45 seconds |
| Started | Sep 24 08:10:03 AM UTC 24 |
| Finished | Sep 24 08:10:06 AM UTC 24 |
| Peak memory | 227484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679664291 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.3679664291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/16.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.262422485 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 8698126373 ps |
| CPU time | 13.19 seconds |
| Started | Sep 24 08:10:03 AM UTC 24 |
| Finished | Sep 24 08:10:17 AM UTC 24 |
| Peak memory | 211472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262422485 -assert nopostproc +UVM_TEST NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_intg_err.262422485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/16.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.565503292 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 718059436 ps |
| CPU time | 1.82 seconds |
| Started | Sep 24 08:10:08 AM UTC 24 |
| Finished | Sep 24 08:10:12 AM UTC 24 |
| Peak memory | 209852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=565503292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_cs r_mem_rw_with_rand_reset.565503292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.512812641 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 364921661 ps |
| CPU time | 2.14 seconds |
| Started | Sep 24 08:10:07 AM UTC 24 |
| Finished | Sep 24 08:10:10 AM UTC 24 |
| Peak memory | 211264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512812641 -assert nopostproc +UVM_TESTNAME=adc_ ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.512812641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/17.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.455647981 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 326631230 ps |
| CPU time | 1.7 seconds |
| Started | Sep 24 08:10:07 AM UTC 24 |
| Finished | Sep 24 08:10:10 AM UTC 24 |
| Peak memory | 210388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455647981 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.455647981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/17.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.4078745714 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 4887425009 ps |
| CPU time | 6.79 seconds |
| Started | Sep 24 08:10:07 AM UTC 24 |
| Finished | Sep 24 08:10:15 AM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078745714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_same_csr_outstanding.4078745714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/17.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.885329105 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 477136743 ps |
| CPU time | 4.32 seconds |
| Started | Sep 24 08:10:06 AM UTC 24 |
| Finished | Sep 24 08:10:12 AM UTC 24 |
| Peak memory | 211420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885329105 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.885329105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/17.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2677240825 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 8408810413 ps |
| CPU time | 27.36 seconds |
| Started | Sep 24 08:10:06 AM UTC 24 |
| Finished | Sep 24 08:10:35 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677240825 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_intg_err.2677240825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/17.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3063740696 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 500909770 ps |
| CPU time | 1.94 seconds |
| Started | Sep 24 08:10:12 AM UTC 24 |
| Finished | Sep 24 08:10:15 AM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3063740696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_c sr_mem_rw_with_rand_reset.3063740696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2838525584 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 543165127 ps |
| CPU time | 3.68 seconds |
| Started | Sep 24 08:10:11 AM UTC 24 |
| Finished | Sep 24 08:10:16 AM UTC 24 |
| Peak memory | 211128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838525584 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.2838525584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/18.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.293628069 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 320798915 ps |
| CPU time | 1.39 seconds |
| Started | Sep 24 08:10:11 AM UTC 24 |
| Finished | Sep 24 08:10:13 AM UTC 24 |
| Peak memory | 210388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293628069 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.293628069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/18.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1322885822 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 4611278803 ps |
| CPU time | 6.93 seconds |
| Started | Sep 24 08:10:11 AM UTC 24 |
| Finished | Sep 24 08:10:19 AM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322885822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_same_csr_outstanding.1322885822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/18.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.128764448 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 593798697 ps |
| CPU time | 3.31 seconds |
| Started | Sep 24 08:10:09 AM UTC 24 |
| Finished | Sep 24 08:10:14 AM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128764448 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.128764448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/18.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3298916611 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 8571513272 ps |
| CPU time | 31.27 seconds |
| Started | Sep 24 08:10:09 AM UTC 24 |
| Finished | Sep 24 08:10:43 AM UTC 24 |
| Peak memory | 211676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298916611 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_intg_err.3298916611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/18.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.377294710 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 461237900 ps |
| CPU time | 1.99 seconds |
| Started | Sep 24 08:10:16 AM UTC 24 |
| Finished | Sep 24 08:10:19 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=377294710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_cs r_mem_rw_with_rand_reset.377294710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1249368621 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 427218698 ps |
| CPU time | 2.05 seconds |
| Started | Sep 24 08:10:14 AM UTC 24 |
| Finished | Sep 24 08:10:17 AM UTC 24 |
| Peak memory | 211264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249368621 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.1249368621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/19.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.2027953952 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 400482569 ps |
| CPU time | 1.12 seconds |
| Started | Sep 24 08:10:13 AM UTC 24 |
| Finished | Sep 24 08:10:15 AM UTC 24 |
| Peak memory | 210096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027953952 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2027953952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/19.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1006325693 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 4853590519 ps |
| CPU time | 5.5 seconds |
| Started | Sep 24 08:10:15 AM UTC 24 |
| Finished | Sep 24 08:10:22 AM UTC 24 |
| Peak memory | 211480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006325693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_same_csr_outstanding.1006325693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/19.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3117506481 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 419037580 ps |
| CPU time | 5.16 seconds |
| Started | Sep 24 08:10:12 AM UTC 24 |
| Finished | Sep 24 08:10:18 AM UTC 24 |
| Peak memory | 221360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117506481 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3117506481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/19.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.496988746 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 8426675320 ps |
| CPU time | 9.73 seconds |
| Started | Sep 24 08:10:13 AM UTC 24 |
| Finished | Sep 24 08:10:24 AM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496988746 -assert nopostproc +UVM_TEST NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_intg_err.496988746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/19.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.273973649 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 998617991 ps |
| CPU time | 3.18 seconds |
| Started | Sep 24 08:09:01 AM UTC 24 |
| Finished | Sep 24 08:09:05 AM UTC 24 |
| Peak memory | 211420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273973649 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_aliasing.273973649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/2.adc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.4179699421 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 903824520 ps |
| CPU time | 8.28 seconds |
| Started | Sep 24 08:09:01 AM UTC 24 |
| Finished | Sep 24 08:09:10 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179699421 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_bash.4179699421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/2.adc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.678841275 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1315973949 ps |
| CPU time | 6.43 seconds |
| Started | Sep 24 08:09:01 AM UTC 24 |
| Finished | Sep 24 08:09:08 AM UTC 24 |
| Peak memory | 211200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678841275 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_reset.678841275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/2.adc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.82143998 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 323569783 ps |
| CPU time | 2.47 seconds |
| Started | Sep 24 08:09:05 AM UTC 24 |
| Finished | Sep 24 08:09:08 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=82143998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_ mem_rw_with_rand_reset.82143998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.519869028 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 545288692 ps |
| CPU time | 2.48 seconds |
| Started | Sep 24 08:09:01 AM UTC 24 |
| Finished | Sep 24 08:09:04 AM UTC 24 |
| Peak memory | 211200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519869028 -assert nopostproc +UVM_TESTNAME=adc_ ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.519869028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/2.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.1977809137 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 480175445 ps |
| CPU time | 3.17 seconds |
| Started | Sep 24 08:09:01 AM UTC 24 |
| Finished | Sep 24 08:09:05 AM UTC 24 |
| Peak memory | 211088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977809137 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.1977809137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/2.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3608175207 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 4542695233 ps |
| CPU time | 11.51 seconds |
| Started | Sep 24 08:09:02 AM UTC 24 |
| Finished | Sep 24 08:09:14 AM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608175207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_same_csr_outstanding.3608175207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/2.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3278924715 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 4659348641 ps |
| CPU time | 7.29 seconds |
| Started | Sep 24 08:08:59 AM UTC 24 |
| Finished | Sep 24 08:09:07 AM UTC 24 |
| Peak memory | 211572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278924715 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_intg_err.3278924715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/2.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.1897756775 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 552394685 ps |
| CPU time | 1.61 seconds |
| Started | Sep 24 08:10:16 AM UTC 24 |
| Finished | Sep 24 08:10:19 AM UTC 24 |
| Peak memory | 210348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897756775 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.1897756775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/20.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.716360925 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 516991706 ps |
| CPU time | 1.09 seconds |
| Started | Sep 24 08:10:16 AM UTC 24 |
| Finished | Sep 24 08:10:18 AM UTC 24 |
| Peak memory | 210300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716360925 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.716360925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/21.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.4181088913 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 423866498 ps |
| CPU time | 2.07 seconds |
| Started | Sep 24 08:10:16 AM UTC 24 |
| Finished | Sep 24 08:10:19 AM UTC 24 |
| Peak memory | 211260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181088913 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.4181088913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/22.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.4088075477 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 350478195 ps |
| CPU time | 2.4 seconds |
| Started | Sep 24 08:10:17 AM UTC 24 |
| Finished | Sep 24 08:10:21 AM UTC 24 |
| Peak memory | 211128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088075477 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.4088075477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/23.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.1191987720 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 394097318 ps |
| CPU time | 2.54 seconds |
| Started | Sep 24 08:10:17 AM UTC 24 |
| Finished | Sep 24 08:10:21 AM UTC 24 |
| Peak memory | 211224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191987720 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.1191987720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/24.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.3998012516 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 456962047 ps |
| CPU time | 2.43 seconds |
| Started | Sep 24 08:10:18 AM UTC 24 |
| Finished | Sep 24 08:10:22 AM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998012516 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.3998012516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/25.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.4186508448 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 396598770 ps |
| CPU time | 1.3 seconds |
| Started | Sep 24 08:10:18 AM UTC 24 |
| Finished | Sep 24 08:10:21 AM UTC 24 |
| Peak memory | 210384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186508448 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.4186508448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/26.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.2238493502 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 364754675 ps |
| CPU time | 1.69 seconds |
| Started | Sep 24 08:10:19 AM UTC 24 |
| Finished | Sep 24 08:10:21 AM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238493502 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2238493502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/27.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.1491133455 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 523092892 ps |
| CPU time | 1.57 seconds |
| Started | Sep 24 08:10:20 AM UTC 24 |
| Finished | Sep 24 08:10:22 AM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491133455 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.1491133455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/28.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.79464739 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 422953128 ps |
| CPU time | 1.08 seconds |
| Started | Sep 24 08:10:20 AM UTC 24 |
| Finished | Sep 24 08:10:22 AM UTC 24 |
| Peak memory | 209848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79464739 -assert nopostproc +UVM_TESTNAME=adc_ctrl _base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.79464739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/29.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3789100495 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 810345553 ps |
| CPU time | 3.7 seconds |
| Started | Sep 24 08:09:11 AM UTC 24 |
| Finished | Sep 24 08:09:16 AM UTC 24 |
| Peak memory | 211160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789100495 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_aliasing.3789100495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/3.adc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1320297061 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 2205209244 ps |
| CPU time | 6.4 seconds |
| Started | Sep 24 08:09:11 AM UTC 24 |
| Finished | Sep 24 08:09:19 AM UTC 24 |
| Peak memory | 211184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320297061 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_bash.1320297061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/3.adc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2122071343 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 913887504 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 08:09:09 AM UTC 24 |
| Finished | Sep 24 08:09:12 AM UTC 24 |
| Peak memory | 210032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122071343 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_reset.2122071343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/3.adc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.4107624736 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 529618668 ps |
| CPU time | 1.99 seconds |
| Started | Sep 24 08:09:12 AM UTC 24 |
| Finished | Sep 24 08:09:16 AM UTC 24 |
| Peak memory | 209848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4107624736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_cs r_mem_rw_with_rand_reset.4107624736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.733369639 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 530723600 ps |
| CPU time | 3.34 seconds |
| Started | Sep 24 08:09:09 AM UTC 24 |
| Finished | Sep 24 08:09:14 AM UTC 24 |
| Peak memory | 211332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733369639 -assert nopostproc +UVM_TESTNAME=adc_ ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.733369639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/3.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.1305168053 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 469400551 ps |
| CPU time | 1.46 seconds |
| Started | Sep 24 08:09:08 AM UTC 24 |
| Finished | Sep 24 08:09:11 AM UTC 24 |
| Peak memory | 210384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305168053 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.1305168053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/3.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3963574670 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 4856973985 ps |
| CPU time | 20.98 seconds |
| Started | Sep 24 08:09:12 AM UTC 24 |
| Finished | Sep 24 08:09:35 AM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963574670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_same_csr_outstanding.3963574670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/3.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.653279469 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1000884353 ps |
| CPU time | 3.92 seconds |
| Started | Sep 24 08:09:06 AM UTC 24 |
| Finished | Sep 24 08:09:11 AM UTC 24 |
| Peak memory | 221308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653279469 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.653279469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/3.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1162043982 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 8225279603 ps |
| CPU time | 11.1 seconds |
| Started | Sep 24 08:09:06 AM UTC 24 |
| Finished | Sep 24 08:09:18 AM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162043982 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_intg_err.1162043982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/3.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/30.adc_ctrl_intr_test.516785888 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 466415639 ps |
| CPU time | 1.04 seconds |
| Started | Sep 24 08:10:20 AM UTC 24 |
| Finished | Sep 24 08:10:22 AM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516785888 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.516785888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/30.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/31.adc_ctrl_intr_test.1522431239 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 476411899 ps |
| CPU time | 1.48 seconds |
| Started | Sep 24 08:10:21 AM UTC 24 |
| Finished | Sep 24 08:10:24 AM UTC 24 |
| Peak memory | 209908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522431239 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1522431239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/31.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/32.adc_ctrl_intr_test.179803950 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 348078201 ps |
| CPU time | 1.18 seconds |
| Started | Sep 24 08:10:21 AM UTC 24 |
| Finished | Sep 24 08:10:23 AM UTC 24 |
| Peak memory | 210272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179803950 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.179803950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/32.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/33.adc_ctrl_intr_test.3642995100 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 381033981 ps |
| CPU time | 2.43 seconds |
| Started | Sep 24 08:10:22 AM UTC 24 |
| Finished | Sep 24 08:10:26 AM UTC 24 |
| Peak memory | 211088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642995100 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.3642995100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/33.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/34.adc_ctrl_intr_test.2537783590 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 401076209 ps |
| CPU time | 2.84 seconds |
| Started | Sep 24 08:10:22 AM UTC 24 |
| Finished | Sep 24 08:10:26 AM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537783590 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2537783590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/34.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/35.adc_ctrl_intr_test.273877399 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 326428123 ps |
| CPU time | 1.35 seconds |
| Started | Sep 24 08:10:22 AM UTC 24 |
| Finished | Sep 24 08:10:24 AM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273877399 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.273877399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/35.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/36.adc_ctrl_intr_test.3218453945 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 349258873 ps |
| CPU time | 1.21 seconds |
| Started | Sep 24 08:10:22 AM UTC 24 |
| Finished | Sep 24 08:10:25 AM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218453945 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3218453945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/36.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/37.adc_ctrl_intr_test.93393754 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 371353546 ps |
| CPU time | 1.31 seconds |
| Started | Sep 24 08:10:22 AM UTC 24 |
| Finished | Sep 24 08:10:25 AM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93393754 -assert nopostproc +UVM_TESTNAME=adc_ctrl _base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.93393754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/37.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/38.adc_ctrl_intr_test.3271623024 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 376324922 ps |
| CPU time | 1.83 seconds |
| Started | Sep 24 08:10:22 AM UTC 24 |
| Finished | Sep 24 08:10:25 AM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271623024 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3271623024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/38.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/39.adc_ctrl_intr_test.2980967790 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 530856506 ps |
| CPU time | 1.29 seconds |
| Started | Sep 24 08:10:23 AM UTC 24 |
| Finished | Sep 24 08:10:26 AM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980967790 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.2980967790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/39.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.429845291 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 417265551 ps |
| CPU time | 3.76 seconds |
| Started | Sep 24 08:09:19 AM UTC 24 |
| Finished | Sep 24 08:09:24 AM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429845291 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_aliasing.429845291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/4.adc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1738971812 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 20965485152 ps |
| CPU time | 19.57 seconds |
| Started | Sep 24 08:09:19 AM UTC 24 |
| Finished | Sep 24 08:09:40 AM UTC 24 |
| Peak memory | 211092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738971812 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_bash.1738971812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/4.adc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1395848953 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1185187477 ps |
| CPU time | 2.41 seconds |
| Started | Sep 24 08:09:17 AM UTC 24 |
| Finished | Sep 24 08:09:20 AM UTC 24 |
| Peak memory | 211200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395848953 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_reset.1395848953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/4.adc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.246569264 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 407910423 ps |
| CPU time | 3.27 seconds |
| Started | Sep 24 08:09:20 AM UTC 24 |
| Finished | Sep 24 08:09:24 AM UTC 24 |
| Peak memory | 211272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=246569264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr _mem_rw_with_rand_reset.246569264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_rw.543832296 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 545930572 ps |
| CPU time | 3.54 seconds |
| Started | Sep 24 08:09:17 AM UTC 24 |
| Finished | Sep 24 08:09:21 AM UTC 24 |
| Peak memory | 211272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543832296 -assert nopostproc +UVM_TESTNAME=adc_ ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.543832296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/4.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_intr_test.3189680868 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 280967687 ps |
| CPU time | 2.28 seconds |
| Started | Sep 24 08:09:16 AM UTC 24 |
| Finished | Sep 24 08:09:19 AM UTC 24 |
| Peak memory | 211092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189680868 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3189680868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/4.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.578870863 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 2802329359 ps |
| CPU time | 2.13 seconds |
| Started | Sep 24 08:09:20 AM UTC 24 |
| Finished | Sep 24 08:09:23 AM UTC 24 |
| Peak memory | 211196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578870863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_same_csr_outstanding.578870863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/4.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1406250644 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 374063074 ps |
| CPU time | 3.56 seconds |
| Started | Sep 24 08:09:14 AM UTC 24 |
| Finished | Sep 24 08:09:18 AM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406250644 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.1406250644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/4.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2289107751 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 3851487924 ps |
| CPU time | 16.4 seconds |
| Started | Sep 24 08:09:15 AM UTC 24 |
| Finished | Sep 24 08:09:32 AM UTC 24 |
| Peak memory | 211672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289107751 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_intg_err.2289107751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/4.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/40.adc_ctrl_intr_test.1314605768 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 407130627 ps |
| CPU time | 1.04 seconds |
| Started | Sep 24 08:10:23 AM UTC 24 |
| Finished | Sep 24 08:10:25 AM UTC 24 |
| Peak memory | 209848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314605768 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1314605768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/40.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/41.adc_ctrl_intr_test.2900622714 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 359151310 ps |
| CPU time | 2.42 seconds |
| Started | Sep 24 08:10:23 AM UTC 24 |
| Finished | Sep 24 08:10:27 AM UTC 24 |
| Peak memory | 211264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900622714 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.2900622714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/41.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/42.adc_ctrl_intr_test.1189762905 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 469387035 ps |
| CPU time | 1.5 seconds |
| Started | Sep 24 08:10:23 AM UTC 24 |
| Finished | Sep 24 08:10:26 AM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189762905 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1189762905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/42.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/43.adc_ctrl_intr_test.387203246 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 316289019 ps |
| CPU time | 2.14 seconds |
| Started | Sep 24 08:10:23 AM UTC 24 |
| Finished | Sep 24 08:10:27 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387203246 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.387203246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/43.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/44.adc_ctrl_intr_test.889882348 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 400311636 ps |
| CPU time | 2.63 seconds |
| Started | Sep 24 08:10:23 AM UTC 24 |
| Finished | Sep 24 08:10:28 AM UTC 24 |
| Peak memory | 211224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889882348 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.889882348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/44.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/45.adc_ctrl_intr_test.1343894579 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 361133766 ps |
| CPU time | 2.71 seconds |
| Started | Sep 24 08:10:24 AM UTC 24 |
| Finished | Sep 24 08:10:28 AM UTC 24 |
| Peak memory | 210452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343894579 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.1343894579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/45.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/46.adc_ctrl_intr_test.664732690 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 502909351 ps |
| CPU time | 2.52 seconds |
| Started | Sep 24 08:10:25 AM UTC 24 |
| Finished | Sep 24 08:10:28 AM UTC 24 |
| Peak memory | 211168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664732690 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.664732690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/46.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/47.adc_ctrl_intr_test.2343088154 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 438140286 ps |
| CPU time | 1.13 seconds |
| Started | Sep 24 08:10:25 AM UTC 24 |
| Finished | Sep 24 08:10:27 AM UTC 24 |
| Peak memory | 209556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343088154 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.2343088154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/47.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/48.adc_ctrl_intr_test.995723274 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 413651912 ps |
| CPU time | 2.77 seconds |
| Started | Sep 24 08:10:25 AM UTC 24 |
| Finished | Sep 24 08:10:29 AM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995723274 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.995723274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/48.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/49.adc_ctrl_intr_test.3782903756 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 430978583 ps |
| CPU time | 3 seconds |
| Started | Sep 24 08:10:26 AM UTC 24 |
| Finished | Sep 24 08:10:30 AM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782903756 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.3782903756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/49.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2479847916 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 376846537 ps |
| CPU time | 2.09 seconds |
| Started | Sep 24 08:09:25 AM UTC 24 |
| Finished | Sep 24 08:09:28 AM UTC 24 |
| Peak memory | 211260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2479847916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_cs r_mem_rw_with_rand_reset.2479847916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1216877549 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 619559830 ps |
| CPU time | 1.74 seconds |
| Started | Sep 24 08:09:24 AM UTC 24 |
| Finished | Sep 24 08:09:27 AM UTC 24 |
| Peak memory | 210032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216877549 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.1216877549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/5.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_intr_test.1741052106 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 308033369 ps |
| CPU time | 2.36 seconds |
| Started | Sep 24 08:09:24 AM UTC 24 |
| Finished | Sep 24 08:09:28 AM UTC 24 |
| Peak memory | 211088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741052106 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.1741052106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/5.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2287060698 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 2975625675 ps |
| CPU time | 12.61 seconds |
| Started | Sep 24 08:09:25 AM UTC 24 |
| Finished | Sep 24 08:09:39 AM UTC 24 |
| Peak memory | 211452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287060698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_same_csr_outstanding.2287060698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/5.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1426525864 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 349632335 ps |
| CPU time | 3.49 seconds |
| Started | Sep 24 08:09:21 AM UTC 24 |
| Finished | Sep 24 08:09:26 AM UTC 24 |
| Peak memory | 211384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426525864 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.1426525864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/5.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2102457222 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 9019436450 ps |
| CPU time | 24.35 seconds |
| Started | Sep 24 08:09:22 AM UTC 24 |
| Finished | Sep 24 08:09:48 AM UTC 24 |
| Peak memory | 211540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102457222 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_intg_err.2102457222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/5.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1629638978 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 544898018 ps |
| CPU time | 1.91 seconds |
| Started | Sep 24 08:09:31 AM UTC 24 |
| Finished | Sep 24 08:09:34 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1629638978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_cs r_mem_rw_with_rand_reset.1629638978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1582699801 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 463143089 ps |
| CPU time | 1.54 seconds |
| Started | Sep 24 08:09:29 AM UTC 24 |
| Finished | Sep 24 08:09:31 AM UTC 24 |
| Peak memory | 210032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582699801 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.1582699801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/6.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_intr_test.3055202980 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 564336072 ps |
| CPU time | 1.63 seconds |
| Started | Sep 24 08:09:27 AM UTC 24 |
| Finished | Sep 24 08:09:30 AM UTC 24 |
| Peak memory | 209908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055202980 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.3055202980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/6.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2926960799 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 2626730044 ps |
| CPU time | 5.79 seconds |
| Started | Sep 24 08:09:30 AM UTC 24 |
| Finished | Sep 24 08:09:37 AM UTC 24 |
| Peak memory | 211268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926960799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_same_csr_outstanding.2926960799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/6.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2464426615 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 501152887 ps |
| CPU time | 5.34 seconds |
| Started | Sep 24 08:09:26 AM UTC 24 |
| Finished | Sep 24 08:09:33 AM UTC 24 |
| Peak memory | 221276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464426615 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.2464426615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/6.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2191441273 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 8866985166 ps |
| CPU time | 10.34 seconds |
| Started | Sep 24 08:09:26 AM UTC 24 |
| Finished | Sep 24 08:09:38 AM UTC 24 |
| Peak memory | 211484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191441273 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_intg_err.2191441273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/6.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3023861221 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 518665029 ps |
| CPU time | 1.93 seconds |
| Started | Sep 24 08:09:35 AM UTC 24 |
| Finished | Sep 24 08:09:38 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3023861221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_cs r_mem_rw_with_rand_reset.3023861221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_rw.947118502 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 425404788 ps |
| CPU time | 1.51 seconds |
| Started | Sep 24 08:09:33 AM UTC 24 |
| Finished | Sep 24 08:09:35 AM UTC 24 |
| Peak memory | 210032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947118502 -assert nopostproc +UVM_TESTNAME=adc_ ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.947118502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/7.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_intr_test.1719389129 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 595103487 ps |
| CPU time | 1.11 seconds |
| Started | Sep 24 08:09:33 AM UTC 24 |
| Finished | Sep 24 08:09:35 AM UTC 24 |
| Peak memory | 209908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719389129 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1719389129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/7.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3595928517 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 2298710734 ps |
| CPU time | 7.72 seconds |
| Started | Sep 24 08:09:34 AM UTC 24 |
| Finished | Sep 24 08:09:43 AM UTC 24 |
| Peak memory | 211268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595928517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_same_csr_outstanding.3595928517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/7.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3460147236 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 710373533 ps |
| CPU time | 3.12 seconds |
| Started | Sep 24 08:09:31 AM UTC 24 |
| Finished | Sep 24 08:09:35 AM UTC 24 |
| Peak memory | 221572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460147236 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.3460147236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/7.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.4148490328 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 423319152 ps |
| CPU time | 2.12 seconds |
| Started | Sep 24 08:09:38 AM UTC 24 |
| Finished | Sep 24 08:09:41 AM UTC 24 |
| Peak memory | 211268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4148490328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_cs r_mem_rw_with_rand_reset.4148490328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1520458435 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 503257062 ps |
| CPU time | 2.25 seconds |
| Started | Sep 24 08:09:36 AM UTC 24 |
| Finished | Sep 24 08:09:40 AM UTC 24 |
| Peak memory | 211128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520458435 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.1520458435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/8.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_intr_test.3961994181 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 430455656 ps |
| CPU time | 1.8 seconds |
| Started | Sep 24 08:09:36 AM UTC 24 |
| Finished | Sep 24 08:09:39 AM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961994181 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.3961994181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/8.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.384925398 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 2376472126 ps |
| CPU time | 1.86 seconds |
| Started | Sep 24 08:09:37 AM UTC 24 |
| Finished | Sep 24 08:09:40 AM UTC 24 |
| Peak memory | 210272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384925398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_same_csr_outstanding.384925398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/8.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2844614420 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 353086148 ps |
| CPU time | 3.82 seconds |
| Started | Sep 24 08:09:36 AM UTC 24 |
| Finished | Sep 24 08:09:41 AM UTC 24 |
| Peak memory | 227624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844614420 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2844614420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/8.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1239969066 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 8432466145 ps |
| CPU time | 12.28 seconds |
| Started | Sep 24 08:09:36 AM UTC 24 |
| Finished | Sep 24 08:09:50 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239969066 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_intg_err.1239969066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/8.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1767640697 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 435514778 ps |
| CPU time | 1.96 seconds |
| Started | Sep 24 08:09:41 AM UTC 24 |
| Finished | Sep 24 08:09:44 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1767640697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_cs r_mem_rw_with_rand_reset.1767640697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1573810320 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 330731519 ps |
| CPU time | 2.55 seconds |
| Started | Sep 24 08:09:41 AM UTC 24 |
| Finished | Sep 24 08:09:44 AM UTC 24 |
| Peak memory | 211264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573810320 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.1573810320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/9.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_intr_test.2505609879 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 374234255 ps |
| CPU time | 1.32 seconds |
| Started | Sep 24 08:09:39 AM UTC 24 |
| Finished | Sep 24 08:09:42 AM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505609879 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.2505609879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/9.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2584901531 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 4831851078 ps |
| CPU time | 27.15 seconds |
| Started | Sep 24 08:09:41 AM UTC 24 |
| Finished | Sep 24 08:10:09 AM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584901531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_same_csr_outstanding.2584901531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/9.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2881021645 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 445635908 ps |
| CPU time | 3.26 seconds |
| Started | Sep 24 08:09:39 AM UTC 24 |
| Finished | Sep 24 08:09:44 AM UTC 24 |
| Peak memory | 221444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881021645 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2881021645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/9.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3296814705 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 4500980515 ps |
| CPU time | 23.99 seconds |
| Started | Sep 24 08:09:39 AM UTC 24 |
| Finished | Sep 24 08:10:05 AM UTC 24 |
| Peak memory | 211480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296814705 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_intg_err.3296814705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/9.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt.3949566679 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 321611579129 ps |
| CPU time | 498.8 seconds |
| Started | Sep 24 06:57:45 AM UTC 24 |
| Finished | Sep 24 07:06:09 AM UTC 24 |
| Peak memory | 213448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949566679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3949566679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/0.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2196155041 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 493544022534 ps |
| CPU time | 1245.17 seconds |
| Started | Sep 24 06:57:46 AM UTC 24 |
| Finished | Sep 24 07:18:43 AM UTC 24 |
| Peak memory | 213436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196155041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt_fixed.2196155041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/0.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled.3630938404 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 171747960386 ps |
| CPU time | 132.92 seconds |
| Started | Sep 24 06:57:44 AM UTC 24 |
| Finished | Sep 24 06:59:59 AM UTC 24 |
| Peak memory | 210852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630938404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.3630938404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/0.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled_fixed.865262129 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 497140768802 ps |
| CPU time | 1563.62 seconds |
| Started | Sep 24 06:57:45 AM UTC 24 |
| Finished | Sep 24 07:24:04 AM UTC 24 |
| Peak memory | 213424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865262129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixed.865262129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/0.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup.1368749766 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 165155652095 ps |
| CPU time | 213.04 seconds |
| Started | Sep 24 06:57:48 AM UTC 24 |
| Finished | Sep 24 07:01:24 AM UTC 24 |
| Peak memory | 211032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368749766 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_wakeup.1368749766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/0.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup_fixed.4141728996 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 625560596558 ps |
| CPU time | 1946.6 seconds |
| Started | Sep 24 06:57:52 AM UTC 24 |
| Finished | Sep 24 07:30:38 AM UTC 24 |
| Peak memory | 213516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141728996 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_wakeup_fixed.4141728996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/0.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_fsm_reset.4182137445 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 70699077006 ps |
| CPU time | 305.86 seconds |
| Started | Sep 24 06:57:59 AM UTC 24 |
| Finished | Sep 24 07:03:08 AM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182137445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.4182137445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/0.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_lowpower_counter.1913894942 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 28294947944 ps |
| CPU time | 25.92 seconds |
| Started | Sep 24 06:57:58 AM UTC 24 |
| Finished | Sep 24 06:58:26 AM UTC 24 |
| Peak memory | 210760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913894942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.1913894942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/0.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_poweron_counter.4100883883 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5603799702 ps |
| CPU time | 27.56 seconds |
| Started | Sep 24 06:57:55 AM UTC 24 |
| Finished | Sep 24 06:58:24 AM UTC 24 |
| Peak memory | 210544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100883883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.4100883883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/0.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.984603109 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 7711323727 ps |
| CPU time | 15.28 seconds |
| Started | Sep 24 06:58:01 AM UTC 24 |
| Finished | Sep 24 06:58:17 AM UTC 24 |
| Peak memory | 242836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984603109 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.984603109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/0.adc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all.2704176829 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 172235011892 ps |
| CPU time | 155.59 seconds |
| Started | Sep 24 06:58:01 AM UTC 24 |
| Finished | Sep 24 07:00:39 AM UTC 24 |
| Peak memory | 210748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704176829 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.2704176829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_alert_test.3557571678 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 464716552 ps |
| CPU time | 3.73 seconds |
| Started | Sep 24 06:58:22 AM UTC 24 |
| Finished | Sep 24 06:58:27 AM UTC 24 |
| Peak memory | 210364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557571678 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.3557571678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/1.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_both.458793816 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 561395086331 ps |
| CPU time | 1456.21 seconds |
| Started | Sep 24 06:58:10 AM UTC 24 |
| Finished | Sep 24 07:22:41 AM UTC 24 |
| Peak memory | 213368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458793816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.458793816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/1.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled.638829618 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 330829619400 ps |
| CPU time | 262.62 seconds |
| Started | Sep 24 06:58:03 AM UTC 24 |
| Finished | Sep 24 07:02:29 AM UTC 24 |
| Peak memory | 210720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638829618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.638829618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/1.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled_fixed.1272740074 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 326385484356 ps |
| CPU time | 228.11 seconds |
| Started | Sep 24 06:58:03 AM UTC 24 |
| Finished | Sep 24 07:01:55 AM UTC 24 |
| Peak memory | 210708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272740074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixed.1272740074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/1.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup_fixed.394448879 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 598135435464 ps |
| CPU time | 1400.86 seconds |
| Started | Sep 24 06:58:05 AM UTC 24 |
| Finished | Sep 24 07:21:41 AM UTC 24 |
| Peak memory | 213616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394448879 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_wakeup_fixed.394448879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/1.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_fsm_reset.297856788 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 94438116454 ps |
| CPU time | 641.68 seconds |
| Started | Sep 24 06:58:15 AM UTC 24 |
| Finished | Sep 24 07:09:03 AM UTC 24 |
| Peak memory | 213780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297856788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.297856788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/1.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_lowpower_counter.1483030626 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 35615135624 ps |
| CPU time | 28.04 seconds |
| Started | Sep 24 06:58:14 AM UTC 24 |
| Finished | Sep 24 06:58:43 AM UTC 24 |
| Peak memory | 210496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483030626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.1483030626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/1.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_poweron_counter.1709234816 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3625129143 ps |
| CPU time | 11.39 seconds |
| Started | Sep 24 06:58:12 AM UTC 24 |
| Finished | Sep 24 06:58:24 AM UTC 24 |
| Peak memory | 210492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709234816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1709234816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/1.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_sec_cm.3120812907 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 4391709566 ps |
| CPU time | 17.73 seconds |
| Started | Sep 24 06:58:19 AM UTC 24 |
| Finished | Sep 24 06:58:38 AM UTC 24 |
| Peak memory | 243040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120812907 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.3120812907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/1.adc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_smoke.283090143 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 6078939877 ps |
| CPU time | 7.32 seconds |
| Started | Sep 24 06:58:02 AM UTC 24 |
| Finished | Sep 24 06:58:10 AM UTC 24 |
| Peak memory | 210572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283090143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.283090143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/1.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_alert_test.2609822827 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 547674933 ps |
| CPU time | 1.41 seconds |
| Started | Sep 24 07:07:45 AM UTC 24 |
| Finished | Sep 24 07:07:48 AM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609822827 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.2609822827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/10.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_both.837178300 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 165763002172 ps |
| CPU time | 422.72 seconds |
| Started | Sep 24 07:07:19 AM UTC 24 |
| Finished | Sep 24 07:14:26 AM UTC 24 |
| Peak memory | 210856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837178300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.837178300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/10.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt.1418644390 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 162670300062 ps |
| CPU time | 456.03 seconds |
| Started | Sep 24 07:06:22 AM UTC 24 |
| Finished | Sep 24 07:14:03 AM UTC 24 |
| Peak memory | 210720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418644390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1418644390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/10.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt_fixed.4270415447 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 165562536646 ps |
| CPU time | 132.26 seconds |
| Started | Sep 24 07:06:23 AM UTC 24 |
| Finished | Sep 24 07:08:37 AM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270415447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt_fixed.4270415447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/10.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled.2991863380 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 162771454325 ps |
| CPU time | 123.73 seconds |
| Started | Sep 24 07:06:20 AM UTC 24 |
| Finished | Sep 24 07:08:25 AM UTC 24 |
| Peak memory | 210772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991863380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2991863380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/10.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled_fixed.3671574615 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 163994716155 ps |
| CPU time | 265.66 seconds |
| Started | Sep 24 07:06:20 AM UTC 24 |
| Finished | Sep 24 07:10:49 AM UTC 24 |
| Peak memory | 210768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671574615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixed.3671574615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/10.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.2033742958 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 165442614639 ps |
| CPU time | 299.68 seconds |
| Started | Sep 24 07:06:26 AM UTC 24 |
| Finished | Sep 24 07:11:29 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033742958 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_wakeup.2033742958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/10.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1273091980 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 197352266315 ps |
| CPU time | 634.87 seconds |
| Started | Sep 24 07:06:27 AM UTC 24 |
| Finished | Sep 24 07:17:09 AM UTC 24 |
| Peak memory | 210696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273091980 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_wakeup_fixed.1273091980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/10.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_lowpower_counter.902080841 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 44679991144 ps |
| CPU time | 19.06 seconds |
| Started | Sep 24 07:07:31 AM UTC 24 |
| Finished | Sep 24 07:07:51 AM UTC 24 |
| Peak memory | 210764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902080841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.902080841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/10.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_poweron_counter.2186195891 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 2861026897 ps |
| CPU time | 1.92 seconds |
| Started | Sep 24 07:07:27 AM UTC 24 |
| Finished | Sep 24 07:07:30 AM UTC 24 |
| Peak memory | 210568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186195891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.2186195891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/10.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_smoke.1598372012 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 6018863348 ps |
| CPU time | 8.51 seconds |
| Started | Sep 24 07:06:17 AM UTC 24 |
| Finished | Sep 24 07:06:26 AM UTC 24 |
| Peak memory | 210512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598372012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.1598372012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/10.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_alert_test.4183023772 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 471106291 ps |
| CPU time | 1.38 seconds |
| Started | Sep 24 07:09:03 AM UTC 24 |
| Finished | Sep 24 07:09:06 AM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183023772 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.4183023772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/11.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt.134700913 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 489858454840 ps |
| CPU time | 1224.25 seconds |
| Started | Sep 24 07:07:52 AM UTC 24 |
| Finished | Sep 24 07:28:29 AM UTC 24 |
| Peak memory | 213508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134700913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.134700913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/11.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2849136727 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 165042681782 ps |
| CPU time | 289.16 seconds |
| Started | Sep 24 07:07:52 AM UTC 24 |
| Finished | Sep 24 07:12:45 AM UTC 24 |
| Peak memory | 210792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849136727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt_fixed.2849136727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/11.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled.1431543033 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 335129830446 ps |
| CPU time | 326.66 seconds |
| Started | Sep 24 07:07:49 AM UTC 24 |
| Finished | Sep 24 07:13:20 AM UTC 24 |
| Peak memory | 210536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431543033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.1431543033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/11.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled_fixed.4244619340 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 170605046468 ps |
| CPU time | 546.08 seconds |
| Started | Sep 24 07:07:51 AM UTC 24 |
| Finished | Sep 24 07:17:04 AM UTC 24 |
| Peak memory | 210760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244619340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixed.4244619340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/11.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1956696791 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 606046333187 ps |
| CPU time | 784.87 seconds |
| Started | Sep 24 07:08:16 AM UTC 24 |
| Finished | Sep 24 07:21:29 AM UTC 24 |
| Peak memory | 211064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956696791 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_wakeup_fixed.1956696791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/11.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_fsm_reset.2432525763 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 130010252785 ps |
| CPU time | 716.48 seconds |
| Started | Sep 24 07:08:38 AM UTC 24 |
| Finished | Sep 24 07:20:42 AM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432525763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.2432525763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/11.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_lowpower_counter.2788222716 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 34655364491 ps |
| CPU time | 124.16 seconds |
| Started | Sep 24 07:08:32 AM UTC 24 |
| Finished | Sep 24 07:10:38 AM UTC 24 |
| Peak memory | 210764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788222716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.2788222716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/11.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_poweron_counter.208717507 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 3404087765 ps |
| CPU time | 4.1 seconds |
| Started | Sep 24 07:08:26 AM UTC 24 |
| Finished | Sep 24 07:08:31 AM UTC 24 |
| Peak memory | 210576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208717507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.208717507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/11.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_smoke.65044768 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 5681227263 ps |
| CPU time | 14.5 seconds |
| Started | Sep 24 07:07:49 AM UTC 24 |
| Finished | Sep 24 07:08:05 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65044768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_ SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.65044768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/11.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2494054050 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 10371130387 ps |
| CPU time | 15.67 seconds |
| Started | Sep 24 07:08:43 AM UTC 24 |
| Finished | Sep 24 07:09:00 AM UTC 24 |
| Peak memory | 221068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2494054050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 11.adc_ctrl_stress_all_with_rand_reset.2494054050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/11.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_alert_test.4082124287 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 442790277 ps |
| CPU time | 1.84 seconds |
| Started | Sep 24 07:10:39 AM UTC 24 |
| Finished | Sep 24 07:10:42 AM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082124287 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.4082124287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/12.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_both.3639185649 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 374126978967 ps |
| CPU time | 271.38 seconds |
| Started | Sep 24 07:10:03 AM UTC 24 |
| Finished | Sep 24 07:14:38 AM UTC 24 |
| Peak memory | 210720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639185649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3639185649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/12.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt.2740880463 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 489111041672 ps |
| CPU time | 481.38 seconds |
| Started | Sep 24 07:09:35 AM UTC 24 |
| Finished | Sep 24 07:17:42 AM UTC 24 |
| Peak memory | 210780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740880463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.2740880463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/12.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1262383572 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 334607605248 ps |
| CPU time | 336.13 seconds |
| Started | Sep 24 07:09:44 AM UTC 24 |
| Finished | Sep 24 07:15:24 AM UTC 24 |
| Peak memory | 210688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262383572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt_fixed.1262383572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/12.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled_fixed.3257623358 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 491568311749 ps |
| CPU time | 1459.1 seconds |
| Started | Sep 24 07:09:26 AM UTC 24 |
| Finished | Sep 24 07:34:00 AM UTC 24 |
| Peak memory | 213492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257623358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fixed.3257623358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/12.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup.3870820881 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 381870970592 ps |
| CPU time | 345.83 seconds |
| Started | Sep 24 07:09:45 AM UTC 24 |
| Finished | Sep 24 07:15:35 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870820881 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_wakeup.3870820881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/12.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_fsm_reset.2599975845 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 99026201522 ps |
| CPU time | 511.7 seconds |
| Started | Sep 24 07:10:16 AM UTC 24 |
| Finished | Sep 24 07:18:54 AM UTC 24 |
| Peak memory | 211060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599975845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.2599975845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/12.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_lowpower_counter.76801041 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 26393194320 ps |
| CPU time | 54.47 seconds |
| Started | Sep 24 07:10:05 AM UTC 24 |
| Finished | Sep 24 07:11:01 AM UTC 24 |
| Peak memory | 210564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76801041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_ SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.76801041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/12.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_poweron_counter.3450507308 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 4608015324 ps |
| CPU time | 18.52 seconds |
| Started | Sep 24 07:10:04 AM UTC 24 |
| Finished | Sep 24 07:10:24 AM UTC 24 |
| Peak memory | 210488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450507308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3450507308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/12.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_smoke.1743732947 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 5871462491 ps |
| CPU time | 26.56 seconds |
| Started | Sep 24 07:09:06 AM UTC 24 |
| Finished | Sep 24 07:09:34 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743732947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.1743732947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/12.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_alert_test.211797979 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 539397277 ps |
| CPU time | 1.16 seconds |
| Started | Sep 24 07:12:21 AM UTC 24 |
| Finished | Sep 24 07:12:24 AM UTC 24 |
| Peak memory | 210444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211797979 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.211797979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/13.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2119830407 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 163744342440 ps |
| CPU time | 407.63 seconds |
| Started | Sep 24 07:11:02 AM UTC 24 |
| Finished | Sep 24 07:17:54 AM UTC 24 |
| Peak memory | 210768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119830407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt_fixed.2119830407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/13.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled.1228797060 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 486957550798 ps |
| CPU time | 1632.12 seconds |
| Started | Sep 24 07:10:49 AM UTC 24 |
| Finished | Sep 24 07:38:18 AM UTC 24 |
| Peak memory | 213424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228797060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1228797060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/13.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled_fixed.1451772980 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 324422627048 ps |
| CPU time | 775.19 seconds |
| Started | Sep 24 07:11:01 AM UTC 24 |
| Finished | Sep 24 07:24:04 AM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451772980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixed.1451772980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/13.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup_fixed.589341117 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 395209092344 ps |
| CPU time | 811.58 seconds |
| Started | Sep 24 07:11:30 AM UTC 24 |
| Finished | Sep 24 07:25:10 AM UTC 24 |
| Peak memory | 213416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589341117 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_wakeup_fixed.589341117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/13.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_fsm_reset.2492808600 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 130664803245 ps |
| CPU time | 446.56 seconds |
| Started | Sep 24 07:11:50 AM UTC 24 |
| Finished | Sep 24 07:19:22 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492808600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2492808600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/13.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_lowpower_counter.1811092660 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 26567677189 ps |
| CPU time | 59.33 seconds |
| Started | Sep 24 07:11:49 AM UTC 24 |
| Finished | Sep 24 07:12:50 AM UTC 24 |
| Peak memory | 210828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811092660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.1811092660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/13.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_poweron_counter.4044263415 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 4724541588 ps |
| CPU time | 11.57 seconds |
| Started | Sep 24 07:11:41 AM UTC 24 |
| Finished | Sep 24 07:11:54 AM UTC 24 |
| Peak memory | 210760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044263415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.4044263415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/13.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_smoke.943566023 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 5741827188 ps |
| CPU time | 14.56 seconds |
| Started | Sep 24 07:10:43 AM UTC 24 |
| Finished | Sep 24 07:10:59 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943566023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.943566023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/13.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all.3466522576 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 441985569538 ps |
| CPU time | 1243.9 seconds |
| Started | Sep 24 07:12:20 AM UTC 24 |
| Finished | Sep 24 07:33:17 AM UTC 24 |
| Peak memory | 213900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466522576 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.3466522576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/13.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.2941093457 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 10572610809 ps |
| CPU time | 41.93 seconds |
| Started | Sep 24 07:11:54 AM UTC 24 |
| Finished | Sep 24 07:12:38 AM UTC 24 |
| Peak memory | 221488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2941093457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 13.adc_ctrl_stress_all_with_rand_reset.2941093457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/13.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_alert_test.365968356 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 543305707 ps |
| CPU time | 1.45 seconds |
| Started | Sep 24 07:13:22 AM UTC 24 |
| Finished | Sep 24 07:13:25 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365968356 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.365968356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/14.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_clock_gating.2438424556 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 537261314493 ps |
| CPU time | 1661.76 seconds |
| Started | Sep 24 07:12:52 AM UTC 24 |
| Finished | Sep 24 07:40:51 AM UTC 24 |
| Peak memory | 213436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438424556 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gating.2438424556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/14.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_both.2979479784 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 197848408620 ps |
| CPU time | 194.27 seconds |
| Started | Sep 24 07:12:59 AM UTC 24 |
| Finished | Sep 24 07:16:16 AM UTC 24 |
| Peak memory | 210800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979479784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.2979479784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/14.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt_fixed.876778383 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 328524845538 ps |
| CPU time | 399.24 seconds |
| Started | Sep 24 07:12:41 AM UTC 24 |
| Finished | Sep 24 07:19:25 AM UTC 24 |
| Peak memory | 211036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876778383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt_fixed.876778383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/14.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled.857360782 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 497116812420 ps |
| CPU time | 592.19 seconds |
| Started | Sep 24 07:12:24 AM UTC 24 |
| Finished | Sep 24 07:22:23 AM UTC 24 |
| Peak memory | 210784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857360782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.857360782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/14.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled_fixed.2531601476 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 164983097376 ps |
| CPU time | 447.56 seconds |
| Started | Sep 24 07:12:36 AM UTC 24 |
| Finished | Sep 24 07:20:09 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531601476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixed.2531601476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/14.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup.978565337 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 651013908034 ps |
| CPU time | 936.48 seconds |
| Started | Sep 24 07:12:46 AM UTC 24 |
| Finished | Sep 24 07:28:32 AM UTC 24 |
| Peak memory | 213364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978565337 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_wakeup.978565337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/14.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup_fixed.2210606845 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 403568269566 ps |
| CPU time | 1078.21 seconds |
| Started | Sep 24 07:12:51 AM UTC 24 |
| Finished | Sep 24 07:31:00 AM UTC 24 |
| Peak memory | 213484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210606845 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_wakeup_fixed.2210606845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/14.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_fsm_reset.985459109 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 92371150599 ps |
| CPU time | 352.95 seconds |
| Started | Sep 24 07:13:14 AM UTC 24 |
| Finished | Sep 24 07:19:11 AM UTC 24 |
| Peak memory | 211124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985459109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.985459109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/14.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_lowpower_counter.4075758443 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 26527671834 ps |
| CPU time | 6.94 seconds |
| Started | Sep 24 07:13:05 AM UTC 24 |
| Finished | Sep 24 07:13:13 AM UTC 24 |
| Peak memory | 210764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075758443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.4075758443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/14.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_poweron_counter.1876289842 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 3248797515 ps |
| CPU time | 10.22 seconds |
| Started | Sep 24 07:13:05 AM UTC 24 |
| Finished | Sep 24 07:13:16 AM UTC 24 |
| Peak memory | 210760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876289842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.1876289842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/14.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_smoke.2615234750 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 6041986172 ps |
| CPU time | 14.11 seconds |
| Started | Sep 24 07:12:24 AM UTC 24 |
| Finished | Sep 24 07:12:40 AM UTC 24 |
| Peak memory | 210576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615234750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2615234750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/14.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3701915106 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 5178640173 ps |
| CPU time | 12.65 seconds |
| Started | Sep 24 07:13:17 AM UTC 24 |
| Finished | Sep 24 07:13:31 AM UTC 24 |
| Peak memory | 210628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3701915106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 14.adc_ctrl_stress_all_with_rand_reset.3701915106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/14.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_alert_test.274661532 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 469766601 ps |
| CPU time | 1.34 seconds |
| Started | Sep 24 07:15:42 AM UTC 24 |
| Finished | Sep 24 07:15:44 AM UTC 24 |
| Peak memory | 210444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274661532 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.274661532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/15.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_both.4040812396 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 343142175178 ps |
| CPU time | 532.81 seconds |
| Started | Sep 24 07:14:37 AM UTC 24 |
| Finished | Sep 24 07:23:36 AM UTC 24 |
| Peak memory | 210792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040812396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.4040812396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/15.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2059532482 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 162148947958 ps |
| CPU time | 389.6 seconds |
| Started | Sep 24 07:13:53 AM UTC 24 |
| Finished | Sep 24 07:20:27 AM UTC 24 |
| Peak memory | 210768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059532482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt_fixed.2059532482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/15.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled.368966164 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 490665048622 ps |
| CPU time | 406.66 seconds |
| Started | Sep 24 07:13:31 AM UTC 24 |
| Finished | Sep 24 07:20:23 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368966164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.368966164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/15.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled_fixed.3331277115 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 163175770277 ps |
| CPU time | 114.48 seconds |
| Started | Sep 24 07:13:35 AM UTC 24 |
| Finished | Sep 24 07:15:31 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331277115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixed.3331277115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/15.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup_fixed.75629823 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 197988754920 ps |
| CPU time | 211.41 seconds |
| Started | Sep 24 07:14:13 AM UTC 24 |
| Finished | Sep 24 07:17:47 AM UTC 24 |
| Peak memory | 210812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75629823 -assert nopostpro c +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_wakeup_fixed.75629823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/15.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_fsm_reset.2867775103 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 75512936419 ps |
| CPU time | 433.9 seconds |
| Started | Sep 24 07:15:25 AM UTC 24 |
| Finished | Sep 24 07:22:45 AM UTC 24 |
| Peak memory | 211128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867775103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.2867775103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/15.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_lowpower_counter.957291240 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 46117619537 ps |
| CPU time | 60.58 seconds |
| Started | Sep 24 07:14:58 AM UTC 24 |
| Finished | Sep 24 07:16:00 AM UTC 24 |
| Peak memory | 210572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957291240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.957291240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/15.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_poweron_counter.2667286314 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 3721925381 ps |
| CPU time | 17.57 seconds |
| Started | Sep 24 07:14:39 AM UTC 24 |
| Finished | Sep 24 07:14:58 AM UTC 24 |
| Peak memory | 210488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667286314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.2667286314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/15.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_smoke.1718711003 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 5962481882 ps |
| CPU time | 13.84 seconds |
| Started | Sep 24 07:13:25 AM UTC 24 |
| Finished | Sep 24 07:13:40 AM UTC 24 |
| Peak memory | 210576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718711003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.1718711003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/15.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all.3090771319 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 187487560262 ps |
| CPU time | 185.11 seconds |
| Started | Sep 24 07:15:35 AM UTC 24 |
| Finished | Sep 24 07:18:43 AM UTC 24 |
| Peak memory | 210784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090771319 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.3090771319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_alert_test.2127815119 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 426788984 ps |
| CPU time | 1.67 seconds |
| Started | Sep 24 07:18:38 AM UTC 24 |
| Finished | Sep 24 07:18:41 AM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127815119 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.2127815119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/16.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_both.171723750 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 488385354152 ps |
| CPU time | 1465.57 seconds |
| Started | Sep 24 07:17:42 AM UTC 24 |
| Finished | Sep 24 07:42:24 AM UTC 24 |
| Peak memory | 213504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171723750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.171723750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/16.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt.2029289102 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 166217518881 ps |
| CPU time | 551.75 seconds |
| Started | Sep 24 07:16:15 AM UTC 24 |
| Finished | Sep 24 07:25:33 AM UTC 24 |
| Peak memory | 210656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029289102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.2029289102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/16.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt_fixed.3176855031 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 165701539934 ps |
| CPU time | 484.83 seconds |
| Started | Sep 24 07:16:17 AM UTC 24 |
| Finished | Sep 24 07:24:28 AM UTC 24 |
| Peak memory | 211020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176855031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt_fixed.3176855031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/16.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled.1735233137 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 325483111081 ps |
| CPU time | 293.47 seconds |
| Started | Sep 24 07:15:59 AM UTC 24 |
| Finished | Sep 24 07:20:56 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735233137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.1735233137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/16.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled_fixed.4168782405 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 166253059675 ps |
| CPU time | 47.56 seconds |
| Started | Sep 24 07:16:01 AM UTC 24 |
| Finished | Sep 24 07:16:50 AM UTC 24 |
| Peak memory | 210672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168782405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixed.4168782405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/16.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup.1429132523 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 250137461596 ps |
| CPU time | 681.58 seconds |
| Started | Sep 24 07:16:51 AM UTC 24 |
| Finished | Sep 24 07:28:20 AM UTC 24 |
| Peak memory | 210844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429132523 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_wakeup.1429132523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/16.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup_fixed.2912182663 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 188412715378 ps |
| CPU time | 240.69 seconds |
| Started | Sep 24 07:17:05 AM UTC 24 |
| Finished | Sep 24 07:21:09 AM UTC 24 |
| Peak memory | 210696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912182663 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_wakeup_fixed.2912182663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/16.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_fsm_reset.658324614 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 94586281134 ps |
| CPU time | 553.13 seconds |
| Started | Sep 24 07:17:58 AM UTC 24 |
| Finished | Sep 24 07:27:16 AM UTC 24 |
| Peak memory | 211120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658324614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.658324614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/16.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_lowpower_counter.597668690 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 41808363002 ps |
| CPU time | 175.57 seconds |
| Started | Sep 24 07:17:54 AM UTC 24 |
| Finished | Sep 24 07:20:53 AM UTC 24 |
| Peak memory | 210572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597668690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.597668690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/16.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_poweron_counter.1624390340 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 3027945041 ps |
| CPU time | 7.34 seconds |
| Started | Sep 24 07:17:48 AM UTC 24 |
| Finished | Sep 24 07:17:57 AM UTC 24 |
| Peak memory | 210760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624390340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.1624390340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/16.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_smoke.747437730 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 6075168243 ps |
| CPU time | 27.91 seconds |
| Started | Sep 24 07:15:45 AM UTC 24 |
| Finished | Sep 24 07:16:14 AM UTC 24 |
| Peak memory | 210764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747437730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.747437730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/16.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.316728047 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 4469971467 ps |
| CPU time | 18.84 seconds |
| Started | Sep 24 07:18:17 AM UTC 24 |
| Finished | Sep 24 07:18:37 AM UTC 24 |
| Peak memory | 221056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=316728047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.316728047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/16.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_alert_test.2835415681 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 486838872 ps |
| CPU time | 2.88 seconds |
| Started | Sep 24 07:20:05 AM UTC 24 |
| Finished | Sep 24 07:20:09 AM UTC 24 |
| Peak memory | 210448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835415681 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2835415681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/17.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_clock_gating.2204576020 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 505767054101 ps |
| CPU time | 409.64 seconds |
| Started | Sep 24 07:19:11 AM UTC 24 |
| Finished | Sep 24 07:26:06 AM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204576020 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gating.2204576020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/17.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_both.3852753161 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 169001200760 ps |
| CPU time | 158.01 seconds |
| Started | Sep 24 07:19:18 AM UTC 24 |
| Finished | Sep 24 07:21:59 AM UTC 24 |
| Peak memory | 210860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852753161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.3852753161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/17.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt.2409376026 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 163494592673 ps |
| CPU time | 142.79 seconds |
| Started | Sep 24 07:18:44 AM UTC 24 |
| Finished | Sep 24 07:21:09 AM UTC 24 |
| Peak memory | 210792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409376026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.2409376026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/17.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2560660423 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 498157599779 ps |
| CPU time | 1069.09 seconds |
| Started | Sep 24 07:18:54 AM UTC 24 |
| Finished | Sep 24 07:36:55 AM UTC 24 |
| Peak memory | 213372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560660423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt_fixed.2560660423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/17.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled.1741925953 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 162387843677 ps |
| CPU time | 146.16 seconds |
| Started | Sep 24 07:18:41 AM UTC 24 |
| Finished | Sep 24 07:21:09 AM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741925953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.1741925953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/17.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled_fixed.1197305381 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 159104880352 ps |
| CPU time | 130.81 seconds |
| Started | Sep 24 07:18:43 AM UTC 24 |
| Finished | Sep 24 07:20:56 AM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197305381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixed.1197305381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/17.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup.1916845882 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 338525066329 ps |
| CPU time | 269.41 seconds |
| Started | Sep 24 07:18:55 AM UTC 24 |
| Finished | Sep 24 07:23:28 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916845882 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_wakeup.1916845882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/17.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3194048513 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 417906153123 ps |
| CPU time | 169.2 seconds |
| Started | Sep 24 07:18:57 AM UTC 24 |
| Finished | Sep 24 07:21:49 AM UTC 24 |
| Peak memory | 210696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194048513 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_wakeup_fixed.3194048513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/17.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_fsm_reset.1690476639 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 103431571970 ps |
| CPU time | 379.95 seconds |
| Started | Sep 24 07:19:37 AM UTC 24 |
| Finished | Sep 24 07:26:01 AM UTC 24 |
| Peak memory | 211052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690476639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.1690476639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/17.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_lowpower_counter.2755167537 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 32811412658 ps |
| CPU time | 37.02 seconds |
| Started | Sep 24 07:19:26 AM UTC 24 |
| Finished | Sep 24 07:20:04 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755167537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.2755167537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/17.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_poweron_counter.3452110788 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 5399241517 ps |
| CPU time | 12.43 seconds |
| Started | Sep 24 07:19:23 AM UTC 24 |
| Finished | Sep 24 07:19:36 AM UTC 24 |
| Peak memory | 210824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452110788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.3452110788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/17.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_smoke.2469136210 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 5802103783 ps |
| CPU time | 15.77 seconds |
| Started | Sep 24 07:18:40 AM UTC 24 |
| Finished | Sep 24 07:18:57 AM UTC 24 |
| Peak memory | 210832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469136210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.2469136210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/17.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.183989249 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 1585862518 ps |
| CPU time | 5.46 seconds |
| Started | Sep 24 07:19:40 AM UTC 24 |
| Finished | Sep 24 07:19:46 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=183989249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.183989249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_alert_test.3035393864 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 428683073 ps |
| CPU time | 1.25 seconds |
| Started | Sep 24 07:21:10 AM UTC 24 |
| Finished | Sep 24 07:21:12 AM UTC 24 |
| Peak memory | 208688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035393864 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.3035393864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/18.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_clock_gating.4108863095 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 352224842758 ps |
| CPU time | 1012.69 seconds |
| Started | Sep 24 07:20:43 AM UTC 24 |
| Finished | Sep 24 07:37:47 AM UTC 24 |
| Peak memory | 213424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108863095 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gating.4108863095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/18.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_both.2475164896 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 162560494161 ps |
| CPU time | 162.35 seconds |
| Started | Sep 24 07:20:48 AM UTC 24 |
| Finished | Sep 24 07:23:33 AM UTC 24 |
| Peak memory | 210800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475164896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2475164896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/18.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt.2092378708 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 164780610591 ps |
| CPU time | 128.45 seconds |
| Started | Sep 24 07:20:20 AM UTC 24 |
| Finished | Sep 24 07:22:31 AM UTC 24 |
| Peak memory | 210728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092378708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.2092378708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/18.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt_fixed.833483967 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 335788004003 ps |
| CPU time | 550.54 seconds |
| Started | Sep 24 07:20:23 AM UTC 24 |
| Finished | Sep 24 07:29:40 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833483967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt_fixed.833483967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/18.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled.3446367029 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 166318665822 ps |
| CPU time | 169.36 seconds |
| Started | Sep 24 07:20:10 AM UTC 24 |
| Finished | Sep 24 07:23:02 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446367029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.3446367029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/18.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled_fixed.1530196574 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 164667541681 ps |
| CPU time | 262.68 seconds |
| Started | Sep 24 07:20:14 AM UTC 24 |
| Finished | Sep 24 07:24:40 AM UTC 24 |
| Peak memory | 210780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530196574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixed.1530196574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/18.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_wakeup.1373684318 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 189899280709 ps |
| CPU time | 186.77 seconds |
| Started | Sep 24 07:20:28 AM UTC 24 |
| Finished | Sep 24 07:23:38 AM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373684318 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_wakeup.1373684318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/18.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1494174679 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 594804395557 ps |
| CPU time | 746.53 seconds |
| Started | Sep 24 07:20:34 AM UTC 24 |
| Finished | Sep 24 07:33:09 AM UTC 24 |
| Peak memory | 213436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494174679 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_wakeup_fixed.1494174679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/18.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_fsm_reset.918797431 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 67414102195 ps |
| CPU time | 466.29 seconds |
| Started | Sep 24 07:20:57 AM UTC 24 |
| Finished | Sep 24 07:28:49 AM UTC 24 |
| Peak memory | 211184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918797431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.918797431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/18.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_lowpower_counter.3815289167 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 42515648148 ps |
| CPU time | 101.97 seconds |
| Started | Sep 24 07:20:57 AM UTC 24 |
| Finished | Sep 24 07:22:41 AM UTC 24 |
| Peak memory | 210480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815289167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.3815289167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/18.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_poweron_counter.2508583084 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 4344820655 ps |
| CPU time | 2.08 seconds |
| Started | Sep 24 07:20:54 AM UTC 24 |
| Finished | Sep 24 07:20:57 AM UTC 24 |
| Peak memory | 210488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508583084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2508583084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/18.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_smoke.3096730353 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 6110507419 ps |
| CPU time | 2.71 seconds |
| Started | Sep 24 07:20:10 AM UTC 24 |
| Finished | Sep 24 07:20:14 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096730353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.3096730353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/18.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all.2150940181 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 169534119206 ps |
| CPU time | 218.44 seconds |
| Started | Sep 24 07:21:10 AM UTC 24 |
| Finished | Sep 24 07:24:51 AM UTC 24 |
| Peak memory | 211040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150940181 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.2150940181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/18.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3844526230 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 166089653024 ps |
| CPU time | 24 seconds |
| Started | Sep 24 07:20:58 AM UTC 24 |
| Finished | Sep 24 07:21:23 AM UTC 24 |
| Peak memory | 221632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3844526230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 18.adc_ctrl_stress_all_with_rand_reset.3844526230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/18.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_alert_test.191117623 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 315182315 ps |
| CPU time | 2.12 seconds |
| Started | Sep 24 07:22:24 AM UTC 24 |
| Finished | Sep 24 07:22:27 AM UTC 24 |
| Peak memory | 210368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191117623 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.191117623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/19.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_both.1248540613 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 322760162065 ps |
| CPU time | 106.09 seconds |
| Started | Sep 24 07:21:54 AM UTC 24 |
| Finished | Sep 24 07:23:42 AM UTC 24 |
| Peak memory | 210756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248540613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1248540613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/19.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3615820259 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 166486579214 ps |
| CPU time | 63.84 seconds |
| Started | Sep 24 07:21:34 AM UTC 24 |
| Finished | Sep 24 07:22:40 AM UTC 24 |
| Peak memory | 210688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615820259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt_fixed.3615820259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/19.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled_fixed.2167932978 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 163184454041 ps |
| CPU time | 145.88 seconds |
| Started | Sep 24 07:21:24 AM UTC 24 |
| Finished | Sep 24 07:23:53 AM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167932978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixed.2167932978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/19.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup.2999845267 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 172923045970 ps |
| CPU time | 369.7 seconds |
| Started | Sep 24 07:21:41 AM UTC 24 |
| Finished | Sep 24 07:27:56 AM UTC 24 |
| Peak memory | 210784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999845267 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_wakeup.2999845267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/19.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup_fixed.878857482 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 397656497067 ps |
| CPU time | 1200.34 seconds |
| Started | Sep 24 07:21:49 AM UTC 24 |
| Finished | Sep 24 07:42:03 AM UTC 24 |
| Peak memory | 213624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878857482 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_wakeup_fixed.878857482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/19.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_fsm_reset.1884131089 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 94564010788 ps |
| CPU time | 732.4 seconds |
| Started | Sep 24 07:22:11 AM UTC 24 |
| Finished | Sep 24 07:34:31 AM UTC 24 |
| Peak memory | 214104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884131089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.1884131089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/19.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_lowpower_counter.2200679227 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 30107505447 ps |
| CPU time | 109.07 seconds |
| Started | Sep 24 07:22:03 AM UTC 24 |
| Finished | Sep 24 07:23:54 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200679227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2200679227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/19.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_poweron_counter.2476477634 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 4521429039 ps |
| CPU time | 21.68 seconds |
| Started | Sep 24 07:22:00 AM UTC 24 |
| Finished | Sep 24 07:22:23 AM UTC 24 |
| Peak memory | 210824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476477634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.2476477634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/19.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_smoke.756636016 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 5674060957 ps |
| CPU time | 21.99 seconds |
| Started | Sep 24 07:21:10 AM UTC 24 |
| Finished | Sep 24 07:21:33 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756636016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.756636016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/19.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_alert_test.3037692540 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 402987902 ps |
| CPU time | 1.56 seconds |
| Started | Sep 24 06:58:37 AM UTC 24 |
| Finished | Sep 24 06:58:40 AM UTC 24 |
| Peak memory | 208684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037692540 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.3037692540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/2.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.1072166576 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 339730405278 ps |
| CPU time | 261.12 seconds |
| Started | Sep 24 06:58:27 AM UTC 24 |
| Finished | Sep 24 07:02:52 AM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072166576 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gating.1072166576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/2.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.2376846586 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 189636823024 ps |
| CPU time | 286.51 seconds |
| Started | Sep 24 06:58:27 AM UTC 24 |
| Finished | Sep 24 07:03:17 AM UTC 24 |
| Peak memory | 210780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376846586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.2376846586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/2.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt.2376419571 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 483650929622 ps |
| CPU time | 384.55 seconds |
| Started | Sep 24 06:58:25 AM UTC 24 |
| Finished | Sep 24 07:04:55 AM UTC 24 |
| Peak memory | 210724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376419571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2376419571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/2.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1224566920 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 167079310787 ps |
| CPU time | 149.46 seconds |
| Started | Sep 24 06:58:25 AM UTC 24 |
| Finished | Sep 24 07:00:58 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224566920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt_fixed.1224566920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/2.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled.2855542879 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 485867943302 ps |
| CPU time | 302.08 seconds |
| Started | Sep 24 06:58:25 AM UTC 24 |
| Finished | Sep 24 07:03:31 AM UTC 24 |
| Peak memory | 211108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855542879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.2855542879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/2.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled_fixed.1894545313 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 165203546049 ps |
| CPU time | 419.48 seconds |
| Started | Sep 24 06:58:25 AM UTC 24 |
| Finished | Sep 24 07:05:30 AM UTC 24 |
| Peak memory | 210768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894545313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed.1894545313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/2.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup_fixed.1110571462 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 401577329695 ps |
| CPU time | 824.44 seconds |
| Started | Sep 24 06:58:25 AM UTC 24 |
| Finished | Sep 24 07:12:20 AM UTC 24 |
| Peak memory | 213436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110571462 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_wakeup_fixed.1110571462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/2.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_fsm_reset.731507103 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 131175702939 ps |
| CPU time | 524.23 seconds |
| Started | Sep 24 06:58:28 AM UTC 24 |
| Finished | Sep 24 07:07:17 AM UTC 24 |
| Peak memory | 211108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731507103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.731507103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/2.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_lowpower_counter.1109158485 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 36593024886 ps |
| CPU time | 102.21 seconds |
| Started | Sep 24 06:58:28 AM UTC 24 |
| Finished | Sep 24 07:00:12 AM UTC 24 |
| Peak memory | 210496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109158485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.1109158485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/2.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_poweron_counter.4148911194 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4161070733 ps |
| CPU time | 17.64 seconds |
| Started | Sep 24 06:58:28 AM UTC 24 |
| Finished | Sep 24 06:58:47 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148911194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.4148911194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/2.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_smoke.3679412402 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 6015799262 ps |
| CPU time | 17.57 seconds |
| Started | Sep 24 06:58:23 AM UTC 24 |
| Finished | Sep 24 06:58:42 AM UTC 24 |
| Peak memory | 210508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679412402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3679412402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/2.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all.3614015128 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 104499394918 ps |
| CPU time | 765.83 seconds |
| Started | Sep 24 06:58:35 AM UTC 24 |
| Finished | Sep 24 07:11:29 AM UTC 24 |
| Peak memory | 213708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614015128 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.3614015128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.170350210 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1460563587 ps |
| CPU time | 8.59 seconds |
| Started | Sep 24 06:58:32 AM UTC 24 |
| Finished | Sep 24 06:58:42 AM UTC 24 |
| Peak memory | 210488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=170350210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.170350210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_alert_test.3153018846 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 522394763 ps |
| CPU time | 2.26 seconds |
| Started | Sep 24 07:23:43 AM UTC 24 |
| Finished | Sep 24 07:23:46 AM UTC 24 |
| Peak memory | 210444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153018846 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.3153018846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/20.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_both.775735750 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 338410147254 ps |
| CPU time | 438.16 seconds |
| Started | Sep 24 07:23:03 AM UTC 24 |
| Finished | Sep 24 07:30:26 AM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775735750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.775735750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/20.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_interrupt.4168279588 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 166803049150 ps |
| CPU time | 180.39 seconds |
| Started | Sep 24 07:22:40 AM UTC 24 |
| Finished | Sep 24 07:25:44 AM UTC 24 |
| Peak memory | 210720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168279588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.4168279588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/20.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3586086414 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 160590379863 ps |
| CPU time | 227.98 seconds |
| Started | Sep 24 07:22:41 AM UTC 24 |
| Finished | Sep 24 07:26:32 AM UTC 24 |
| Peak memory | 210748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586086414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt_fixed.3586086414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/20.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_polled.3784901885 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 482206887915 ps |
| CPU time | 289.69 seconds |
| Started | Sep 24 07:22:32 AM UTC 24 |
| Finished | Sep 24 07:27:25 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784901885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3784901885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/20.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_polled_fixed.2272509821 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 156714806144 ps |
| CPU time | 363.41 seconds |
| Started | Sep 24 07:22:35 AM UTC 24 |
| Finished | Sep 24 07:28:43 AM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272509821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixed.2272509821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/20.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_wakeup.2615340941 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 521923621594 ps |
| CPU time | 644.64 seconds |
| Started | Sep 24 07:22:42 AM UTC 24 |
| Finished | Sep 24 07:33:34 AM UTC 24 |
| Peak memory | 210772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615340941 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_wakeup.2615340941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/20.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_wakeup_fixed.2025005358 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 618830796454 ps |
| CPU time | 771.54 seconds |
| Started | Sep 24 07:22:45 AM UTC 24 |
| Finished | Sep 24 07:35:45 AM UTC 24 |
| Peak memory | 213484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025005358 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_wakeup_fixed.2025005358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/20.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_fsm_reset.2385295058 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 126025043200 ps |
| CPU time | 446.61 seconds |
| Started | Sep 24 07:23:36 AM UTC 24 |
| Finished | Sep 24 07:31:07 AM UTC 24 |
| Peak memory | 211124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385295058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2385295058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/20.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_lowpower_counter.730040227 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 40846833755 ps |
| CPU time | 123.76 seconds |
| Started | Sep 24 07:23:34 AM UTC 24 |
| Finished | Sep 24 07:25:40 AM UTC 24 |
| Peak memory | 210572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730040227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.730040227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/20.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_poweron_counter.100673657 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 2782288450 ps |
| CPU time | 12.22 seconds |
| Started | Sep 24 07:23:29 AM UTC 24 |
| Finished | Sep 24 07:23:42 AM UTC 24 |
| Peak memory | 210492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100673657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.100673657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/20.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_smoke.3174831399 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 6006047109 ps |
| CPU time | 23.99 seconds |
| Started | Sep 24 07:22:28 AM UTC 24 |
| Finished | Sep 24 07:22:53 AM UTC 24 |
| Peak memory | 210576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174831399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3174831399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/20.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all.443564096 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 169332537982 ps |
| CPU time | 393.96 seconds |
| Started | Sep 24 07:23:39 AM UTC 24 |
| Finished | Sep 24 07:30:18 AM UTC 24 |
| Peak memory | 210788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443564096 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.443564096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/20.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.3788989407 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 8442456789 ps |
| CPU time | 12.36 seconds |
| Started | Sep 24 07:23:39 AM UTC 24 |
| Finished | Sep 24 07:23:52 AM UTC 24 |
| Peak memory | 211228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3788989407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 20.adc_ctrl_stress_all_with_rand_reset.3788989407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/20.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_alert_test.1533597240 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 431052338 ps |
| CPU time | 2.61 seconds |
| Started | Sep 24 07:24:39 AM UTC 24 |
| Finished | Sep 24 07:24:43 AM UTC 24 |
| Peak memory | 210364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533597240 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1533597240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/21.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_both.2371396132 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 571628982636 ps |
| CPU time | 1102.31 seconds |
| Started | Sep 24 07:24:04 AM UTC 24 |
| Finished | Sep 24 07:42:39 AM UTC 24 |
| Peak memory | 213704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371396132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.2371396132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/21.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_interrupt.76787510 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 164207910804 ps |
| CPU time | 423.82 seconds |
| Started | Sep 24 07:23:51 AM UTC 24 |
| Finished | Sep 24 07:31:00 AM UTC 24 |
| Peak memory | 210720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76787510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_ SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.76787510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/21.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_interrupt_fixed.13526825 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 162348828793 ps |
| CPU time | 666.48 seconds |
| Started | Sep 24 07:23:53 AM UTC 24 |
| Finished | Sep 24 07:35:08 AM UTC 24 |
| Peak memory | 210724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13526825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas e_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt_fixed.13526825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/21.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_polled.4173744359 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 159488500980 ps |
| CPU time | 120.52 seconds |
| Started | Sep 24 07:23:47 AM UTC 24 |
| Finished | Sep 24 07:25:50 AM UTC 24 |
| Peak memory | 210792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173744359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.4173744359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/21.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_polled_fixed.4003345981 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 327326336734 ps |
| CPU time | 92.76 seconds |
| Started | Sep 24 07:23:47 AM UTC 24 |
| Finished | Sep 24 07:25:22 AM UTC 24 |
| Peak memory | 211032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003345981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fixed.4003345981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/21.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_wakeup_fixed.1377119328 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 205258733379 ps |
| CPU time | 524.77 seconds |
| Started | Sep 24 07:23:54 AM UTC 24 |
| Finished | Sep 24 07:32:45 AM UTC 24 |
| Peak memory | 210696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377119328 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_wakeup_fixed.1377119328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/21.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_lowpower_counter.3843558054 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 35176999409 ps |
| CPU time | 40.06 seconds |
| Started | Sep 24 07:24:26 AM UTC 24 |
| Finished | Sep 24 07:25:07 AM UTC 24 |
| Peak memory | 210572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843558054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.3843558054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/21.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_poweron_counter.955795977 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 4663296381 ps |
| CPU time | 21.22 seconds |
| Started | Sep 24 07:24:05 AM UTC 24 |
| Finished | Sep 24 07:24:27 AM UTC 24 |
| Peak memory | 210496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955795977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.955795977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/21.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_smoke.1548696815 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 5925698379 ps |
| CPU time | 6.4 seconds |
| Started | Sep 24 07:23:43 AM UTC 24 |
| Finished | Sep 24 07:23:50 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548696815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.1548696815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/21.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.826451675 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 776471443813 ps |
| CPU time | 73.33 seconds |
| Started | Sep 24 07:24:29 AM UTC 24 |
| Finished | Sep 24 07:25:44 AM UTC 24 |
| Peak memory | 220996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=826451675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.826451675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/21.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_alert_test.800885892 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 376760623 ps |
| CPU time | 1.27 seconds |
| Started | Sep 24 07:25:45 AM UTC 24 |
| Finished | Sep 24 07:25:47 AM UTC 24 |
| Peak memory | 210444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800885892 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.800885892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/22.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_clock_gating.2233314009 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 329184509883 ps |
| CPU time | 171.26 seconds |
| Started | Sep 24 07:25:22 AM UTC 24 |
| Finished | Sep 24 07:28:17 AM UTC 24 |
| Peak memory | 211036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233314009 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gating.2233314009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/22.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_both.3712232105 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 163074979994 ps |
| CPU time | 127.97 seconds |
| Started | Sep 24 07:25:22 AM UTC 24 |
| Finished | Sep 24 07:27:33 AM UTC 24 |
| Peak memory | 210720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712232105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.3712232105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/22.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_interrupt.504444975 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 326195987814 ps |
| CPU time | 164.55 seconds |
| Started | Sep 24 07:24:54 AM UTC 24 |
| Finished | Sep 24 07:27:41 AM UTC 24 |
| Peak memory | 210796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504444975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.504444975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/22.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_interrupt_fixed.241663612 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 330469114782 ps |
| CPU time | 860.32 seconds |
| Started | Sep 24 07:25:08 AM UTC 24 |
| Finished | Sep 24 07:39:37 AM UTC 24 |
| Peak memory | 213044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241663612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt_fixed.241663612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/22.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_polled.3093952827 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 498897974099 ps |
| CPU time | 1408.63 seconds |
| Started | Sep 24 07:24:43 AM UTC 24 |
| Finished | Sep 24 07:48:26 AM UTC 24 |
| Peak memory | 213448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093952827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.3093952827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/22.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_polled_fixed.1925921851 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 494464626209 ps |
| CPU time | 382.02 seconds |
| Started | Sep 24 07:24:52 AM UTC 24 |
| Finished | Sep 24 07:31:19 AM UTC 24 |
| Peak memory | 210760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925921851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixed.1925921851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/22.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_wakeup.1187321776 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 388975716618 ps |
| CPU time | 989.97 seconds |
| Started | Sep 24 07:25:08 AM UTC 24 |
| Finished | Sep 24 07:41:48 AM UTC 24 |
| Peak memory | 213080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187321776 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_wakeup.1187321776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/22.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_wakeup_fixed.3696294427 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 189865647911 ps |
| CPU time | 477.12 seconds |
| Started | Sep 24 07:25:10 AM UTC 24 |
| Finished | Sep 24 07:33:13 AM UTC 24 |
| Peak memory | 210696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696294427 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_wakeup_fixed.3696294427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/22.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_fsm_reset.1583515482 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 69777008239 ps |
| CPU time | 380.13 seconds |
| Started | Sep 24 07:25:40 AM UTC 24 |
| Finished | Sep 24 07:32:04 AM UTC 24 |
| Peak memory | 211380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583515482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.1583515482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/22.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_lowpower_counter.1279414228 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 39110168502 ps |
| CPU time | 115.42 seconds |
| Started | Sep 24 07:25:34 AM UTC 24 |
| Finished | Sep 24 07:27:31 AM UTC 24 |
| Peak memory | 210480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279414228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1279414228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/22.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_poweron_counter.1443307176 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 3590410974 ps |
| CPU time | 8.03 seconds |
| Started | Sep 24 07:25:30 AM UTC 24 |
| Finished | Sep 24 07:25:39 AM UTC 24 |
| Peak memory | 210488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443307176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.1443307176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/22.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_smoke.1809490293 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 5928789182 ps |
| CPU time | 25.38 seconds |
| Started | Sep 24 07:24:41 AM UTC 24 |
| Finished | Sep 24 07:25:08 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809490293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.1809490293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/22.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_stress_all.3617272396 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 191780501874 ps |
| CPU time | 571.07 seconds |
| Started | Sep 24 07:25:44 AM UTC 24 |
| Finished | Sep 24 07:35:21 AM UTC 24 |
| Peak memory | 210708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617272396 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.3617272396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/22.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1701235877 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 23334646118 ps |
| CPU time | 32.46 seconds |
| Started | Sep 24 07:25:41 AM UTC 24 |
| Finished | Sep 24 07:26:15 AM UTC 24 |
| Peak memory | 221128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1701235877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 22.adc_ctrl_stress_all_with_rand_reset.1701235877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/22.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_alert_test.395884833 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 478319677 ps |
| CPU time | 2.77 seconds |
| Started | Sep 24 07:27:32 AM UTC 24 |
| Finished | Sep 24 07:27:36 AM UTC 24 |
| Peak memory | 210632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395884833 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.395884833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/23.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_clock_gating.603502712 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 424562447927 ps |
| CPU time | 928.29 seconds |
| Started | Sep 24 07:26:41 AM UTC 24 |
| Finished | Sep 24 07:42:19 AM UTC 24 |
| Peak memory | 213752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603502712 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gating.603502712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/23.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_interrupt.585137159 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 332938680818 ps |
| CPU time | 207.28 seconds |
| Started | Sep 24 07:26:01 AM UTC 24 |
| Finished | Sep 24 07:29:31 AM UTC 24 |
| Peak memory | 210740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585137159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.585137159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/23.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_interrupt_fixed.1964527743 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 323696974959 ps |
| CPU time | 239.79 seconds |
| Started | Sep 24 07:26:07 AM UTC 24 |
| Finished | Sep 24 07:30:10 AM UTC 24 |
| Peak memory | 210756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964527743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt_fixed.1964527743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/23.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_polled.1084266612 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 331327722598 ps |
| CPU time | 231.91 seconds |
| Started | Sep 24 07:25:50 AM UTC 24 |
| Finished | Sep 24 07:29:45 AM UTC 24 |
| Peak memory | 210792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084266612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.1084266612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/23.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_polled_fixed.1585266255 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 489232875015 ps |
| CPU time | 238.28 seconds |
| Started | Sep 24 07:25:57 AM UTC 24 |
| Finished | Sep 24 07:29:59 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585266255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixed.1585266255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/23.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_wakeup_fixed.2696168004 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 388372541131 ps |
| CPU time | 968.14 seconds |
| Started | Sep 24 07:26:33 AM UTC 24 |
| Finished | Sep 24 07:42:51 AM UTC 24 |
| Peak memory | 213508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696168004 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_wakeup_fixed.2696168004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/23.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_fsm_reset.2762726631 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 105923266564 ps |
| CPU time | 703.67 seconds |
| Started | Sep 24 07:27:24 AM UTC 24 |
| Finished | Sep 24 07:39:15 AM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762726631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2762726631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/23.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_lowpower_counter.347069700 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 26549564884 ps |
| CPU time | 51.97 seconds |
| Started | Sep 24 07:27:17 AM UTC 24 |
| Finished | Sep 24 07:28:11 AM UTC 24 |
| Peak memory | 210480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347069700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.347069700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/23.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_poweron_counter.3281315261 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 3024837168 ps |
| CPU time | 7.07 seconds |
| Started | Sep 24 07:27:15 AM UTC 24 |
| Finished | Sep 24 07:27:23 AM UTC 24 |
| Peak memory | 210568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281315261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3281315261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/23.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_smoke.3709682756 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 5568324619 ps |
| CPU time | 7.34 seconds |
| Started | Sep 24 07:25:48 AM UTC 24 |
| Finished | Sep 24 07:25:56 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709682756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.3709682756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/23.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1668473934 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 32715545312 ps |
| CPU time | 11.88 seconds |
| Started | Sep 24 07:27:26 AM UTC 24 |
| Finished | Sep 24 07:27:39 AM UTC 24 |
| Peak memory | 221344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1668473934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 23.adc_ctrl_stress_all_with_rand_reset.1668473934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/23.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_alert_test.3304230464 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 346736353 ps |
| CPU time | 2.26 seconds |
| Started | Sep 24 07:28:33 AM UTC 24 |
| Finished | Sep 24 07:28:36 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304230464 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.3304230464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/24.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_clock_gating.1792940765 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 501775651371 ps |
| CPU time | 1132.96 seconds |
| Started | Sep 24 07:28:11 AM UTC 24 |
| Finished | Sep 24 07:47:15 AM UTC 24 |
| Peak memory | 213364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792940765 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gating.1792940765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/24.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_both.962766388 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 404800132582 ps |
| CPU time | 550.36 seconds |
| Started | Sep 24 07:28:12 AM UTC 24 |
| Finished | Sep 24 07:37:28 AM UTC 24 |
| Peak memory | 210716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962766388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.962766388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/24.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_interrupt.2250301491 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 490108295938 ps |
| CPU time | 1249.34 seconds |
| Started | Sep 24 07:27:41 AM UTC 24 |
| Finished | Sep 24 07:48:43 AM UTC 24 |
| Peak memory | 213508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250301491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2250301491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/24.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_interrupt_fixed.3388505350 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 161081444507 ps |
| CPU time | 71.44 seconds |
| Started | Sep 24 07:27:41 AM UTC 24 |
| Finished | Sep 24 07:28:55 AM UTC 24 |
| Peak memory | 210772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388505350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt_fixed.3388505350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/24.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_polled.1605955245 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 326652974557 ps |
| CPU time | 882.28 seconds |
| Started | Sep 24 07:27:37 AM UTC 24 |
| Finished | Sep 24 07:42:29 AM UTC 24 |
| Peak memory | 213444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605955245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.1605955245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/24.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_polled_fixed.1046082384 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 166089116976 ps |
| CPU time | 110.94 seconds |
| Started | Sep 24 07:27:39 AM UTC 24 |
| Finished | Sep 24 07:29:32 AM UTC 24 |
| Peak memory | 211032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046082384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixed.1046082384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/24.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_wakeup.1930672743 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 547812410065 ps |
| CPU time | 1669.93 seconds |
| Started | Sep 24 07:27:42 AM UTC 24 |
| Finished | Sep 24 07:55:50 AM UTC 24 |
| Peak memory | 213364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930672743 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_wakeup.1930672743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/24.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_wakeup_fixed.3370622384 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 217986799693 ps |
| CPU time | 156.7 seconds |
| Started | Sep 24 07:27:57 AM UTC 24 |
| Finished | Sep 24 07:30:36 AM UTC 24 |
| Peak memory | 211088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370622384 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_wakeup_fixed.3370622384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/24.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_fsm_reset.1218438090 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 68325434125 ps |
| CPU time | 360.23 seconds |
| Started | Sep 24 07:28:30 AM UTC 24 |
| Finished | Sep 24 07:34:34 AM UTC 24 |
| Peak memory | 211140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218438090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1218438090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/24.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_lowpower_counter.1097135349 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 24833771191 ps |
| CPU time | 16.94 seconds |
| Started | Sep 24 07:28:21 AM UTC 24 |
| Finished | Sep 24 07:28:39 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097135349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1097135349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/24.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_poweron_counter.2384300367 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 4773105145 ps |
| CPU time | 10.69 seconds |
| Started | Sep 24 07:28:17 AM UTC 24 |
| Finished | Sep 24 07:28:29 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384300367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2384300367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/24.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_smoke.633592140 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 5783201430 ps |
| CPU time | 5.2 seconds |
| Started | Sep 24 07:27:34 AM UTC 24 |
| Finished | Sep 24 07:27:41 AM UTC 24 |
| Peak memory | 210572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633592140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.633592140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/24.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_stress_all.2167387198 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 375486393002 ps |
| CPU time | 573.73 seconds |
| Started | Sep 24 07:28:32 AM UTC 24 |
| Finished | Sep 24 07:38:12 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167387198 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.2167387198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/24.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2267288963 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 7910980093 ps |
| CPU time | 24.51 seconds |
| Started | Sep 24 07:28:30 AM UTC 24 |
| Finished | Sep 24 07:28:56 AM UTC 24 |
| Peak memory | 221744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2267288963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 24.adc_ctrl_stress_all_with_rand_reset.2267288963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/24.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_alert_test.1530772227 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 328207176 ps |
| CPU time | 1.85 seconds |
| Started | Sep 24 07:29:44 AM UTC 24 |
| Finished | Sep 24 07:29:47 AM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530772227 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1530772227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/25.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_clock_gating.3478290520 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 199236898153 ps |
| CPU time | 531.23 seconds |
| Started | Sep 24 07:28:57 AM UTC 24 |
| Finished | Sep 24 07:37:54 AM UTC 24 |
| Peak memory | 210772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478290520 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gating.3478290520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/25.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_interrupt.2206805727 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 165627359338 ps |
| CPU time | 411.65 seconds |
| Started | Sep 24 07:28:43 AM UTC 24 |
| Finished | Sep 24 07:35:40 AM UTC 24 |
| Peak memory | 210852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206805727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2206805727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/25.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_interrupt_fixed.691479783 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 166091414765 ps |
| CPU time | 421.28 seconds |
| Started | Sep 24 07:28:46 AM UTC 24 |
| Finished | Sep 24 07:35:53 AM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691479783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt_fixed.691479783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/25.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_polled.3453854736 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 330830102308 ps |
| CPU time | 220.59 seconds |
| Started | Sep 24 07:28:39 AM UTC 24 |
| Finished | Sep 24 07:32:23 AM UTC 24 |
| Peak memory | 210848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453854736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.3453854736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/25.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_polled_fixed.292771875 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 327020145184 ps |
| CPU time | 236.76 seconds |
| Started | Sep 24 07:28:40 AM UTC 24 |
| Finished | Sep 24 07:32:40 AM UTC 24 |
| Peak memory | 210752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292771875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixed.292771875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/25.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_wakeup.257388237 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 192221997106 ps |
| CPU time | 143.17 seconds |
| Started | Sep 24 07:28:49 AM UTC 24 |
| Finished | Sep 24 07:31:15 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257388237 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_wakeup.257388237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/25.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_wakeup_fixed.584488245 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 200613931982 ps |
| CPU time | 143.75 seconds |
| Started | Sep 24 07:28:55 AM UTC 24 |
| Finished | Sep 24 07:31:22 AM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584488245 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_wakeup_fixed.584488245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/25.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_fsm_reset.2165289836 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 111335703690 ps |
| CPU time | 527.71 seconds |
| Started | Sep 24 07:29:32 AM UTC 24 |
| Finished | Sep 24 07:38:25 AM UTC 24 |
| Peak memory | 211068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165289836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2165289836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/25.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_lowpower_counter.2995352811 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 27326373561 ps |
| CPU time | 52.13 seconds |
| Started | Sep 24 07:29:29 AM UTC 24 |
| Finished | Sep 24 07:30:22 AM UTC 24 |
| Peak memory | 210764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995352811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.2995352811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/25.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_poweron_counter.3976505229 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 5058941741 ps |
| CPU time | 3.58 seconds |
| Started | Sep 24 07:29:24 AM UTC 24 |
| Finished | Sep 24 07:29:28 AM UTC 24 |
| Peak memory | 210488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976505229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.3976505229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/25.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_smoke.3981705864 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 6010667593 ps |
| CPU time | 7 seconds |
| Started | Sep 24 07:28:37 AM UTC 24 |
| Finished | Sep 24 07:28:45 AM UTC 24 |
| Peak memory | 210576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981705864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3981705864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/25.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_stress_all.1752750666 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 637312953382 ps |
| CPU time | 1687.69 seconds |
| Started | Sep 24 07:29:41 AM UTC 24 |
| Finished | Sep 24 07:58:06 AM UTC 24 |
| Peak memory | 213628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752750666 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.1752750666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/25.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2515068906 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 2048286325 ps |
| CPU time | 9.2 seconds |
| Started | Sep 24 07:29:33 AM UTC 24 |
| Finished | Sep 24 07:29:43 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2515068906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 25.adc_ctrl_stress_all_with_rand_reset.2515068906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/25.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_alert_test.127308728 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 465898241 ps |
| CPU time | 1.87 seconds |
| Started | Sep 24 07:31:02 AM UTC 24 |
| Finished | Sep 24 07:31:05 AM UTC 24 |
| Peak memory | 210564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127308728 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.127308728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/26.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_clock_gating.3199510503 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 510822638454 ps |
| CPU time | 1280.74 seconds |
| Started | Sep 24 07:30:24 AM UTC 24 |
| Finished | Sep 24 07:51:57 AM UTC 24 |
| Peak memory | 213424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199510503 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gating.3199510503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/26.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_interrupt.3984044017 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 326491076720 ps |
| CPU time | 922.23 seconds |
| Started | Sep 24 07:30:11 AM UTC 24 |
| Finished | Sep 24 07:45:43 AM UTC 24 |
| Peak memory | 210796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984044017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.3984044017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/26.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2609704913 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 165129051037 ps |
| CPU time | 443.27 seconds |
| Started | Sep 24 07:30:12 AM UTC 24 |
| Finished | Sep 24 07:37:41 AM UTC 24 |
| Peak memory | 210852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609704913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt_fixed.2609704913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/26.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_polled.87116513 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 485156313097 ps |
| CPU time | 586.89 seconds |
| Started | Sep 24 07:29:48 AM UTC 24 |
| Finished | Sep 24 07:39:41 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87116513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_ SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.87116513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/26.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_polled_fixed.763056602 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 164887177786 ps |
| CPU time | 558.69 seconds |
| Started | Sep 24 07:29:59 AM UTC 24 |
| Finished | Sep 24 07:39:24 AM UTC 24 |
| Peak memory | 210680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763056602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fixed.763056602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/26.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_wakeup.457203273 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 372326905192 ps |
| CPU time | 467.18 seconds |
| Started | Sep 24 07:30:18 AM UTC 24 |
| Finished | Sep 24 07:38:11 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457203273 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_wakeup.457203273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/26.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_wakeup_fixed.806272096 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 194756192179 ps |
| CPU time | 604.56 seconds |
| Started | Sep 24 07:30:22 AM UTC 24 |
| Finished | Sep 24 07:40:33 AM UTC 24 |
| Peak memory | 210840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806272096 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_wakeup_fixed.806272096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/26.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_fsm_reset.3201055511 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 98299195194 ps |
| CPU time | 721.62 seconds |
| Started | Sep 24 07:30:51 AM UTC 24 |
| Finished | Sep 24 07:43:00 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201055511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.3201055511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/26.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_lowpower_counter.3784076795 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 21418166058 ps |
| CPU time | 21.31 seconds |
| Started | Sep 24 07:30:39 AM UTC 24 |
| Finished | Sep 24 07:31:01 AM UTC 24 |
| Peak memory | 210572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784076795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.3784076795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/26.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_poweron_counter.1860065316 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 5215996463 ps |
| CPU time | 12.42 seconds |
| Started | Sep 24 07:30:37 AM UTC 24 |
| Finished | Sep 24 07:30:50 AM UTC 24 |
| Peak memory | 210488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860065316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1860065316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/26.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_smoke.2643190835 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 6078816903 ps |
| CPU time | 24.27 seconds |
| Started | Sep 24 07:29:46 AM UTC 24 |
| Finished | Sep 24 07:30:12 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643190835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2643190835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/26.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_stress_all.1971158651 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 420643752763 ps |
| CPU time | 1543.05 seconds |
| Started | Sep 24 07:31:01 AM UTC 24 |
| Finished | Sep 24 07:57:01 AM UTC 24 |
| Peak memory | 213964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971158651 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.1971158651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/26.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.1315206256 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 10336416870 ps |
| CPU time | 28.4 seconds |
| Started | Sep 24 07:31:01 AM UTC 24 |
| Finished | Sep 24 07:31:31 AM UTC 24 |
| Peak memory | 221596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1315206256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 26.adc_ctrl_stress_all_with_rand_reset.1315206256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/26.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_alert_test.1497357582 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 472667950 ps |
| CPU time | 2.9 seconds |
| Started | Sep 24 07:33:00 AM UTC 24 |
| Finished | Sep 24 07:33:04 AM UTC 24 |
| Peak memory | 210640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497357582 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1497357582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/27.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_clock_gating.773325157 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 430335416295 ps |
| CPU time | 175.42 seconds |
| Started | Sep 24 07:31:32 AM UTC 24 |
| Finished | Sep 24 07:34:30 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773325157 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gating.773325157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/27.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_both.2017166580 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 336393941373 ps |
| CPU time | 243.43 seconds |
| Started | Sep 24 07:32:05 AM UTC 24 |
| Finished | Sep 24 07:36:11 AM UTC 24 |
| Peak memory | 210780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017166580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.2017166580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/27.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_interrupt.652320708 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 495991895771 ps |
| CPU time | 1201.87 seconds |
| Started | Sep 24 07:31:16 AM UTC 24 |
| Finished | Sep 24 07:51:30 AM UTC 24 |
| Peak memory | 213368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652320708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.652320708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/27.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_interrupt_fixed.1203697581 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 170908380319 ps |
| CPU time | 534.76 seconds |
| Started | Sep 24 07:31:18 AM UTC 24 |
| Finished | Sep 24 07:40:19 AM UTC 24 |
| Peak memory | 210748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203697581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt_fixed.1203697581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/27.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_polled.2618357206 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 168742379142 ps |
| CPU time | 208.3 seconds |
| Started | Sep 24 07:31:08 AM UTC 24 |
| Finished | Sep 24 07:34:39 AM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618357206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.2618357206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/27.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_polled_fixed.975569298 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 328593373445 ps |
| CPU time | 216.94 seconds |
| Started | Sep 24 07:31:15 AM UTC 24 |
| Finished | Sep 24 07:34:55 AM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975569298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixed.975569298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/27.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_wakeup.1394597329 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 395650299350 ps |
| CPU time | 374.7 seconds |
| Started | Sep 24 07:31:19 AM UTC 24 |
| Finished | Sep 24 07:37:39 AM UTC 24 |
| Peak memory | 210784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394597329 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_wakeup.1394597329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/27.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_wakeup_fixed.860146918 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 204974811738 ps |
| CPU time | 135.98 seconds |
| Started | Sep 24 07:31:23 AM UTC 24 |
| Finished | Sep 24 07:33:41 AM UTC 24 |
| Peak memory | 210780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860146918 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_wakeup_fixed.860146918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/27.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_lowpower_counter.538408614 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 23720008179 ps |
| CPU time | 22.38 seconds |
| Started | Sep 24 07:32:36 AM UTC 24 |
| Finished | Sep 24 07:33:00 AM UTC 24 |
| Peak memory | 210764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538408614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.538408614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/27.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_poweron_counter.2620639604 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 4395270514 ps |
| CPU time | 10.2 seconds |
| Started | Sep 24 07:32:24 AM UTC 24 |
| Finished | Sep 24 07:32:35 AM UTC 24 |
| Peak memory | 210488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620639604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2620639604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/27.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_smoke.1035125836 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 5938723431 ps |
| CPU time | 10.32 seconds |
| Started | Sep 24 07:31:06 AM UTC 24 |
| Finished | Sep 24 07:31:17 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035125836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.1035125836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/27.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_stress_all.2752260484 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 489448054759 ps |
| CPU time | 1013.41 seconds |
| Started | Sep 24 07:33:00 AM UTC 24 |
| Finished | Sep 24 07:50:03 AM UTC 24 |
| Peak memory | 213564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752260484 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all.2752260484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/27.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.185643514 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 12891170333 ps |
| CPU time | 12.32 seconds |
| Started | Sep 24 07:32:46 AM UTC 24 |
| Finished | Sep 24 07:33:00 AM UTC 24 |
| Peak memory | 227200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=185643514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.185643514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/27.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_alert_test.1849113808 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 554779124 ps |
| CPU time | 1.44 seconds |
| Started | Sep 24 07:34:54 AM UTC 24 |
| Finished | Sep 24 07:34:58 AM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849113808 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.1849113808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/28.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_clock_gating.2645849347 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 327889318213 ps |
| CPU time | 143.43 seconds |
| Started | Sep 24 07:33:42 AM UTC 24 |
| Finished | Sep 24 07:36:08 AM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645849347 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gating.2645849347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/28.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_both.4145806066 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 176199540326 ps |
| CPU time | 480.13 seconds |
| Started | Sep 24 07:34:01 AM UTC 24 |
| Finished | Sep 24 07:42:06 AM UTC 24 |
| Peak memory | 210836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145806066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.4145806066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/28.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_interrupt.4243167051 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 493586440504 ps |
| CPU time | 1360.78 seconds |
| Started | Sep 24 07:33:14 AM UTC 24 |
| Finished | Sep 24 07:56:08 AM UTC 24 |
| Peak memory | 213468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243167051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.4243167051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/28.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2920000471 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 494463628389 ps |
| CPU time | 868.46 seconds |
| Started | Sep 24 07:33:14 AM UTC 24 |
| Finished | Sep 24 07:47:51 AM UTC 24 |
| Peak memory | 211020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920000471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt_fixed.2920000471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/28.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_polled.3791600808 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 489115025059 ps |
| CPU time | 329.51 seconds |
| Started | Sep 24 07:33:06 AM UTC 24 |
| Finished | Sep 24 07:38:40 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791600808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.3791600808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/28.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_polled_fixed.4155012900 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 487839859440 ps |
| CPU time | 333.17 seconds |
| Started | Sep 24 07:33:09 AM UTC 24 |
| Finished | Sep 24 07:38:47 AM UTC 24 |
| Peak memory | 210768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155012900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixed.4155012900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/28.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_wakeup_fixed.488754140 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 418314683049 ps |
| CPU time | 222.95 seconds |
| Started | Sep 24 07:33:35 AM UTC 24 |
| Finished | Sep 24 07:37:21 AM UTC 24 |
| Peak memory | 210704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488754140 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_wakeup_fixed.488754140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/28.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_fsm_reset.3363919776 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 99131494631 ps |
| CPU time | 477.91 seconds |
| Started | Sep 24 07:34:35 AM UTC 24 |
| Finished | Sep 24 07:42:38 AM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363919776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3363919776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/28.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_lowpower_counter.2600976734 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 36615732508 ps |
| CPU time | 16.56 seconds |
| Started | Sep 24 07:34:32 AM UTC 24 |
| Finished | Sep 24 07:34:50 AM UTC 24 |
| Peak memory | 210808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600976734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.2600976734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/28.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_poweron_counter.179547082 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 5145141214 ps |
| CPU time | 21.43 seconds |
| Started | Sep 24 07:34:31 AM UTC 24 |
| Finished | Sep 24 07:34:54 AM UTC 24 |
| Peak memory | 210492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179547082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.179547082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/28.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_smoke.2083465858 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 5802308283 ps |
| CPU time | 6.5 seconds |
| Started | Sep 24 07:33:05 AM UTC 24 |
| Finished | Sep 24 07:33:13 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083465858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2083465858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/28.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_stress_all.4284717557 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 336296079874 ps |
| CPU time | 209.5 seconds |
| Started | Sep 24 07:34:50 AM UTC 24 |
| Finished | Sep 24 07:38:23 AM UTC 24 |
| Peak memory | 210772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284717557 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.4284717557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/28.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1151303956 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 5321724051 ps |
| CPU time | 27.41 seconds |
| Started | Sep 24 07:34:40 AM UTC 24 |
| Finished | Sep 24 07:35:09 AM UTC 24 |
| Peak memory | 221092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1151303956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 28.adc_ctrl_stress_all_with_rand_reset.1151303956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/28.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_alert_test.2236679424 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 550910154 ps |
| CPU time | 1.39 seconds |
| Started | Sep 24 07:36:27 AM UTC 24 |
| Finished | Sep 24 07:36:30 AM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236679424 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.2236679424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/29.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_clock_gating.1795185355 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 371882923001 ps |
| CPU time | 711.55 seconds |
| Started | Sep 24 07:35:46 AM UTC 24 |
| Finished | Sep 24 07:47:45 AM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795185355 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gating.1795185355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/29.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_both.474962149 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 335372291639 ps |
| CPU time | 827.44 seconds |
| Started | Sep 24 07:35:53 AM UTC 24 |
| Finished | Sep 24 07:49:49 AM UTC 24 |
| Peak memory | 210716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474962149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.474962149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/29.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_interrupt.967997594 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 497250079797 ps |
| CPU time | 1461.02 seconds |
| Started | Sep 24 07:35:10 AM UTC 24 |
| Finished | Sep 24 07:59:46 AM UTC 24 |
| Peak memory | 213364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967997594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.967997594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/29.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1301260771 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 159400875099 ps |
| CPU time | 465 seconds |
| Started | Sep 24 07:35:24 AM UTC 24 |
| Finished | Sep 24 07:43:14 AM UTC 24 |
| Peak memory | 210768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301260771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt_fixed.1301260771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/29.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_polled.3764489839 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 326003693577 ps |
| CPU time | 494.75 seconds |
| Started | Sep 24 07:34:59 AM UTC 24 |
| Finished | Sep 24 07:43:20 AM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764489839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3764489839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/29.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_polled_fixed.1672252514 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 492437718716 ps |
| CPU time | 1314.39 seconds |
| Started | Sep 24 07:35:09 AM UTC 24 |
| Finished | Sep 24 07:57:16 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672252514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixed.1672252514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/29.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_wakeup.4230648791 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 487019752091 ps |
| CPU time | 689.13 seconds |
| Started | Sep 24 07:35:25 AM UTC 24 |
| Finished | Sep 24 07:47:01 AM UTC 24 |
| Peak memory | 210772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230648791 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_wakeup.4230648791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/29.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_wakeup_fixed.1443592720 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 401987907984 ps |
| CPU time | 327.85 seconds |
| Started | Sep 24 07:35:41 AM UTC 24 |
| Finished | Sep 24 07:41:13 AM UTC 24 |
| Peak memory | 210756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443592720 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_wakeup_fixed.1443592720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/29.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_fsm_reset.1539661515 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 114058633231 ps |
| CPU time | 575.05 seconds |
| Started | Sep 24 07:36:15 AM UTC 24 |
| Finished | Sep 24 07:45:57 AM UTC 24 |
| Peak memory | 211052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539661515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.1539661515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/29.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_lowpower_counter.1663186680 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 26878370964 ps |
| CPU time | 7.74 seconds |
| Started | Sep 24 07:36:12 AM UTC 24 |
| Finished | Sep 24 07:36:21 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663186680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1663186680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/29.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_poweron_counter.1743743841 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 4838471100 ps |
| CPU time | 16.73 seconds |
| Started | Sep 24 07:36:09 AM UTC 24 |
| Finished | Sep 24 07:36:27 AM UTC 24 |
| Peak memory | 210564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743743841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.1743743841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/29.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_smoke.2123312520 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 5999666353 ps |
| CPU time | 25.51 seconds |
| Started | Sep 24 07:34:56 AM UTC 24 |
| Finished | Sep 24 07:35:24 AM UTC 24 |
| Peak memory | 210768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123312520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.2123312520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/29.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.1482729225 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 2018948996 ps |
| CPU time | 3.42 seconds |
| Started | Sep 24 07:36:21 AM UTC 24 |
| Finished | Sep 24 07:36:26 AM UTC 24 |
| Peak memory | 210572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1482729225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 29.adc_ctrl_stress_all_with_rand_reset.1482729225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/29.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_alert_test.3812438562 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 547547431 ps |
| CPU time | 1.43 seconds |
| Started | Sep 24 06:58:57 AM UTC 24 |
| Finished | Sep 24 06:58:59 AM UTC 24 |
| Peak memory | 210376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812438562 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.3812438562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/3.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt.3232970148 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 492630599701 ps |
| CPU time | 1385.13 seconds |
| Started | Sep 24 06:58:43 AM UTC 24 |
| Finished | Sep 24 07:22:02 AM UTC 24 |
| Peak memory | 213396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232970148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.3232970148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/3.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2018878304 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 155210949085 ps |
| CPU time | 364.11 seconds |
| Started | Sep 24 06:58:43 AM UTC 24 |
| Finished | Sep 24 07:04:52 AM UTC 24 |
| Peak memory | 210760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018878304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt_fixed.2018878304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/3.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled.3583208936 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 161585354358 ps |
| CPU time | 186.82 seconds |
| Started | Sep 24 06:58:38 AM UTC 24 |
| Finished | Sep 24 07:01:48 AM UTC 24 |
| Peak memory | 210792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583208936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.3583208936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/3.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled_fixed.2543700448 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 331577805073 ps |
| CPU time | 271.67 seconds |
| Started | Sep 24 06:58:40 AM UTC 24 |
| Finished | Sep 24 07:03:17 AM UTC 24 |
| Peak memory | 210768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543700448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed.2543700448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/3.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup.1835358385 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 173467486055 ps |
| CPU time | 656.45 seconds |
| Started | Sep 24 06:58:44 AM UTC 24 |
| Finished | Sep 24 07:09:48 AM UTC 24 |
| Peak memory | 210768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835358385 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_wakeup.1835358385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/3.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1071899843 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 606133282148 ps |
| CPU time | 1770.86 seconds |
| Started | Sep 24 06:58:44 AM UTC 24 |
| Finished | Sep 24 07:28:32 AM UTC 24 |
| Peak memory | 213336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071899843 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_wakeup_fixed.1071899843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/3.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_lowpower_counter.951747784 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 27703559755 ps |
| CPU time | 32.61 seconds |
| Started | Sep 24 06:58:51 AM UTC 24 |
| Finished | Sep 24 06:59:25 AM UTC 24 |
| Peak memory | 210564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951747784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.951747784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/3.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_poweron_counter.2901077698 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 3848482293 ps |
| CPU time | 4.69 seconds |
| Started | Sep 24 06:58:48 AM UTC 24 |
| Finished | Sep 24 06:58:54 AM UTC 24 |
| Peak memory | 210484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901077698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.2901077698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/3.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_sec_cm.2583989497 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 7874930720 ps |
| CPU time | 10.52 seconds |
| Started | Sep 24 06:58:55 AM UTC 24 |
| Finished | Sep 24 06:59:07 AM UTC 24 |
| Peak memory | 242976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583989497 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.2583989497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/3.adc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_smoke.191537798 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 5902557088 ps |
| CPU time | 12.67 seconds |
| Started | Sep 24 06:58:38 AM UTC 24 |
| Finished | Sep 24 06:58:52 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191537798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.191537798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/3.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all.4018925769 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 175312020799 ps |
| CPU time | 312.49 seconds |
| Started | Sep 24 06:58:54 AM UTC 24 |
| Finished | Sep 24 07:04:11 AM UTC 24 |
| Peak memory | 211036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018925769 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.4018925769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1054374055 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 50881917182 ps |
| CPU time | 60.86 seconds |
| Started | Sep 24 06:58:53 AM UTC 24 |
| Finished | Sep 24 06:59:56 AM UTC 24 |
| Peak memory | 227820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1054374055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 3.adc_ctrl_stress_all_with_rand_reset.1054374055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_alert_test.2586084349 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 521872621 ps |
| CPU time | 1.17 seconds |
| Started | Sep 24 07:38:17 AM UTC 24 |
| Finished | Sep 24 07:38:19 AM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586084349 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2586084349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/30.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_clock_gating.1548385232 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 526013988521 ps |
| CPU time | 696.4 seconds |
| Started | Sep 24 07:37:40 AM UTC 24 |
| Finished | Sep 24 07:49:24 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548385232 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gating.1548385232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/30.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_both.1129271141 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 181920842775 ps |
| CPU time | 135.13 seconds |
| Started | Sep 24 07:37:41 AM UTC 24 |
| Finished | Sep 24 07:39:59 AM UTC 24 |
| Peak memory | 210780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129271141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1129271141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/30.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_interrupt.1469179186 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 333555922588 ps |
| CPU time | 234.9 seconds |
| Started | Sep 24 07:36:56 AM UTC 24 |
| Finished | Sep 24 07:40:54 AM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469179186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.1469179186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/30.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3565620032 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 500274216027 ps |
| CPU time | 1306.63 seconds |
| Started | Sep 24 07:37:10 AM UTC 24 |
| Finished | Sep 24 07:59:09 AM UTC 24 |
| Peak memory | 213400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565620032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt_fixed.3565620032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/30.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_polled.917987196 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 478637501365 ps |
| CPU time | 119.23 seconds |
| Started | Sep 24 07:36:35 AM UTC 24 |
| Finished | Sep 24 07:38:36 AM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917987196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.917987196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/30.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_polled_fixed.2512172011 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 330888882297 ps |
| CPU time | 469.84 seconds |
| Started | Sep 24 07:36:50 AM UTC 24 |
| Finished | Sep 24 07:44:45 AM UTC 24 |
| Peak memory | 210760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512172011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixed.2512172011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/30.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_wakeup.3396252817 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 205596268639 ps |
| CPU time | 142.34 seconds |
| Started | Sep 24 07:37:22 AM UTC 24 |
| Finished | Sep 24 07:39:47 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396252817 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_wakeup.3396252817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/30.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3686602610 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 613781416675 ps |
| CPU time | 230.62 seconds |
| Started | Sep 24 07:37:29 AM UTC 24 |
| Finished | Sep 24 07:41:23 AM UTC 24 |
| Peak memory | 210696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686602610 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_wakeup_fixed.3686602610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/30.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_fsm_reset.3817168567 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 74709546707 ps |
| CPU time | 390.56 seconds |
| Started | Sep 24 07:37:54 AM UTC 24 |
| Finished | Sep 24 07:44:30 AM UTC 24 |
| Peak memory | 211320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817168567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.3817168567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/30.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_lowpower_counter.2383280528 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 33684738848 ps |
| CPU time | 134.61 seconds |
| Started | Sep 24 07:37:52 AM UTC 24 |
| Finished | Sep 24 07:40:09 AM UTC 24 |
| Peak memory | 210480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383280528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2383280528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/30.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_poweron_counter.3914129018 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 3784442349 ps |
| CPU time | 3.47 seconds |
| Started | Sep 24 07:37:47 AM UTC 24 |
| Finished | Sep 24 07:37:52 AM UTC 24 |
| Peak memory | 210488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914129018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3914129018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/30.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_smoke.3006919570 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 5956613120 ps |
| CPU time | 2.46 seconds |
| Started | Sep 24 07:36:30 AM UTC 24 |
| Finished | Sep 24 07:36:34 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006919570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.3006919570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/30.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all.592794191 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 844489177211 ps |
| CPU time | 3419.82 seconds |
| Started | Sep 24 07:38:13 AM UTC 24 |
| Finished | Sep 24 08:35:47 AM UTC 24 |
| Peak memory | 223844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592794191 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all.592794191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/30.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.3300741097 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 60732294198 ps |
| CPU time | 28.4 seconds |
| Started | Sep 24 07:38:11 AM UTC 24 |
| Finished | Sep 24 07:38:41 AM UTC 24 |
| Peak memory | 220996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3300741097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 30.adc_ctrl_stress_all_with_rand_reset.3300741097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/30.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_alert_test.616532709 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 492123335 ps |
| CPU time | 1.91 seconds |
| Started | Sep 24 07:39:48 AM UTC 24 |
| Finished | Sep 24 07:39:51 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616532709 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.616532709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/31.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_both.2955244680 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 326104213177 ps |
| CPU time | 916.38 seconds |
| Started | Sep 24 07:38:48 AM UTC 24 |
| Finished | Sep 24 07:54:14 AM UTC 24 |
| Peak memory | 210784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955244680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2955244680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/31.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_interrupt.3161269049 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 500855718926 ps |
| CPU time | 1545.08 seconds |
| Started | Sep 24 07:38:26 AM UTC 24 |
| Finished | Sep 24 08:04:27 AM UTC 24 |
| Peak memory | 213444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161269049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.3161269049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/31.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2066819328 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 167835472644 ps |
| CPU time | 511.49 seconds |
| Started | Sep 24 07:38:35 AM UTC 24 |
| Finished | Sep 24 07:47:12 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066819328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt_fixed.2066819328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/31.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_polled.2870356949 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 162643733295 ps |
| CPU time | 434.12 seconds |
| Started | Sep 24 07:38:20 AM UTC 24 |
| Finished | Sep 24 07:45:39 AM UTC 24 |
| Peak memory | 210792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870356949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2870356949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/31.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_polled_fixed.2162001792 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 496598327898 ps |
| CPU time | 405.88 seconds |
| Started | Sep 24 07:38:24 AM UTC 24 |
| Finished | Sep 24 07:45:15 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162001792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixed.2162001792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/31.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_wakeup.4215245021 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 354896204314 ps |
| CPU time | 196.47 seconds |
| Started | Sep 24 07:38:37 AM UTC 24 |
| Finished | Sep 24 07:41:56 AM UTC 24 |
| Peak memory | 210844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215245021 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_wakeup.4215245021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/31.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3396311703 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 398848299634 ps |
| CPU time | 378.18 seconds |
| Started | Sep 24 07:38:41 AM UTC 24 |
| Finished | Sep 24 07:45:04 AM UTC 24 |
| Peak memory | 210748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396311703 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_wakeup_fixed.3396311703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/31.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_lowpower_counter.1153298627 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 26283645590 ps |
| CPU time | 29.83 seconds |
| Started | Sep 24 07:39:26 AM UTC 24 |
| Finished | Sep 24 07:39:57 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153298627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.1153298627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/31.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_poweron_counter.1929831762 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 3964753365 ps |
| CPU time | 9.06 seconds |
| Started | Sep 24 07:39:16 AM UTC 24 |
| Finished | Sep 24 07:39:27 AM UTC 24 |
| Peak memory | 210484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929831762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.1929831762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/31.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_smoke.1857384527 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 5833868636 ps |
| CPU time | 14.23 seconds |
| Started | Sep 24 07:38:19 AM UTC 24 |
| Finished | Sep 24 07:38:34 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857384527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.1857384527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/31.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_alert_test.3663019854 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 319271654 ps |
| CPU time | 1.56 seconds |
| Started | Sep 24 07:41:18 AM UTC 24 |
| Finished | Sep 24 07:41:21 AM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663019854 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3663019854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/32.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_clock_gating.2061320977 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 497635324960 ps |
| CPU time | 1395.61 seconds |
| Started | Sep 24 07:40:33 AM UTC 24 |
| Finished | Sep 24 08:04:03 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061320977 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gating.2061320977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/32.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_both.2049108872 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 553509066158 ps |
| CPU time | 1044.36 seconds |
| Started | Sep 24 07:40:42 AM UTC 24 |
| Finished | Sep 24 07:58:17 AM UTC 24 |
| Peak memory | 213440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049108872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2049108872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/32.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_interrupt_fixed.122265976 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 326873884265 ps |
| CPU time | 882.43 seconds |
| Started | Sep 24 07:40:08 AM UTC 24 |
| Finished | Sep 24 07:55:00 AM UTC 24 |
| Peak memory | 210784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122265976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt_fixed.122265976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/32.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_polled.3291394559 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 491188086232 ps |
| CPU time | 352.15 seconds |
| Started | Sep 24 07:39:58 AM UTC 24 |
| Finished | Sep 24 07:45:54 AM UTC 24 |
| Peak memory | 210780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291394559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.3291394559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/32.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_polled_fixed.2626764259 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 489446055503 ps |
| CPU time | 274 seconds |
| Started | Sep 24 07:39:59 AM UTC 24 |
| Finished | Sep 24 07:44:37 AM UTC 24 |
| Peak memory | 210764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626764259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixed.2626764259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/32.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_wakeup.496925538 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 170299166751 ps |
| CPU time | 103.26 seconds |
| Started | Sep 24 07:40:10 AM UTC 24 |
| Finished | Sep 24 07:41:55 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496925538 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_wakeup.496925538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/32.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_wakeup_fixed.2969211874 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 199070481977 ps |
| CPU time | 392.34 seconds |
| Started | Sep 24 07:40:20 AM UTC 24 |
| Finished | Sep 24 07:46:58 AM UTC 24 |
| Peak memory | 210832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969211874 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_wakeup_fixed.2969211874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/32.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_lowpower_counter.2811564828 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 36004813388 ps |
| CPU time | 44.33 seconds |
| Started | Sep 24 07:40:52 AM UTC 24 |
| Finished | Sep 24 07:41:37 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811564828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.2811564828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/32.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_poweron_counter.2297947259 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 3314362384 ps |
| CPU time | 11.59 seconds |
| Started | Sep 24 07:40:46 AM UTC 24 |
| Finished | Sep 24 07:40:58 AM UTC 24 |
| Peak memory | 210488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297947259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.2297947259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/32.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_smoke.2046856465 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 5678784906 ps |
| CPU time | 12.94 seconds |
| Started | Sep 24 07:39:52 AM UTC 24 |
| Finished | Sep 24 07:40:06 AM UTC 24 |
| Peak memory | 210768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046856465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2046856465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/32.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1180133095 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 6563109657 ps |
| CPU time | 16.87 seconds |
| Started | Sep 24 07:40:59 AM UTC 24 |
| Finished | Sep 24 07:41:17 AM UTC 24 |
| Peak memory | 221392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1180133095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 32.adc_ctrl_stress_all_with_rand_reset.1180133095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/32.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_alert_test.779239683 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 508333347 ps |
| CPU time | 1.04 seconds |
| Started | Sep 24 07:42:39 AM UTC 24 |
| Finished | Sep 24 07:42:41 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779239683 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.779239683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/33.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_clock_gating.2892188086 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 355495753973 ps |
| CPU time | 467.54 seconds |
| Started | Sep 24 07:42:04 AM UTC 24 |
| Finished | Sep 24 07:49:56 AM UTC 24 |
| Peak memory | 210772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892188086 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gating.2892188086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/33.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_interrupt.3597916796 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 163683786932 ps |
| CPU time | 294.55 seconds |
| Started | Sep 24 07:41:38 AM UTC 24 |
| Finished | Sep 24 07:46:37 AM UTC 24 |
| Peak memory | 210792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597916796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.3597916796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/33.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_interrupt_fixed.2817672791 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 335279101015 ps |
| CPU time | 424.25 seconds |
| Started | Sep 24 07:41:49 AM UTC 24 |
| Finished | Sep 24 07:48:59 AM UTC 24 |
| Peak memory | 210688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817672791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt_fixed.2817672791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/33.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_polled.1462863794 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 166958887045 ps |
| CPU time | 109.93 seconds |
| Started | Sep 24 07:41:23 AM UTC 24 |
| Finished | Sep 24 07:43:15 AM UTC 24 |
| Peak memory | 210792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462863794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1462863794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/33.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_polled_fixed.3677697458 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 161455362338 ps |
| CPU time | 103.67 seconds |
| Started | Sep 24 07:41:28 AM UTC 24 |
| Finished | Sep 24 07:43:14 AM UTC 24 |
| Peak memory | 210768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677697458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixed.3677697458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/33.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_wakeup.1290737453 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 358695951515 ps |
| CPU time | 828.04 seconds |
| Started | Sep 24 07:41:56 AM UTC 24 |
| Finished | Sep 24 07:55:53 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290737453 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_wakeup.1290737453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/33.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1672575532 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 195208204200 ps |
| CPU time | 122.78 seconds |
| Started | Sep 24 07:41:57 AM UTC 24 |
| Finished | Sep 24 07:44:02 AM UTC 24 |
| Peak memory | 210756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672575532 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_wakeup_fixed.1672575532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/33.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_fsm_reset.4030515485 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 110306825017 ps |
| CPU time | 593.84 seconds |
| Started | Sep 24 07:42:20 AM UTC 24 |
| Finished | Sep 24 07:52:20 AM UTC 24 |
| Peak memory | 211188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030515485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.4030515485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/33.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_lowpower_counter.3706412645 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 44161808501 ps |
| CPU time | 45.31 seconds |
| Started | Sep 24 07:42:14 AM UTC 24 |
| Finished | Sep 24 07:43:01 AM UTC 24 |
| Peak memory | 210828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706412645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3706412645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/33.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_poweron_counter.1441802941 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 4423658616 ps |
| CPU time | 5.25 seconds |
| Started | Sep 24 07:42:07 AM UTC 24 |
| Finished | Sep 24 07:42:13 AM UTC 24 |
| Peak memory | 210568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441802941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1441802941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/33.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_smoke.539354439 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 5998792797 ps |
| CPU time | 4.82 seconds |
| Started | Sep 24 07:41:21 AM UTC 24 |
| Finished | Sep 24 07:41:27 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539354439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.539354439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/33.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.2389253502 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 17438004291 ps |
| CPU time | 43.09 seconds |
| Started | Sep 24 07:42:25 AM UTC 24 |
| Finished | Sep 24 07:43:10 AM UTC 24 |
| Peak memory | 221416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2389253502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 33.adc_ctrl_stress_all_with_rand_reset.2389253502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/33.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_alert_test.2667037212 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 466335361 ps |
| CPU time | 1.33 seconds |
| Started | Sep 24 07:44:09 AM UTC 24 |
| Finished | Sep 24 07:44:11 AM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667037212 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.2667037212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/34.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_both.247623551 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 337279230487 ps |
| CPU time | 909.06 seconds |
| Started | Sep 24 07:43:15 AM UTC 24 |
| Finished | Sep 24 07:58:33 AM UTC 24 |
| Peak memory | 210776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247623551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.247623551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/34.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_interrupt.3616516114 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 332783007425 ps |
| CPU time | 93.77 seconds |
| Started | Sep 24 07:42:51 AM UTC 24 |
| Finished | Sep 24 07:44:27 AM UTC 24 |
| Peak memory | 210720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616516114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.3616516114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/34.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3599483380 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 486794301959 ps |
| CPU time | 212.43 seconds |
| Started | Sep 24 07:43:01 AM UTC 24 |
| Finished | Sep 24 07:46:37 AM UTC 24 |
| Peak memory | 210852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599483380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt_fixed.3599483380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/34.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_polled.743220903 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 493628048496 ps |
| CPU time | 353 seconds |
| Started | Sep 24 07:42:42 AM UTC 24 |
| Finished | Sep 24 07:48:40 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743220903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.743220903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/34.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_polled_fixed.2920356539 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 497926065373 ps |
| CPU time | 1407.85 seconds |
| Started | Sep 24 07:42:46 AM UTC 24 |
| Finished | Sep 24 08:06:29 AM UTC 24 |
| Peak memory | 213352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920356539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixed.2920356539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/34.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_wakeup.2188842913 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 517459220918 ps |
| CPU time | 1335.25 seconds |
| Started | Sep 24 07:43:01 AM UTC 24 |
| Finished | Sep 24 08:05:29 AM UTC 24 |
| Peak memory | 213364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188842913 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_wakeup.2188842913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/34.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_wakeup_fixed.2320157102 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 588719772386 ps |
| CPU time | 938.31 seconds |
| Started | Sep 24 07:43:11 AM UTC 24 |
| Finished | Sep 24 07:58:59 AM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320157102 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_wakeup_fixed.2320157102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/34.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_fsm_reset.3743084152 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 87583226416 ps |
| CPU time | 504.42 seconds |
| Started | Sep 24 07:43:28 AM UTC 24 |
| Finished | Sep 24 07:51:58 AM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743084152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3743084152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/34.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_lowpower_counter.3952816036 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 21234102861 ps |
| CPU time | 81.75 seconds |
| Started | Sep 24 07:43:21 AM UTC 24 |
| Finished | Sep 24 07:44:45 AM UTC 24 |
| Peak memory | 210572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952816036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3952816036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/34.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_poweron_counter.754543759 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 4799733901 ps |
| CPU time | 10.49 seconds |
| Started | Sep 24 07:43:16 AM UTC 24 |
| Finished | Sep 24 07:43:27 AM UTC 24 |
| Peak memory | 210508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754543759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.754543759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/34.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_smoke.1028226087 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 5867187796 ps |
| CPU time | 4.06 seconds |
| Started | Sep 24 07:42:40 AM UTC 24 |
| Finished | Sep 24 07:42:45 AM UTC 24 |
| Peak memory | 210768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028226087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.1028226087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/34.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_stress_all.1522062394 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 476634023590 ps |
| CPU time | 1398.13 seconds |
| Started | Sep 24 07:44:02 AM UTC 24 |
| Finished | Sep 24 08:07:36 AM UTC 24 |
| Peak memory | 223936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522062394 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.1522062394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/34.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.173354751 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 4409721411 ps |
| CPU time | 7.61 seconds |
| Started | Sep 24 07:44:00 AM UTC 24 |
| Finished | Sep 24 07:44:09 AM UTC 24 |
| Peak memory | 210628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=173354751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.173354751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/34.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_alert_test.2954617815 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 486749452 ps |
| CPU time | 1.86 seconds |
| Started | Sep 24 07:45:55 AM UTC 24 |
| Finished | Sep 24 07:45:58 AM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954617815 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2954617815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/35.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_clock_gating.2214342637 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 335057559435 ps |
| CPU time | 286.17 seconds |
| Started | Sep 24 07:45:05 AM UTC 24 |
| Finished | Sep 24 07:49:55 AM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214342637 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gating.2214342637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/35.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_both.718259016 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 162986603439 ps |
| CPU time | 128.07 seconds |
| Started | Sep 24 07:45:16 AM UTC 24 |
| Finished | Sep 24 07:47:26 AM UTC 24 |
| Peak memory | 210856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718259016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.718259016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/35.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_interrupt.466128829 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 333227977228 ps |
| CPU time | 330.77 seconds |
| Started | Sep 24 07:44:30 AM UTC 24 |
| Finished | Sep 24 07:50:05 AM UTC 24 |
| Peak memory | 210856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466128829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.466128829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/35.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1953276846 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 330148603887 ps |
| CPU time | 203.96 seconds |
| Started | Sep 24 07:44:38 AM UTC 24 |
| Finished | Sep 24 07:48:04 AM UTC 24 |
| Peak memory | 210756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953276846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt_fixed.1953276846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/35.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_polled.1306293978 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 164647895883 ps |
| CPU time | 59.85 seconds |
| Started | Sep 24 07:44:28 AM UTC 24 |
| Finished | Sep 24 07:45:30 AM UTC 24 |
| Peak memory | 209904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306293978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.1306293978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/35.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_polled_fixed.905570508 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 319783465261 ps |
| CPU time | 128.34 seconds |
| Started | Sep 24 07:44:28 AM UTC 24 |
| Finished | Sep 24 07:46:39 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905570508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixed.905570508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/35.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_wakeup.2018959859 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 527796794896 ps |
| CPU time | 679.5 seconds |
| Started | Sep 24 07:44:46 AM UTC 24 |
| Finished | Sep 24 07:56:12 AM UTC 24 |
| Peak memory | 210772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018959859 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_wakeup.2018959859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/35.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_wakeup_fixed.3851768335 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 589325655737 ps |
| CPU time | 371.71 seconds |
| Started | Sep 24 07:44:46 AM UTC 24 |
| Finished | Sep 24 07:51:02 AM UTC 24 |
| Peak memory | 210696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851768335 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_wakeup_fixed.3851768335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/35.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_fsm_reset.1120779286 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 72291074549 ps |
| CPU time | 446.62 seconds |
| Started | Sep 24 07:45:40 AM UTC 24 |
| Finished | Sep 24 07:53:12 AM UTC 24 |
| Peak memory | 211192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120779286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.1120779286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/35.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_lowpower_counter.1945843012 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 35230990368 ps |
| CPU time | 12.75 seconds |
| Started | Sep 24 07:45:36 AM UTC 24 |
| Finished | Sep 24 07:45:50 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945843012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.1945843012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/35.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_poweron_counter.1396753217 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 2864814128 ps |
| CPU time | 3.66 seconds |
| Started | Sep 24 07:45:31 AM UTC 24 |
| Finished | Sep 24 07:45:36 AM UTC 24 |
| Peak memory | 210740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396753217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.1396753217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/35.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_smoke.4116824541 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 5780328565 ps |
| CPU time | 14.03 seconds |
| Started | Sep 24 07:44:12 AM UTC 24 |
| Finished | Sep 24 07:44:27 AM UTC 24 |
| Peak memory | 210768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116824541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.4116824541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/35.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_stress_all.2219886601 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 498217073809 ps |
| CPU time | 1218.77 seconds |
| Started | Sep 24 07:45:50 AM UTC 24 |
| Finished | Sep 24 08:06:21 AM UTC 24 |
| Peak memory | 213448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219886601 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.2219886601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/35.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.1126528011 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9224094562 ps |
| CPU time | 25 seconds |
| Started | Sep 24 07:45:44 AM UTC 24 |
| Finished | Sep 24 07:46:10 AM UTC 24 |
| Peak memory | 227548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1126528011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 35.adc_ctrl_stress_all_with_rand_reset.1126528011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/35.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_alert_test.2401599466 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 489516627 ps |
| CPU time | 1.86 seconds |
| Started | Sep 24 07:47:44 AM UTC 24 |
| Finished | Sep 24 07:47:47 AM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401599466 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2401599466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/36.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_clock_gating.1392162270 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 321192409232 ps |
| CPU time | 135.98 seconds |
| Started | Sep 24 07:46:52 AM UTC 24 |
| Finished | Sep 24 07:49:10 AM UTC 24 |
| Peak memory | 210772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392162270 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gating.1392162270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/36.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_both.2069759705 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 171456628978 ps |
| CPU time | 293.67 seconds |
| Started | Sep 24 07:46:59 AM UTC 24 |
| Finished | Sep 24 07:51:57 AM UTC 24 |
| Peak memory | 210720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069759705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2069759705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/36.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_interrupt_fixed.1818371936 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 330359450024 ps |
| CPU time | 470.03 seconds |
| Started | Sep 24 07:46:38 AM UTC 24 |
| Finished | Sep 24 07:54:33 AM UTC 24 |
| Peak memory | 210828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818371936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt_fixed.1818371936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/36.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_polled.321698005 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 161030695032 ps |
| CPU time | 137.72 seconds |
| Started | Sep 24 07:45:59 AM UTC 24 |
| Finished | Sep 24 07:48:19 AM UTC 24 |
| Peak memory | 210784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321698005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.321698005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/36.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_polled_fixed.2910590453 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 166044943373 ps |
| CPU time | 575.99 seconds |
| Started | Sep 24 07:46:04 AM UTC 24 |
| Finished | Sep 24 07:55:47 AM UTC 24 |
| Peak memory | 210748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910590453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixed.2910590453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/36.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_wakeup.1273153995 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 521784041891 ps |
| CPU time | 420.31 seconds |
| Started | Sep 24 07:46:38 AM UTC 24 |
| Finished | Sep 24 07:53:44 AM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273153995 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_wakeup.1273153995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/36.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2860700072 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 202421645562 ps |
| CPU time | 690.22 seconds |
| Started | Sep 24 07:46:40 AM UTC 24 |
| Finished | Sep 24 07:58:18 AM UTC 24 |
| Peak memory | 210756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860700072 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_wakeup_fixed.2860700072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/36.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_fsm_reset.412298067 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 86415354295 ps |
| CPU time | 510 seconds |
| Started | Sep 24 07:47:16 AM UTC 24 |
| Finished | Sep 24 07:55:52 AM UTC 24 |
| Peak memory | 211052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412298067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.412298067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/36.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_lowpower_counter.4094377960 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 23445908200 ps |
| CPU time | 53.03 seconds |
| Started | Sep 24 07:47:13 AM UTC 24 |
| Finished | Sep 24 07:48:08 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094377960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.4094377960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/36.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_poweron_counter.1459567800 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 3962076989 ps |
| CPU time | 17.06 seconds |
| Started | Sep 24 07:47:02 AM UTC 24 |
| Finished | Sep 24 07:47:20 AM UTC 24 |
| Peak memory | 210496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459567800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.1459567800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/36.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_smoke.1958050196 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 6041175951 ps |
| CPU time | 4.53 seconds |
| Started | Sep 24 07:45:58 AM UTC 24 |
| Finished | Sep 24 07:46:04 AM UTC 24 |
| Peak memory | 210576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958050196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.1958050196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/36.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_stress_all.133855132 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 180043316478 ps |
| CPU time | 513.49 seconds |
| Started | Sep 24 07:47:27 AM UTC 24 |
| Finished | Sep 24 07:56:07 AM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133855132 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.133855132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/36.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.1895452549 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 12387267683 ps |
| CPU time | 22.86 seconds |
| Started | Sep 24 07:47:21 AM UTC 24 |
| Finished | Sep 24 07:47:45 AM UTC 24 |
| Peak memory | 221196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1895452549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 36.adc_ctrl_stress_all_with_rand_reset.1895452549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/36.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_alert_test.2540444023 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 310933974 ps |
| CPU time | 2.13 seconds |
| Started | Sep 24 07:48:45 AM UTC 24 |
| Finished | Sep 24 07:48:48 AM UTC 24 |
| Peak memory | 210364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540444023 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.2540444023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/37.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_both.1774439819 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 332701172811 ps |
| CPU time | 209.2 seconds |
| Started | Sep 24 07:48:11 AM UTC 24 |
| Finished | Sep 24 07:51:43 AM UTC 24 |
| Peak memory | 210720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774439819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.1774439819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/37.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_interrupt.1486554123 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 492622258255 ps |
| CPU time | 1493.16 seconds |
| Started | Sep 24 07:47:52 AM UTC 24 |
| Finished | Sep 24 08:13:00 AM UTC 24 |
| Peak memory | 213504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486554123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1486554123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/37.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2887718553 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 163760744747 ps |
| CPU time | 429.17 seconds |
| Started | Sep 24 07:47:52 AM UTC 24 |
| Finished | Sep 24 07:55:06 AM UTC 24 |
| Peak memory | 211020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887718553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt_fixed.2887718553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/37.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_polled.2951587075 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 496142208977 ps |
| CPU time | 334.64 seconds |
| Started | Sep 24 07:47:47 AM UTC 24 |
| Finished | Sep 24 07:53:25 AM UTC 24 |
| Peak memory | 210780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951587075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2951587075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/37.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_polled_fixed.3728448315 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 493414370987 ps |
| CPU time | 331.24 seconds |
| Started | Sep 24 07:47:48 AM UTC 24 |
| Finished | Sep 24 07:53:23 AM UTC 24 |
| Peak memory | 210760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728448315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixed.3728448315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/37.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_wakeup.95194514 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 525551767631 ps |
| CPU time | 752.39 seconds |
| Started | Sep 24 07:47:54 AM UTC 24 |
| Finished | Sep 24 08:00:34 AM UTC 24 |
| Peak memory | 211032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95194514 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_wakeup.95194514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/37.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_wakeup_fixed.361933371 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 194261207643 ps |
| CPU time | 454.52 seconds |
| Started | Sep 24 07:48:05 AM UTC 24 |
| Finished | Sep 24 07:55:45 AM UTC 24 |
| Peak memory | 210716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361933371 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_wakeup_fixed.361933371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/37.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_fsm_reset.2211703879 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 108488306589 ps |
| CPU time | 671.74 seconds |
| Started | Sep 24 07:48:26 AM UTC 24 |
| Finished | Sep 24 07:59:45 AM UTC 24 |
| Peak memory | 211188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211703879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2211703879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/37.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_lowpower_counter.1670594789 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 37042566442 ps |
| CPU time | 54.55 seconds |
| Started | Sep 24 07:48:25 AM UTC 24 |
| Finished | Sep 24 07:49:21 AM UTC 24 |
| Peak memory | 210552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670594789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1670594789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/37.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_poweron_counter.2799096079 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 3761897561 ps |
| CPU time | 3.36 seconds |
| Started | Sep 24 07:48:20 AM UTC 24 |
| Finished | Sep 24 07:48:25 AM UTC 24 |
| Peak memory | 210760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799096079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.2799096079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/37.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_smoke.3338283302 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 6130970557 ps |
| CPU time | 5.29 seconds |
| Started | Sep 24 07:47:47 AM UTC 24 |
| Finished | Sep 24 07:47:53 AM UTC 24 |
| Peak memory | 210832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338283302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.3338283302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/37.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_stress_all.2492175063 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 386343485073 ps |
| CPU time | 198.68 seconds |
| Started | Sep 24 07:48:40 AM UTC 24 |
| Finished | Sep 24 07:52:03 AM UTC 24 |
| Peak memory | 210708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492175063 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.2492175063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/37.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.3186717123 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 9043960664 ps |
| CPU time | 25.49 seconds |
| Started | Sep 24 07:48:29 AM UTC 24 |
| Finished | Sep 24 07:48:56 AM UTC 24 |
| Peak memory | 221336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3186717123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 37.adc_ctrl_stress_all_with_rand_reset.3186717123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/37.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_alert_test.2178711386 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 459865665 ps |
| CPU time | 1.38 seconds |
| Started | Sep 24 07:50:40 AM UTC 24 |
| Finished | Sep 24 07:50:42 AM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178711386 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.2178711386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/38.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_clock_gating.3613815752 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 166747895238 ps |
| CPU time | 45.51 seconds |
| Started | Sep 24 07:49:50 AM UTC 24 |
| Finished | Sep 24 07:50:37 AM UTC 24 |
| Peak memory | 211036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613815752 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gating.3613815752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/38.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_both.3516334177 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 570351389216 ps |
| CPU time | 1565.63 seconds |
| Started | Sep 24 07:49:55 AM UTC 24 |
| Finished | Sep 24 08:16:17 AM UTC 24 |
| Peak memory | 213708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516334177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.3516334177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/38.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_interrupt.2868880262 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 168583201527 ps |
| CPU time | 415.17 seconds |
| Started | Sep 24 07:49:00 AM UTC 24 |
| Finished | Sep 24 07:56:00 AM UTC 24 |
| Peak memory | 210780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868880262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2868880262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/38.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_interrupt_fixed.3249653451 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 492950111245 ps |
| CPU time | 377.6 seconds |
| Started | Sep 24 07:49:11 AM UTC 24 |
| Finished | Sep 24 07:55:33 AM UTC 24 |
| Peak memory | 210748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249653451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt_fixed.3249653451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/38.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_polled.2357033486 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 161901397204 ps |
| CPU time | 540.37 seconds |
| Started | Sep 24 07:48:57 AM UTC 24 |
| Finished | Sep 24 07:58:03 AM UTC 24 |
| Peak memory | 210792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357033486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.2357033486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/38.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_polled_fixed.2674549857 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 156962107843 ps |
| CPU time | 177.84 seconds |
| Started | Sep 24 07:48:58 AM UTC 24 |
| Finished | Sep 24 07:51:58 AM UTC 24 |
| Peak memory | 210760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674549857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fixed.2674549857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/38.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_wakeup.4264581077 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 391731635562 ps |
| CPU time | 452.96 seconds |
| Started | Sep 24 07:49:22 AM UTC 24 |
| Finished | Sep 24 07:57:00 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264581077 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_wakeup.4264581077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/38.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2562978718 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 408871652530 ps |
| CPU time | 139.53 seconds |
| Started | Sep 24 07:49:25 AM UTC 24 |
| Finished | Sep 24 07:51:47 AM UTC 24 |
| Peak memory | 210756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562978718 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_wakeup_fixed.2562978718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/38.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_fsm_reset.2345101145 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 73917207882 ps |
| CPU time | 478.6 seconds |
| Started | Sep 24 07:50:04 AM UTC 24 |
| Finished | Sep 24 07:58:08 AM UTC 24 |
| Peak memory | 211076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345101145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.2345101145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/38.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_lowpower_counter.306915895 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 27299275683 ps |
| CPU time | 77.9 seconds |
| Started | Sep 24 07:50:03 AM UTC 24 |
| Finished | Sep 24 07:51:23 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306915895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.306915895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/38.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_poweron_counter.3664736517 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 4303514349 ps |
| CPU time | 5.84 seconds |
| Started | Sep 24 07:49:57 AM UTC 24 |
| Finished | Sep 24 07:50:04 AM UTC 24 |
| Peak memory | 210568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664736517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3664736517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/38.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_smoke.2376022803 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 5872590936 ps |
| CPU time | 7.17 seconds |
| Started | Sep 24 07:48:49 AM UTC 24 |
| Finished | Sep 24 07:48:57 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376022803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.2376022803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/38.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_stress_all.165868410 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 35774247617 ps |
| CPU time | 47.73 seconds |
| Started | Sep 24 07:50:38 AM UTC 24 |
| Finished | Sep 24 07:51:27 AM UTC 24 |
| Peak memory | 210492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165868410 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.165868410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/38.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.4125835010 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 6196935114 ps |
| CPU time | 31.4 seconds |
| Started | Sep 24 07:50:06 AM UTC 24 |
| Finished | Sep 24 07:50:39 AM UTC 24 |
| Peak memory | 221408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4125835010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 38.adc_ctrl_stress_all_with_rand_reset.4125835010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/38.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_alert_test.1634628358 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 289943134 ps |
| CPU time | 1.46 seconds |
| Started | Sep 24 07:51:59 AM UTC 24 |
| Finished | Sep 24 07:52:01 AM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634628358 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.1634628358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/39.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_clock_gating.2634871768 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 177418223258 ps |
| CPU time | 111.72 seconds |
| Started | Sep 24 07:51:43 AM UTC 24 |
| Finished | Sep 24 07:53:37 AM UTC 24 |
| Peak memory | 210688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634871768 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gating.2634871768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/39.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_both.4024412688 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 358851412712 ps |
| CPU time | 1100.86 seconds |
| Started | Sep 24 07:51:44 AM UTC 24 |
| Finished | Sep 24 08:10:17 AM UTC 24 |
| Peak memory | 213680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024412688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.4024412688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/39.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_interrupt.445891235 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 170517472751 ps |
| CPU time | 168.1 seconds |
| Started | Sep 24 07:51:24 AM UTC 24 |
| Finished | Sep 24 07:54:15 AM UTC 24 |
| Peak memory | 210716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445891235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.445891235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/39.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_interrupt_fixed.1028208895 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 332493628816 ps |
| CPU time | 750.52 seconds |
| Started | Sep 24 07:51:28 AM UTC 24 |
| Finished | Sep 24 08:04:06 AM UTC 24 |
| Peak memory | 213504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028208895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt_fixed.1028208895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/39.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_polled.2389807116 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 488770558338 ps |
| CPU time | 304.74 seconds |
| Started | Sep 24 07:51:02 AM UTC 24 |
| Finished | Sep 24 07:56:10 AM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389807116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.2389807116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/39.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_polled_fixed.1944697257 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 165728264907 ps |
| CPU time | 529.05 seconds |
| Started | Sep 24 07:51:03 AM UTC 24 |
| Finished | Sep 24 07:59:58 AM UTC 24 |
| Peak memory | 210676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944697257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixed.1944697257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/39.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_wakeup.2674785586 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 555889664527 ps |
| CPU time | 339.07 seconds |
| Started | Sep 24 07:51:31 AM UTC 24 |
| Finished | Sep 24 07:57:15 AM UTC 24 |
| Peak memory | 211060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674785586 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_wakeup.2674785586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/39.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_wakeup_fixed.3971541213 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 401706172125 ps |
| CPU time | 592.75 seconds |
| Started | Sep 24 07:51:42 AM UTC 24 |
| Finished | Sep 24 08:01:42 AM UTC 24 |
| Peak memory | 210696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971541213 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_wakeup_fixed.3971541213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/39.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_fsm_reset.594234502 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 125871675737 ps |
| CPU time | 837.38 seconds |
| Started | Sep 24 07:51:54 AM UTC 24 |
| Finished | Sep 24 08:05:59 AM UTC 24 |
| Peak memory | 213708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594234502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.594234502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/39.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_lowpower_counter.1110128037 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 33057824905 ps |
| CPU time | 128.46 seconds |
| Started | Sep 24 07:51:48 AM UTC 24 |
| Finished | Sep 24 07:53:58 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110128037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.1110128037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/39.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_poweron_counter.2060627565 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 3601286824 ps |
| CPU time | 5.87 seconds |
| Started | Sep 24 07:51:45 AM UTC 24 |
| Finished | Sep 24 07:51:52 AM UTC 24 |
| Peak memory | 210548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060627565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2060627565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/39.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_smoke.3278143544 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 5988913026 ps |
| CPU time | 17.33 seconds |
| Started | Sep 24 07:50:43 AM UTC 24 |
| Finished | Sep 24 07:51:01 AM UTC 24 |
| Peak memory | 210576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278143544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3278143544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/39.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_stress_all.4113541907 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 474750835485 ps |
| CPU time | 924.97 seconds |
| Started | Sep 24 07:51:58 AM UTC 24 |
| Finished | Sep 24 08:07:31 AM UTC 24 |
| Peak memory | 213496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113541907 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.4113541907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/39.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.2027451134 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 1687543681 ps |
| CPU time | 6.63 seconds |
| Started | Sep 24 07:51:58 AM UTC 24 |
| Finished | Sep 24 07:52:05 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2027451134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 39.adc_ctrl_stress_all_with_rand_reset.2027451134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/39.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_alert_test.1305855302 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 532376448 ps |
| CPU time | 1.23 seconds |
| Started | Sep 24 06:59:57 AM UTC 24 |
| Finished | Sep 24 06:59:59 AM UTC 24 |
| Peak memory | 210376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305855302 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1305855302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/4.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_clock_gating.3525605240 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 166335000923 ps |
| CPU time | 310.54 seconds |
| Started | Sep 24 06:59:21 AM UTC 24 |
| Finished | Sep 24 07:04:36 AM UTC 24 |
| Peak memory | 210844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525605240 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gating.3525605240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/4.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_both.1144069743 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 341931760329 ps |
| CPU time | 1117.83 seconds |
| Started | Sep 24 06:59:26 AM UTC 24 |
| Finished | Sep 24 07:18:16 AM UTC 24 |
| Peak memory | 213528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144069743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.1144069743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/4.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt.2032026933 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 323249891008 ps |
| CPU time | 895.42 seconds |
| Started | Sep 24 06:59:08 AM UTC 24 |
| Finished | Sep 24 07:14:12 AM UTC 24 |
| Peak memory | 213432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032026933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.2032026933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/4.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt_fixed.571982881 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 489990304751 ps |
| CPU time | 671.76 seconds |
| Started | Sep 24 06:59:08 AM UTC 24 |
| Finished | Sep 24 07:10:28 AM UTC 24 |
| Peak memory | 210872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571982881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt_fixed.571982881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/4.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled.2912568949 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 323410486382 ps |
| CPU time | 201.72 seconds |
| Started | Sep 24 06:59:00 AM UTC 24 |
| Finished | Sep 24 07:02:25 AM UTC 24 |
| Peak memory | 210816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912568949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.2912568949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/4.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled_fixed.3877576599 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 168098939983 ps |
| CPU time | 53.62 seconds |
| Started | Sep 24 06:59:00 AM UTC 24 |
| Finished | Sep 24 06:59:55 AM UTC 24 |
| Peak memory | 210768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877576599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed.3877576599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/4.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup.3251496840 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 173548893983 ps |
| CPU time | 468.97 seconds |
| Started | Sep 24 06:59:13 AM UTC 24 |
| Finished | Sep 24 07:07:07 AM UTC 24 |
| Peak memory | 210708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251496840 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_wakeup.3251496840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/4.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup_fixed.1236156561 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 189931209783 ps |
| CPU time | 596.72 seconds |
| Started | Sep 24 06:59:20 AM UTC 24 |
| Finished | Sep 24 07:09:23 AM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236156561 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_wakeup_fixed.1236156561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/4.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_fsm_reset.1876884738 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 75627613027 ps |
| CPU time | 345.19 seconds |
| Started | Sep 24 06:59:35 AM UTC 24 |
| Finished | Sep 24 07:05:24 AM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876884738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.1876884738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/4.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_lowpower_counter.1180618143 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 27754060323 ps |
| CPU time | 30.84 seconds |
| Started | Sep 24 06:59:32 AM UTC 24 |
| Finished | Sep 24 07:00:05 AM UTC 24 |
| Peak memory | 210496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180618143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1180618143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/4.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_poweron_counter.153206781 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 3784808460 ps |
| CPU time | 16.67 seconds |
| Started | Sep 24 06:59:30 AM UTC 24 |
| Finished | Sep 24 06:59:48 AM UTC 24 |
| Peak memory | 210824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153206781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.153206781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/4.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_sec_cm.1715574442 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 7936752176 ps |
| CPU time | 9.46 seconds |
| Started | Sep 24 06:59:56 AM UTC 24 |
| Finished | Sep 24 07:00:06 AM UTC 24 |
| Peak memory | 242912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715574442 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.1715574442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/4.adc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_smoke.2925403378 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 5596298243 ps |
| CPU time | 9.3 seconds |
| Started | Sep 24 06:58:57 AM UTC 24 |
| Finished | Sep 24 06:59:07 AM UTC 24 |
| Peak memory | 210580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925403378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2925403378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/4.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all.12990807 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 76996423149 ps |
| CPU time | 293.63 seconds |
| Started | Sep 24 06:59:55 AM UTC 24 |
| Finished | Sep 24 07:04:52 AM UTC 24 |
| Peak memory | 211076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12990807 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.12990807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2810579121 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 7019331354 ps |
| CPU time | 7.58 seconds |
| Started | Sep 24 06:59:49 AM UTC 24 |
| Finished | Sep 24 06:59:57 AM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2810579121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 4.adc_ctrl_stress_all_with_rand_reset.2810579121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_alert_test.2724541732 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 361539540 ps |
| CPU time | 2.37 seconds |
| Started | Sep 24 07:53:59 AM UTC 24 |
| Finished | Sep 24 07:54:02 AM UTC 24 |
| Peak memory | 210640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724541732 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2724541732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/40.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_clock_gating.2494103940 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 179876405287 ps |
| CPU time | 10.38 seconds |
| Started | Sep 24 07:53:24 AM UTC 24 |
| Finished | Sep 24 07:53:35 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494103940 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gating.2494103940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/40.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_both.3419693074 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 328927771279 ps |
| CPU time | 560 seconds |
| Started | Sep 24 07:53:27 AM UTC 24 |
| Finished | Sep 24 08:02:54 AM UTC 24 |
| Peak memory | 211052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419693074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.3419693074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/40.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_interrupt.2846365910 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 161049971305 ps |
| CPU time | 180.83 seconds |
| Started | Sep 24 07:52:06 AM UTC 24 |
| Finished | Sep 24 07:55:10 AM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846365910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.2846365910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/40.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1943867941 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 497188892779 ps |
| CPU time | 439.88 seconds |
| Started | Sep 24 07:52:07 AM UTC 24 |
| Finished | Sep 24 07:59:32 AM UTC 24 |
| Peak memory | 210716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943867941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt_fixed.1943867941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/40.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_polled.2298865407 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 327662485729 ps |
| CPU time | 1072.33 seconds |
| Started | Sep 24 07:52:02 AM UTC 24 |
| Finished | Sep 24 08:10:06 AM UTC 24 |
| Peak memory | 213424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298865407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.2298865407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/40.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_polled_fixed.831793682 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 167159883622 ps |
| CPU time | 175.43 seconds |
| Started | Sep 24 07:52:03 AM UTC 24 |
| Finished | Sep 24 07:55:01 AM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831793682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixed.831793682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/40.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_wakeup_fixed.3099344314 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 398416570922 ps |
| CPU time | 1178.98 seconds |
| Started | Sep 24 07:53:13 AM UTC 24 |
| Finished | Sep 24 08:13:04 AM UTC 24 |
| Peak memory | 213508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099344314 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_wakeup_fixed.3099344314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/40.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_fsm_reset.2926796367 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 87095569897 ps |
| CPU time | 790.14 seconds |
| Started | Sep 24 07:53:42 AM UTC 24 |
| Finished | Sep 24 08:07:01 AM UTC 24 |
| Peak memory | 211076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926796367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2926796367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/40.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_lowpower_counter.2094333010 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 26499307576 ps |
| CPU time | 88.14 seconds |
| Started | Sep 24 07:53:38 AM UTC 24 |
| Finished | Sep 24 07:55:08 AM UTC 24 |
| Peak memory | 210576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094333010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2094333010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/40.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_poweron_counter.4191862904 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 2785547576 ps |
| CPU time | 3.97 seconds |
| Started | Sep 24 07:53:36 AM UTC 24 |
| Finished | Sep 24 07:53:41 AM UTC 24 |
| Peak memory | 210568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191862904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.4191862904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/40.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_smoke.1401513183 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 6012807221 ps |
| CPU time | 6.17 seconds |
| Started | Sep 24 07:51:59 AM UTC 24 |
| Finished | Sep 24 07:52:06 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401513183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.1401513183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/40.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.1870976599 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 1252594049 ps |
| CPU time | 7.7 seconds |
| Started | Sep 24 07:53:44 AM UTC 24 |
| Finished | Sep 24 07:53:53 AM UTC 24 |
| Peak memory | 210572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1870976599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 40.adc_ctrl_stress_all_with_rand_reset.1870976599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/40.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_alert_test.2106608160 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 476361431 ps |
| CPU time | 1.48 seconds |
| Started | Sep 24 07:55:48 AM UTC 24 |
| Finished | Sep 24 07:55:51 AM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106608160 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.2106608160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/41.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_both.1021699154 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 182117367587 ps |
| CPU time | 166.04 seconds |
| Started | Sep 24 07:55:07 AM UTC 24 |
| Finished | Sep 24 07:57:55 AM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021699154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.1021699154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/41.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_interrupt.3016436876 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 497156173364 ps |
| CPU time | 1413.22 seconds |
| Started | Sep 24 07:54:15 AM UTC 24 |
| Finished | Sep 24 08:18:03 AM UTC 24 |
| Peak memory | 213372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016436876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.3016436876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/41.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_interrupt_fixed.93391932 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 168775198109 ps |
| CPU time | 232.48 seconds |
| Started | Sep 24 07:54:26 AM UTC 24 |
| Finished | Sep 24 07:58:22 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93391932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas e_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt_fixed.93391932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/41.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_polled.753107693 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 335696250365 ps |
| CPU time | 506.68 seconds |
| Started | Sep 24 07:54:03 AM UTC 24 |
| Finished | Sep 24 08:02:36 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753107693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.753107693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/41.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_polled_fixed.2250858352 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 490591786750 ps |
| CPU time | 1158.82 seconds |
| Started | Sep 24 07:54:15 AM UTC 24 |
| Finished | Sep 24 08:13:46 AM UTC 24 |
| Peak memory | 213352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250858352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fixed.2250858352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/41.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_wakeup.4289344387 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 174049017987 ps |
| CPU time | 640.16 seconds |
| Started | Sep 24 07:54:34 AM UTC 24 |
| Finished | Sep 24 08:05:22 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289344387 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_wakeup.4289344387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/41.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_wakeup_fixed.3275755835 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 205922802874 ps |
| CPU time | 119.4 seconds |
| Started | Sep 24 07:55:01 AM UTC 24 |
| Finished | Sep 24 07:57:02 AM UTC 24 |
| Peak memory | 210760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275755835 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_wakeup_fixed.3275755835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/41.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_fsm_reset.1335152422 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 90952183875 ps |
| CPU time | 471.92 seconds |
| Started | Sep 24 07:55:18 AM UTC 24 |
| Finished | Sep 24 08:03:15 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335152422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.1335152422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/41.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_lowpower_counter.3838671713 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 29407043370 ps |
| CPU time | 103.41 seconds |
| Started | Sep 24 07:55:10 AM UTC 24 |
| Finished | Sep 24 07:56:55 AM UTC 24 |
| Peak memory | 210572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838671713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.3838671713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/41.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_poweron_counter.2835187583 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 2930615735 ps |
| CPU time | 6.82 seconds |
| Started | Sep 24 07:55:09 AM UTC 24 |
| Finished | Sep 24 07:55:17 AM UTC 24 |
| Peak memory | 210568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835187583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.2835187583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/41.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_smoke.3541149581 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 5951616851 ps |
| CPU time | 22.32 seconds |
| Started | Sep 24 07:54:02 AM UTC 24 |
| Finished | Sep 24 07:54:26 AM UTC 24 |
| Peak memory | 210640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541149581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.3541149581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/41.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_stress_all.2304503931 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 679198213969 ps |
| CPU time | 1767.11 seconds |
| Started | Sep 24 07:55:45 AM UTC 24 |
| Finished | Sep 24 08:25:30 AM UTC 24 |
| Peak memory | 213756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304503931 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.2304503931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/41.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3893159476 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 5980098715 ps |
| CPU time | 14.09 seconds |
| Started | Sep 24 07:55:34 AM UTC 24 |
| Finished | Sep 24 07:55:49 AM UTC 24 |
| Peak memory | 221236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3893159476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 41.adc_ctrl_stress_all_with_rand_reset.3893159476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/41.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_alert_test.2314087733 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 418505461 ps |
| CPU time | 2.6 seconds |
| Started | Sep 24 07:57:01 AM UTC 24 |
| Finished | Sep 24 07:57:05 AM UTC 24 |
| Peak memory | 210364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314087733 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2314087733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/42.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_clock_gating.3198392065 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 196392801688 ps |
| CPU time | 77.17 seconds |
| Started | Sep 24 07:56:08 AM UTC 24 |
| Finished | Sep 24 07:57:27 AM UTC 24 |
| Peak memory | 210868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198392065 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gating.3198392065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/42.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_both.804657803 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 164258450598 ps |
| CPU time | 63.25 seconds |
| Started | Sep 24 07:56:09 AM UTC 24 |
| Finished | Sep 24 07:57:14 AM UTC 24 |
| Peak memory | 210852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804657803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.804657803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/42.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_interrupt.2098793157 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 322457961675 ps |
| CPU time | 77.32 seconds |
| Started | Sep 24 07:55:52 AM UTC 24 |
| Finished | Sep 24 07:57:12 AM UTC 24 |
| Peak memory | 210720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098793157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.2098793157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/42.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3883982799 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 489366061126 ps |
| CPU time | 906.04 seconds |
| Started | Sep 24 07:55:53 AM UTC 24 |
| Finished | Sep 24 08:11:10 AM UTC 24 |
| Peak memory | 210688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883982799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt_fixed.3883982799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/42.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_polled.3137863795 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 327878768182 ps |
| CPU time | 213.25 seconds |
| Started | Sep 24 07:55:50 AM UTC 24 |
| Finished | Sep 24 07:59:26 AM UTC 24 |
| Peak memory | 210792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137863795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.3137863795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/42.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_polled_fixed.3230542360 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 161034810731 ps |
| CPU time | 236.54 seconds |
| Started | Sep 24 07:55:51 AM UTC 24 |
| Finished | Sep 24 07:59:51 AM UTC 24 |
| Peak memory | 210676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230542360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixed.3230542360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/42.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_wakeup.3183526515 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 173184989965 ps |
| CPU time | 104.5 seconds |
| Started | Sep 24 07:56:01 AM UTC 24 |
| Finished | Sep 24 07:57:47 AM UTC 24 |
| Peak memory | 211040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183526515 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_wakeup.3183526515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/42.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3910085780 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 199098034405 ps |
| CPU time | 178.21 seconds |
| Started | Sep 24 07:56:08 AM UTC 24 |
| Finished | Sep 24 07:59:09 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910085780 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_wakeup_fixed.3910085780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/42.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_fsm_reset.3891021625 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 128152696411 ps |
| CPU time | 730.98 seconds |
| Started | Sep 24 07:56:14 AM UTC 24 |
| Finished | Sep 24 08:08:33 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891021625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.3891021625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/42.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_lowpower_counter.3389333268 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 28162013361 ps |
| CPU time | 92.23 seconds |
| Started | Sep 24 07:56:13 AM UTC 24 |
| Finished | Sep 24 07:57:47 AM UTC 24 |
| Peak memory | 210572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389333268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3389333268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/42.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_poweron_counter.717397086 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 3865309022 ps |
| CPU time | 8.95 seconds |
| Started | Sep 24 07:56:11 AM UTC 24 |
| Finished | Sep 24 07:56:21 AM UTC 24 |
| Peak memory | 210492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717397086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.717397086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/42.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_smoke.828609822 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 5901074466 ps |
| CPU time | 15.24 seconds |
| Started | Sep 24 07:55:50 AM UTC 24 |
| Finished | Sep 24 07:56:07 AM UTC 24 |
| Peak memory | 210572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828609822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.828609822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/42.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_stress_all.1107333788 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 636942866127 ps |
| CPU time | 927.66 seconds |
| Started | Sep 24 07:56:56 AM UTC 24 |
| Finished | Sep 24 08:12:33 AM UTC 24 |
| Peak memory | 223936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107333788 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.1107333788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/42.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.3163285952 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 86127477017 ps |
| CPU time | 49.17 seconds |
| Started | Sep 24 07:56:22 AM UTC 24 |
| Finished | Sep 24 07:57:13 AM UTC 24 |
| Peak memory | 227632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3163285952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 42.adc_ctrl_stress_all_with_rand_reset.3163285952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/42.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_alert_test.904771024 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 398142173 ps |
| CPU time | 1.07 seconds |
| Started | Sep 24 07:57:48 AM UTC 24 |
| Finished | Sep 24 07:57:50 AM UTC 24 |
| Peak memory | 210444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904771024 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.904771024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/43.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_clock_gating.2964545835 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 524178608871 ps |
| CPU time | 374.27 seconds |
| Started | Sep 24 07:57:17 AM UTC 24 |
| Finished | Sep 24 08:03:36 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964545835 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gating.2964545835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/43.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_both.1390040422 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 355128716810 ps |
| CPU time | 1137.61 seconds |
| Started | Sep 24 07:57:23 AM UTC 24 |
| Finished | Sep 24 08:16:32 AM UTC 24 |
| Peak memory | 213512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390040422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.1390040422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/43.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_interrupt.316974283 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 158890130418 ps |
| CPU time | 150.06 seconds |
| Started | Sep 24 07:57:12 AM UTC 24 |
| Finished | Sep 24 07:59:45 AM UTC 24 |
| Peak memory | 210776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316974283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.316974283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/43.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_interrupt_fixed.3119729961 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 494908585957 ps |
| CPU time | 376.54 seconds |
| Started | Sep 24 07:57:14 AM UTC 24 |
| Finished | Sep 24 08:03:35 AM UTC 24 |
| Peak memory | 210768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119729961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt_fixed.3119729961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/43.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_polled.3495221875 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 328371045336 ps |
| CPU time | 790.51 seconds |
| Started | Sep 24 07:57:03 AM UTC 24 |
| Finished | Sep 24 08:10:22 AM UTC 24 |
| Peak memory | 210792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495221875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3495221875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/43.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_polled_fixed.231861774 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 485881557085 ps |
| CPU time | 1293.78 seconds |
| Started | Sep 24 07:57:05 AM UTC 24 |
| Finished | Sep 24 08:18:52 AM UTC 24 |
| Peak memory | 213416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231861774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixed.231861774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/43.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_wakeup.1140157125 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 170259102217 ps |
| CPU time | 95.32 seconds |
| Started | Sep 24 07:57:15 AM UTC 24 |
| Finished | Sep 24 07:58:52 AM UTC 24 |
| Peak memory | 210720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140157125 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_wakeup.1140157125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/43.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_wakeup_fixed.995340581 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 395678016413 ps |
| CPU time | 1140.93 seconds |
| Started | Sep 24 07:57:16 AM UTC 24 |
| Finished | Sep 24 08:16:28 AM UTC 24 |
| Peak memory | 213416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995340581 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_wakeup_fixed.995340581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/43.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_fsm_reset.121721165 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 70041379621 ps |
| CPU time | 347.8 seconds |
| Started | Sep 24 07:57:36 AM UTC 24 |
| Finished | Sep 24 08:03:28 AM UTC 24 |
| Peak memory | 211312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121721165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.121721165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/43.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_lowpower_counter.1680217659 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 23175622169 ps |
| CPU time | 95.47 seconds |
| Started | Sep 24 07:57:28 AM UTC 24 |
| Finished | Sep 24 07:59:06 AM UTC 24 |
| Peak memory | 210764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680217659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.1680217659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/43.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_poweron_counter.221363422 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 3875173329 ps |
| CPU time | 11.44 seconds |
| Started | Sep 24 07:57:23 AM UTC 24 |
| Finished | Sep 24 07:57:35 AM UTC 24 |
| Peak memory | 210756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221363422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.221363422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/43.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_smoke.1757653149 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 5726651764 ps |
| CPU time | 18.96 seconds |
| Started | Sep 24 07:57:02 AM UTC 24 |
| Finished | Sep 24 07:57:22 AM UTC 24 |
| Peak memory | 210832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757653149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1757653149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/43.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_stress_all.2082996637 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 164736402341 ps |
| CPU time | 51.9 seconds |
| Started | Sep 24 07:57:48 AM UTC 24 |
| Finished | Sep 24 07:58:42 AM UTC 24 |
| Peak memory | 210708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082996637 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.2082996637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/43.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.2618774675 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 961501344 ps |
| CPU time | 7.45 seconds |
| Started | Sep 24 07:57:43 AM UTC 24 |
| Finished | Sep 24 07:57:52 AM UTC 24 |
| Peak memory | 210572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2618774675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 43.adc_ctrl_stress_all_with_rand_reset.2618774675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/43.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_alert_test.3755160095 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 447547258 ps |
| CPU time | 1.35 seconds |
| Started | Sep 24 07:58:45 AM UTC 24 |
| Finished | Sep 24 07:58:48 AM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755160095 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.3755160095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/44.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_clock_gating.894886123 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 166780648040 ps |
| CPU time | 116.59 seconds |
| Started | Sep 24 07:58:18 AM UTC 24 |
| Finished | Sep 24 08:00:17 AM UTC 24 |
| Peak memory | 211124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894886123 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gating.894886123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/44.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_both.4225272001 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 166278631160 ps |
| CPU time | 103.15 seconds |
| Started | Sep 24 07:58:19 AM UTC 24 |
| Finished | Sep 24 08:00:04 AM UTC 24 |
| Peak memory | 211028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225272001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.4225272001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/44.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_interrupt.2193026674 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 168070271530 ps |
| CPU time | 648 seconds |
| Started | Sep 24 07:58:05 AM UTC 24 |
| Finished | Sep 24 08:09:00 AM UTC 24 |
| Peak memory | 210720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193026674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.2193026674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/44.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_interrupt_fixed.3730563456 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 495135126491 ps |
| CPU time | 1022.26 seconds |
| Started | Sep 24 07:58:06 AM UTC 24 |
| Finished | Sep 24 08:15:18 AM UTC 24 |
| Peak memory | 213420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730563456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt_fixed.3730563456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/44.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_polled.1904999323 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 498050518295 ps |
| CPU time | 795.65 seconds |
| Started | Sep 24 07:57:52 AM UTC 24 |
| Finished | Sep 24 08:11:17 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904999323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.1904999323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/44.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_polled_fixed.1906603752 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 329687438520 ps |
| CPU time | 427.48 seconds |
| Started | Sep 24 07:57:56 AM UTC 24 |
| Finished | Sep 24 08:05:09 AM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906603752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixed.1906603752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/44.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_wakeup.3046656699 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 554804225496 ps |
| CPU time | 1531.06 seconds |
| Started | Sep 24 07:58:07 AM UTC 24 |
| Finished | Sep 24 08:23:53 AM UTC 24 |
| Peak memory | 213364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046656699 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_wakeup.3046656699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/44.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_wakeup_fixed.58929406 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 591840001682 ps |
| CPU time | 727.26 seconds |
| Started | Sep 24 07:58:09 AM UTC 24 |
| Finished | Sep 24 08:10:24 AM UTC 24 |
| Peak memory | 210704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58929406 -assert nopostpro c +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_wakeup_fixed.58929406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/44.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_fsm_reset.2802984574 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 132091172987 ps |
| CPU time | 743.77 seconds |
| Started | Sep 24 07:58:34 AM UTC 24 |
| Finished | Sep 24 08:11:06 AM UTC 24 |
| Peak memory | 211128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802984574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.2802984574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/44.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_lowpower_counter.1949025237 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 38636401438 ps |
| CPU time | 142.1 seconds |
| Started | Sep 24 07:58:31 AM UTC 24 |
| Finished | Sep 24 08:00:56 AM UTC 24 |
| Peak memory | 210828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949025237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1949025237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/44.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_poweron_counter.1933855134 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 4836543873 ps |
| CPU time | 6.42 seconds |
| Started | Sep 24 07:58:23 AM UTC 24 |
| Finished | Sep 24 07:58:31 AM UTC 24 |
| Peak memory | 210568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933855134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.1933855134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/44.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_smoke.234664111 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 5646691969 ps |
| CPU time | 12.11 seconds |
| Started | Sep 24 07:57:51 AM UTC 24 |
| Finished | Sep 24 07:58:04 AM UTC 24 |
| Peak memory | 210572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234664111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.234664111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/44.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_alert_test.204531499 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 443183148 ps |
| CPU time | 1.79 seconds |
| Started | Sep 24 07:59:59 AM UTC 24 |
| Finished | Sep 24 08:00:02 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204531499 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.204531499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/45.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_clock_gating.4194945082 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 317930189583 ps |
| CPU time | 974.93 seconds |
| Started | Sep 24 07:59:27 AM UTC 24 |
| Finished | Sep 24 08:15:53 AM UTC 24 |
| Peak memory | 210716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194945082 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gating.4194945082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/45.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_both.262747580 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 531840648010 ps |
| CPU time | 1444.12 seconds |
| Started | Sep 24 07:59:33 AM UTC 24 |
| Finished | Sep 24 08:23:53 AM UTC 24 |
| Peak memory | 213368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262747580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.262747580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/45.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_interrupt.2307049394 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 162001506825 ps |
| CPU time | 153.52 seconds |
| Started | Sep 24 07:59:00 AM UTC 24 |
| Finished | Sep 24 08:01:36 AM UTC 24 |
| Peak memory | 210852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307049394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.2307049394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/45.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3555105651 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 326846494262 ps |
| CPU time | 244.63 seconds |
| Started | Sep 24 07:59:07 AM UTC 24 |
| Finished | Sep 24 08:03:15 AM UTC 24 |
| Peak memory | 211020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555105651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt_fixed.3555105651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/45.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_polled.1929200676 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 164578395555 ps |
| CPU time | 600.4 seconds |
| Started | Sep 24 07:58:52 AM UTC 24 |
| Finished | Sep 24 08:09:00 AM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929200676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.1929200676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/45.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_polled_fixed.3990239960 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 479844589630 ps |
| CPU time | 1164.91 seconds |
| Started | Sep 24 07:58:53 AM UTC 24 |
| Finished | Sep 24 08:18:29 AM UTC 24 |
| Peak memory | 213352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990239960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixed.3990239960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/45.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_wakeup.3071020014 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 206111242395 ps |
| CPU time | 518.96 seconds |
| Started | Sep 24 07:59:10 AM UTC 24 |
| Finished | Sep 24 08:07:54 AM UTC 24 |
| Peak memory | 210784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071020014 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_wakeup.3071020014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/45.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_wakeup_fixed.3205123133 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 611265883322 ps |
| CPU time | 408.72 seconds |
| Started | Sep 24 07:59:10 AM UTC 24 |
| Finished | Sep 24 08:06:03 AM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205123133 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_wakeup_fixed.3205123133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/45.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_fsm_reset.904400400 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 119457290621 ps |
| CPU time | 481.62 seconds |
| Started | Sep 24 07:59:46 AM UTC 24 |
| Finished | Sep 24 08:07:53 AM UTC 24 |
| Peak memory | 211120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904400400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.904400400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/45.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_lowpower_counter.1129174945 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 36465132268 ps |
| CPU time | 37.91 seconds |
| Started | Sep 24 07:59:46 AM UTC 24 |
| Finished | Sep 24 08:00:25 AM UTC 24 |
| Peak memory | 210572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129174945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1129174945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/45.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_poweron_counter.1674613852 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 5191246983 ps |
| CPU time | 6.16 seconds |
| Started | Sep 24 07:59:46 AM UTC 24 |
| Finished | Sep 24 07:59:53 AM UTC 24 |
| Peak memory | 210492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674613852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.1674613852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/45.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_smoke.1681241472 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 6086666643 ps |
| CPU time | 2.4 seconds |
| Started | Sep 24 07:58:48 AM UTC 24 |
| Finished | Sep 24 07:58:52 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681241472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.1681241472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/45.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_stress_all.2609254997 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 423573363237 ps |
| CPU time | 982.69 seconds |
| Started | Sep 24 07:59:54 AM UTC 24 |
| Finished | Sep 24 08:16:27 AM UTC 24 |
| Peak memory | 211016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609254997 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all.2609254997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/45.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.2494029710 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 21851530048 ps |
| CPU time | 9.42 seconds |
| Started | Sep 24 07:59:52 AM UTC 24 |
| Finished | Sep 24 08:00:03 AM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2494029710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 45.adc_ctrl_stress_all_with_rand_reset.2494029710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/45.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_alert_test.1840542110 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 286312153 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 08:02:40 AM UTC 24 |
| Finished | Sep 24 08:02:42 AM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840542110 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1840542110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/46.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_clock_gating.143824976 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 336787494774 ps |
| CPU time | 302.91 seconds |
| Started | Sep 24 08:00:57 AM UTC 24 |
| Finished | Sep 24 08:06:04 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143824976 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gating.143824976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/46.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_both.2241240354 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 327218858737 ps |
| CPU time | 264.96 seconds |
| Started | Sep 24 08:01:36 AM UTC 24 |
| Finished | Sep 24 08:06:05 AM UTC 24 |
| Peak memory | 210780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241240354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.2241240354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/46.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_interrupt.3208710650 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 161926205415 ps |
| CPU time | 480.4 seconds |
| Started | Sep 24 08:00:18 AM UTC 24 |
| Finished | Sep 24 08:08:24 AM UTC 24 |
| Peak memory | 210744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208710650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.3208710650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/46.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_interrupt_fixed.948845145 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 163582519773 ps |
| CPU time | 101.1 seconds |
| Started | Sep 24 08:00:26 AM UTC 24 |
| Finished | Sep 24 08:02:09 AM UTC 24 |
| Peak memory | 210760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948845145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt_fixed.948845145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/46.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_polled_fixed.524745836 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 496312971305 ps |
| CPU time | 518.85 seconds |
| Started | Sep 24 08:00:07 AM UTC 24 |
| Finished | Sep 24 08:08:52 AM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524745836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fixed.524745836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/46.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_wakeup.2011652975 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 188493662829 ps |
| CPU time | 391.34 seconds |
| Started | Sep 24 08:00:31 AM UTC 24 |
| Finished | Sep 24 08:07:07 AM UTC 24 |
| Peak memory | 210844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011652975 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_wakeup.2011652975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/46.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1089370469 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 601560971247 ps |
| CPU time | 478.67 seconds |
| Started | Sep 24 08:00:35 AM UTC 24 |
| Finished | Sep 24 08:08:39 AM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089370469 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_wakeup_fixed.1089370469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/46.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_fsm_reset.2860841456 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 70029228074 ps |
| CPU time | 240.58 seconds |
| Started | Sep 24 08:02:09 AM UTC 24 |
| Finished | Sep 24 08:06:13 AM UTC 24 |
| Peak memory | 211064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860841456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.2860841456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/46.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_lowpower_counter.2738050140 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 41969043968 ps |
| CPU time | 28.05 seconds |
| Started | Sep 24 08:01:50 AM UTC 24 |
| Finished | Sep 24 08:02:20 AM UTC 24 |
| Peak memory | 210572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738050140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2738050140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/46.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_poweron_counter.825678851 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 4580095684 ps |
| CPU time | 5.95 seconds |
| Started | Sep 24 08:01:42 AM UTC 24 |
| Finished | Sep 24 08:01:49 AM UTC 24 |
| Peak memory | 210492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825678851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.825678851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/46.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_smoke.3035638393 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 5741515049 ps |
| CPU time | 21.8 seconds |
| Started | Sep 24 08:00:06 AM UTC 24 |
| Finished | Sep 24 08:00:30 AM UTC 24 |
| Peak memory | 210768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035638393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3035638393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/46.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_stress_all.793170233 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 218491572776 ps |
| CPU time | 501.04 seconds |
| Started | Sep 24 08:02:37 AM UTC 24 |
| Finished | Sep 24 08:11:03 AM UTC 24 |
| Peak memory | 211004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793170233 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.793170233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/46.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.2391006321 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 5732946237 ps |
| CPU time | 16.1 seconds |
| Started | Sep 24 08:02:22 AM UTC 24 |
| Finished | Sep 24 08:02:39 AM UTC 24 |
| Peak memory | 221284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2391006321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 46.adc_ctrl_stress_all_with_rand_reset.2391006321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/46.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_alert_test.3120715345 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 308972467 ps |
| CPU time | 1.38 seconds |
| Started | Sep 24 08:04:48 AM UTC 24 |
| Finished | Sep 24 08:04:50 AM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120715345 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3120715345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/47.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_clock_gating.4264949714 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 163820427849 ps |
| CPU time | 352.84 seconds |
| Started | Sep 24 08:03:35 AM UTC 24 |
| Finished | Sep 24 08:09:32 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264949714 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gating.4264949714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/47.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_both.2641220350 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 380314420449 ps |
| CPU time | 469.8 seconds |
| Started | Sep 24 08:03:36 AM UTC 24 |
| Finished | Sep 24 08:11:32 AM UTC 24 |
| Peak memory | 210836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641220350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.2641220350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/47.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_interrupt.31015325 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 161096357046 ps |
| CPU time | 420.8 seconds |
| Started | Sep 24 08:03:15 AM UTC 24 |
| Finished | Sep 24 08:10:21 AM UTC 24 |
| Peak memory | 210724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31015325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_ SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.31015325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/47.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_interrupt_fixed.711121269 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 494879498609 ps |
| CPU time | 982.74 seconds |
| Started | Sep 24 08:03:16 AM UTC 24 |
| Finished | Sep 24 08:19:50 AM UTC 24 |
| Peak memory | 213436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711121269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt_fixed.711121269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/47.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_polled.3826937589 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 327017506995 ps |
| CPU time | 175.42 seconds |
| Started | Sep 24 08:02:54 AM UTC 24 |
| Finished | Sep 24 08:05:52 AM UTC 24 |
| Peak memory | 210852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826937589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.3826937589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/47.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_polled_fixed.1764338538 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 484700951163 ps |
| CPU time | 597.34 seconds |
| Started | Sep 24 08:03:07 AM UTC 24 |
| Finished | Sep 24 08:13:11 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764338538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixed.1764338538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/47.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_wakeup.1400191874 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 370387798360 ps |
| CPU time | 458.81 seconds |
| Started | Sep 24 08:03:28 AM UTC 24 |
| Finished | Sep 24 08:11:12 AM UTC 24 |
| Peak memory | 210720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400191874 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_wakeup.1400191874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/47.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3106000849 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 200237591979 ps |
| CPU time | 521.97 seconds |
| Started | Sep 24 08:03:34 AM UTC 24 |
| Finished | Sep 24 08:12:22 AM UTC 24 |
| Peak memory | 210696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106000849 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_wakeup_fixed.3106000849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/47.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_fsm_reset.4171091433 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 63101691846 ps |
| CPU time | 245.81 seconds |
| Started | Sep 24 08:04:25 AM UTC 24 |
| Finished | Sep 24 08:08:33 AM UTC 24 |
| Peak memory | 211140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171091433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.4171091433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/47.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_lowpower_counter.1582950556 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 33016614935 ps |
| CPU time | 35.53 seconds |
| Started | Sep 24 08:04:08 AM UTC 24 |
| Finished | Sep 24 08:04:44 AM UTC 24 |
| Peak memory | 210760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582950556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.1582950556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/47.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_poweron_counter.686693615 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 3821714720 ps |
| CPU time | 18.66 seconds |
| Started | Sep 24 08:04:04 AM UTC 24 |
| Finished | Sep 24 08:04:23 AM UTC 24 |
| Peak memory | 210756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686693615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.686693615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/47.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_smoke.2793898518 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 5811323127 ps |
| CPU time | 22.17 seconds |
| Started | Sep 24 08:02:43 AM UTC 24 |
| Finished | Sep 24 08:03:06 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793898518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2793898518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/47.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_stress_all.2100689297 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 377220798093 ps |
| CPU time | 281.2 seconds |
| Started | Sep 24 08:04:45 AM UTC 24 |
| Finished | Sep 24 08:09:30 AM UTC 24 |
| Peak memory | 210768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100689297 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.2100689297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/47.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.844016933 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 11792637482 ps |
| CPU time | 18.31 seconds |
| Started | Sep 24 08:04:28 AM UTC 24 |
| Finished | Sep 24 08:04:47 AM UTC 24 |
| Peak memory | 221384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=844016933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.844016933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/47.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_alert_test.1800933542 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 388940489 ps |
| CPU time | 2.34 seconds |
| Started | Sep 24 08:06:29 AM UTC 24 |
| Finished | Sep 24 08:06:32 AM UTC 24 |
| Peak memory | 210368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800933542 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1800933542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/48.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_interrupt.1168858021 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 486953105936 ps |
| CPU time | 401.37 seconds |
| Started | Sep 24 08:05:23 AM UTC 24 |
| Finished | Sep 24 08:12:10 AM UTC 24 |
| Peak memory | 210792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168858021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.1168858021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/48.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_interrupt_fixed.126370148 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 489093535451 ps |
| CPU time | 674.71 seconds |
| Started | Sep 24 08:05:30 AM UTC 24 |
| Finished | Sep 24 08:16:52 AM UTC 24 |
| Peak memory | 210768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126370148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt_fixed.126370148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/48.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_polled.681921923 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 166356893994 ps |
| CPU time | 188.14 seconds |
| Started | Sep 24 08:05:07 AM UTC 24 |
| Finished | Sep 24 08:08:18 AM UTC 24 |
| Peak memory | 211036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681921923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.681921923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/48.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_polled_fixed.1286589113 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 335109621171 ps |
| CPU time | 117.88 seconds |
| Started | Sep 24 08:05:10 AM UTC 24 |
| Finished | Sep 24 08:07:10 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286589113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixed.1286589113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/48.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_wakeup.850470174 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 558068253364 ps |
| CPU time | 477.5 seconds |
| Started | Sep 24 08:05:31 AM UTC 24 |
| Finished | Sep 24 08:13:35 AM UTC 24 |
| Peak memory | 210844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850470174 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_wakeup.850470174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/48.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3107111866 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 416065949899 ps |
| CPU time | 1246.73 seconds |
| Started | Sep 24 08:05:53 AM UTC 24 |
| Finished | Sep 24 08:26:52 AM UTC 24 |
| Peak memory | 213412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107111866 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_wakeup_fixed.3107111866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/48.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_fsm_reset.3083897076 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 78636593053 ps |
| CPU time | 440.15 seconds |
| Started | Sep 24 08:06:14 AM UTC 24 |
| Finished | Sep 24 08:13:39 AM UTC 24 |
| Peak memory | 211196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083897076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3083897076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/48.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_lowpower_counter.1963497638 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 38205205744 ps |
| CPU time | 114.1 seconds |
| Started | Sep 24 08:06:06 AM UTC 24 |
| Finished | Sep 24 08:08:02 AM UTC 24 |
| Peak memory | 210764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963497638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.1963497638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/48.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_poweron_counter.3353117945 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 4660579917 ps |
| CPU time | 20.06 seconds |
| Started | Sep 24 08:06:05 AM UTC 24 |
| Finished | Sep 24 08:06:26 AM UTC 24 |
| Peak memory | 210824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353117945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.3353117945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/48.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_smoke.2571287497 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 5702296034 ps |
| CPU time | 14.07 seconds |
| Started | Sep 24 08:04:51 AM UTC 24 |
| Finished | Sep 24 08:05:06 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571287497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.2571287497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/48.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_stress_all.1350643106 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 1349030199747 ps |
| CPU time | 1139.76 seconds |
| Started | Sep 24 08:06:27 AM UTC 24 |
| Finished | Sep 24 08:25:39 AM UTC 24 |
| Peak memory | 223960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350643106 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.1350643106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/48.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.2804717365 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 6736304357 ps |
| CPU time | 23.32 seconds |
| Started | Sep 24 08:06:22 AM UTC 24 |
| Finished | Sep 24 08:06:46 AM UTC 24 |
| Peak memory | 221108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2804717365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 48.adc_ctrl_stress_all_with_rand_reset.2804717365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/48.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_alert_test.2597597460 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 506676341 ps |
| CPU time | 2.26 seconds |
| Started | Sep 24 08:08:19 AM UTC 24 |
| Finished | Sep 24 08:08:23 AM UTC 24 |
| Peak memory | 210368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597597460 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.2597597460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/49.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_clock_gating.3393894107 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 330838647058 ps |
| CPU time | 892.69 seconds |
| Started | Sep 24 08:07:37 AM UTC 24 |
| Finished | Sep 24 08:22:40 AM UTC 24 |
| Peak memory | 213628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393894107 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gating.3393894107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/49.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_both.822815277 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 509444070435 ps |
| CPU time | 486.96 seconds |
| Started | Sep 24 08:07:41 AM UTC 24 |
| Finished | Sep 24 08:15:54 AM UTC 24 |
| Peak memory | 210856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822815277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.822815277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/49.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt.3400750149 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 493340796359 ps |
| CPU time | 1550.4 seconds |
| Started | Sep 24 08:07:01 AM UTC 24 |
| Finished | Sep 24 08:33:09 AM UTC 24 |
| Peak memory | 213372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400750149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3400750149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/49.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2913061306 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 327688242221 ps |
| CPU time | 412.64 seconds |
| Started | Sep 24 08:07:07 AM UTC 24 |
| Finished | Sep 24 08:14:05 AM UTC 24 |
| Peak memory | 210828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913061306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt_fixed.2913061306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/49.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_polled.2177488692 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 329543809891 ps |
| CPU time | 307.79 seconds |
| Started | Sep 24 08:06:40 AM UTC 24 |
| Finished | Sep 24 08:11:52 AM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177488692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2177488692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/49.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_polled_fixed.2054136977 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 488951828919 ps |
| CPU time | 362.2 seconds |
| Started | Sep 24 08:06:47 AM UTC 24 |
| Finished | Sep 24 08:12:54 AM UTC 24 |
| Peak memory | 210780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054136977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixed.2054136977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/49.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_wakeup.1307342184 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 380387803734 ps |
| CPU time | 162.14 seconds |
| Started | Sep 24 08:07:11 AM UTC 24 |
| Finished | Sep 24 08:09:55 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307342184 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_wakeup.1307342184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/49.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_wakeup_fixed.3552036382 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 607311547999 ps |
| CPU time | 1520.21 seconds |
| Started | Sep 24 08:07:33 AM UTC 24 |
| Finished | Sep 24 08:33:08 AM UTC 24 |
| Peak memory | 213352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552036382 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_wakeup_fixed.3552036382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/49.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_fsm_reset.1043030624 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 121400690665 ps |
| CPU time | 566.39 seconds |
| Started | Sep 24 08:08:02 AM UTC 24 |
| Finished | Sep 24 08:17:35 AM UTC 24 |
| Peak memory | 211380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043030624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.1043030624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/49.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_lowpower_counter.650063836 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 36047570749 ps |
| CPU time | 89 seconds |
| Started | Sep 24 08:07:55 AM UTC 24 |
| Finished | Sep 24 08:09:26 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650063836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.650063836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/49.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_poweron_counter.2152348230 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 4043056583 ps |
| CPU time | 6.29 seconds |
| Started | Sep 24 08:07:54 AM UTC 24 |
| Finished | Sep 24 08:08:01 AM UTC 24 |
| Peak memory | 210568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152348230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2152348230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/49.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_smoke.326463151 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 5706834562 ps |
| CPU time | 4.76 seconds |
| Started | Sep 24 08:06:33 AM UTC 24 |
| Finished | Sep 24 08:06:39 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326463151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.326463151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/49.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_stress_all.1236612000 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 173174720489 ps |
| CPU time | 64.01 seconds |
| Started | Sep 24 08:08:18 AM UTC 24 |
| Finished | Sep 24 08:09:24 AM UTC 24 |
| Peak memory | 210716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236612000 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.1236612000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/49.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.249581308 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 2414396555 ps |
| CPU time | 13.38 seconds |
| Started | Sep 24 08:08:03 AM UTC 24 |
| Finished | Sep 24 08:08:18 AM UTC 24 |
| Peak memory | 221108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=249581308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.249581308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/49.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_alert_test.3473837257 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 448241198 ps |
| CPU time | 1.76 seconds |
| Started | Sep 24 07:00:34 AM UTC 24 |
| Finished | Sep 24 07:00:37 AM UTC 24 |
| Peak memory | 210168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473837257 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.3473837257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/5.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_clock_gating.1151770516 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 174715752017 ps |
| CPU time | 153.3 seconds |
| Started | Sep 24 07:00:08 AM UTC 24 |
| Finished | Sep 24 07:02:43 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151770516 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gating.1151770516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/5.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_both.2829223832 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 397956084272 ps |
| CPU time | 1094.73 seconds |
| Started | Sep 24 07:00:13 AM UTC 24 |
| Finished | Sep 24 07:18:39 AM UTC 24 |
| Peak memory | 213408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829223832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.2829223832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/5.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt.3647798665 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 160469168842 ps |
| CPU time | 116.06 seconds |
| Started | Sep 24 07:00:00 AM UTC 24 |
| Finished | Sep 24 07:02:03 AM UTC 24 |
| Peak memory | 210744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647798665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3647798665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/5.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3417266451 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 338128414920 ps |
| CPU time | 282.48 seconds |
| Started | Sep 24 07:00:01 AM UTC 24 |
| Finished | Sep 24 07:04:52 AM UTC 24 |
| Peak memory | 210800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417266451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt_fixed.3417266451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/5.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled.4159230835 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 156796334632 ps |
| CPU time | 452.88 seconds |
| Started | Sep 24 06:59:58 AM UTC 24 |
| Finished | Sep 24 07:07:36 AM UTC 24 |
| Peak memory | 211068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159230835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.4159230835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/5.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled_fixed.3644113852 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 495164227991 ps |
| CPU time | 217.83 seconds |
| Started | Sep 24 07:00:00 AM UTC 24 |
| Finished | Sep 24 07:03:45 AM UTC 24 |
| Peak memory | 210708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644113852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed.3644113852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/5.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup.2066982247 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 339388995870 ps |
| CPU time | 590.59 seconds |
| Started | Sep 24 07:00:06 AM UTC 24 |
| Finished | Sep 24 07:10:04 AM UTC 24 |
| Peak memory | 210768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066982247 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_wakeup.2066982247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/5.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup_fixed.918551701 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 614419218142 ps |
| CPU time | 1638.54 seconds |
| Started | Sep 24 07:00:06 AM UTC 24 |
| Finished | Sep 24 07:27:41 AM UTC 24 |
| Peak memory | 213356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918551701 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_wakeup_fixed.918551701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/5.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_fsm_reset.4121997205 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 75374620052 ps |
| CPU time | 351.77 seconds |
| Started | Sep 24 07:00:25 AM UTC 24 |
| Finished | Sep 24 07:06:21 AM UTC 24 |
| Peak memory | 211128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121997205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.4121997205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/5.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_lowpower_counter.87214888 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 24896119190 ps |
| CPU time | 14.89 seconds |
| Started | Sep 24 07:00:21 AM UTC 24 |
| Finished | Sep 24 07:00:37 AM UTC 24 |
| Peak memory | 210820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87214888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_ SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.87214888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/5.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_poweron_counter.2078451678 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 3711133766 ps |
| CPU time | 3.33 seconds |
| Started | Sep 24 07:00:21 AM UTC 24 |
| Finished | Sep 24 07:00:26 AM UTC 24 |
| Peak memory | 210388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078451678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2078451678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/5.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_smoke.1489366625 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 6088685556 ps |
| CPU time | 20.65 seconds |
| Started | Sep 24 06:59:58 AM UTC 24 |
| Finished | Sep 24 07:00:20 AM UTC 24 |
| Peak memory | 210580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489366625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.1489366625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/5.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all.3490045758 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 119267962808 ps |
| CPU time | 420.87 seconds |
| Started | Sep 24 07:00:34 AM UTC 24 |
| Finished | Sep 24 07:07:40 AM UTC 24 |
| Peak memory | 221028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490045758 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.3490045758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3006354570 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 2457563747 ps |
| CPU time | 6.43 seconds |
| Started | Sep 24 07:00:26 AM UTC 24 |
| Finished | Sep 24 07:00:34 AM UTC 24 |
| Peak memory | 210624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3006354570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 5.adc_ctrl_stress_all_with_rand_reset.3006354570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_alert_test.436994302 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 398581203 ps |
| CPU time | 1.74 seconds |
| Started | Sep 24 07:01:45 AM UTC 24 |
| Finished | Sep 24 07:01:48 AM UTC 24 |
| Peak memory | 210384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436994302 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.436994302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/6.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_clock_gating.167445202 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 332923982994 ps |
| CPU time | 224.24 seconds |
| Started | Sep 24 07:01:00 AM UTC 24 |
| Finished | Sep 24 07:04:48 AM UTC 24 |
| Peak memory | 210780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167445202 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gating.167445202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/6.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt_fixed.2418756533 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 485057619489 ps |
| CPU time | 424.96 seconds |
| Started | Sep 24 07:00:42 AM UTC 24 |
| Finished | Sep 24 07:07:52 AM UTC 24 |
| Peak memory | 210768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418756533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt_fixed.2418756533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/6.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled.2476915293 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 487785280004 ps |
| CPU time | 342.4 seconds |
| Started | Sep 24 07:00:38 AM UTC 24 |
| Finished | Sep 24 07:06:25 AM UTC 24 |
| Peak memory | 210780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476915293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.2476915293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/6.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled_fixed.3027372579 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 492489832286 ps |
| CPU time | 338.65 seconds |
| Started | Sep 24 07:00:39 AM UTC 24 |
| Finished | Sep 24 07:06:22 AM UTC 24 |
| Peak memory | 211032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027372579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixed.3027372579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/6.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup_fixed.3865596652 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 391318304817 ps |
| CPU time | 196.28 seconds |
| Started | Sep 24 07:00:58 AM UTC 24 |
| Finished | Sep 24 07:04:17 AM UTC 24 |
| Peak memory | 210676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865596652 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_wakeup_fixed.3865596652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/6.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_lowpower_counter.913220172 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 25342349610 ps |
| CPU time | 54.92 seconds |
| Started | Sep 24 07:01:12 AM UTC 24 |
| Finished | Sep 24 07:02:08 AM UTC 24 |
| Peak memory | 210492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913220172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.913220172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/6.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_poweron_counter.1223018475 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 5339585281 ps |
| CPU time | 10.16 seconds |
| Started | Sep 24 07:01:04 AM UTC 24 |
| Finished | Sep 24 07:01:16 AM UTC 24 |
| Peak memory | 210584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223018475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.1223018475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/6.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_smoke.3890532448 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 5919613788 ps |
| CPU time | 25.65 seconds |
| Started | Sep 24 07:00:36 AM UTC 24 |
| Finished | Sep 24 07:01:04 AM UTC 24 |
| Peak memory | 210580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890532448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3890532448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/6.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3648930437 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 15278249068 ps |
| CPU time | 7.67 seconds |
| Started | Sep 24 07:01:25 AM UTC 24 |
| Finished | Sep 24 07:01:33 AM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3648930437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 6.adc_ctrl_stress_all_with_rand_reset.3648930437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/6.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_alert_test.3031292970 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 381931782 ps |
| CPU time | 1.19 seconds |
| Started | Sep 24 07:03:18 AM UTC 24 |
| Finished | Sep 24 07:03:21 AM UTC 24 |
| Peak memory | 210376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031292970 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.3031292970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/7.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_both.2542398551 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 177990531757 ps |
| CPU time | 552.19 seconds |
| Started | Sep 24 07:02:30 AM UTC 24 |
| Finished | Sep 24 07:11:48 AM UTC 24 |
| Peak memory | 210756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542398551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.2542398551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/7.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt.945052874 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 322475209465 ps |
| CPU time | 223.63 seconds |
| Started | Sep 24 07:01:56 AM UTC 24 |
| Finished | Sep 24 07:05:42 AM UTC 24 |
| Peak memory | 210988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945052874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.945052874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/7.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2032882178 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 325024776613 ps |
| CPU time | 209.55 seconds |
| Started | Sep 24 07:02:04 AM UTC 24 |
| Finished | Sep 24 07:05:36 AM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032882178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt_fixed.2032882178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/7.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled.1796135102 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 162237020462 ps |
| CPU time | 210.94 seconds |
| Started | Sep 24 07:01:48 AM UTC 24 |
| Finished | Sep 24 07:05:23 AM UTC 24 |
| Peak memory | 210852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796135102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.1796135102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/7.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled_fixed.3896555324 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 331099135511 ps |
| CPU time | 468.77 seconds |
| Started | Sep 24 07:01:49 AM UTC 24 |
| Finished | Sep 24 07:09:44 AM UTC 24 |
| Peak memory | 210768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896555324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed.3896555324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/7.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup.4190917059 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 411502156600 ps |
| CPU time | 120.57 seconds |
| Started | Sep 24 07:02:09 AM UTC 24 |
| Finished | Sep 24 07:04:12 AM UTC 24 |
| Peak memory | 210768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190917059 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_wakeup.4190917059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/7.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3846558009 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 595496166357 ps |
| CPU time | 568.57 seconds |
| Started | Sep 24 07:02:14 AM UTC 24 |
| Finished | Sep 24 07:11:49 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846558009 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_wakeup_fixed.3846558009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/7.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_fsm_reset.2032996213 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 108244612475 ps |
| CPU time | 413.21 seconds |
| Started | Sep 24 07:02:52 AM UTC 24 |
| Finished | Sep 24 07:09:50 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032996213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.2032996213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/7.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_lowpower_counter.140275658 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 35852456888 ps |
| CPU time | 33.05 seconds |
| Started | Sep 24 07:02:48 AM UTC 24 |
| Finished | Sep 24 07:03:22 AM UTC 24 |
| Peak memory | 210756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140275658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.140275658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/7.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_poweron_counter.822171989 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 4400257776 ps |
| CPU time | 2.41 seconds |
| Started | Sep 24 07:02:44 AM UTC 24 |
| Finished | Sep 24 07:02:47 AM UTC 24 |
| Peak memory | 210760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822171989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.822171989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/7.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_smoke.1589611670 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 5931872990 ps |
| CPU time | 24.84 seconds |
| Started | Sep 24 07:01:46 AM UTC 24 |
| Finished | Sep 24 07:02:13 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589611670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.1589611670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/7.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.302982125 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 60899093550 ps |
| CPU time | 27.1 seconds |
| Started | Sep 24 07:03:08 AM UTC 24 |
| Finished | Sep 24 07:03:37 AM UTC 24 |
| Peak memory | 210836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=302982125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.302982125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_alert_test.12371239 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 501760951 ps |
| CPU time | 3 seconds |
| Started | Sep 24 07:04:53 AM UTC 24 |
| Finished | Sep 24 07:04:57 AM UTC 24 |
| Peak memory | 210372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12371239 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.12371239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/8.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_clock_gating.351406264 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 495298539882 ps |
| CPU time | 344.61 seconds |
| Started | Sep 24 07:04:13 AM UTC 24 |
| Finished | Sep 24 07:10:02 AM UTC 24 |
| Peak memory | 210716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351406264 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gating.351406264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/8.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_both.3222741526 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 503283224454 ps |
| CPU time | 1148.26 seconds |
| Started | Sep 24 07:04:18 AM UTC 24 |
| Finished | Sep 24 07:23:38 AM UTC 24 |
| Peak memory | 213368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222741526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.3222741526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/8.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt.3195372807 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 163355454118 ps |
| CPU time | 118.25 seconds |
| Started | Sep 24 07:03:38 AM UTC 24 |
| Finished | Sep 24 07:05:38 AM UTC 24 |
| Peak memory | 210856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195372807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.3195372807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/8.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt_fixed.305772619 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 504438234623 ps |
| CPU time | 1113.39 seconds |
| Started | Sep 24 07:03:38 AM UTC 24 |
| Finished | Sep 24 07:22:22 AM UTC 24 |
| Peak memory | 213716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305772619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt_fixed.305772619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/8.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled.527149554 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 159903655119 ps |
| CPU time | 481.31 seconds |
| Started | Sep 24 07:03:24 AM UTC 24 |
| Finished | Sep 24 07:11:31 AM UTC 24 |
| Peak memory | 210720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527149554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.527149554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/8.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled_fixed.3245194949 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 324395142623 ps |
| CPU time | 482.23 seconds |
| Started | Sep 24 07:03:33 AM UTC 24 |
| Finished | Sep 24 07:11:40 AM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245194949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed.3245194949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/8.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup.3619878710 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 164212531056 ps |
| CPU time | 127.67 seconds |
| Started | Sep 24 07:03:46 AM UTC 24 |
| Finished | Sep 24 07:05:56 AM UTC 24 |
| Peak memory | 210768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619878710 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_wakeup.3619878710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/8.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup_fixed.2103031886 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 598848036708 ps |
| CPU time | 1381.95 seconds |
| Started | Sep 24 07:04:12 AM UTC 24 |
| Finished | Sep 24 07:27:28 AM UTC 24 |
| Peak memory | 213432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103031886 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_wakeup_fixed.2103031886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/8.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_fsm_reset.116633031 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 124994184759 ps |
| CPU time | 921.2 seconds |
| Started | Sep 24 07:04:48 AM UTC 24 |
| Finished | Sep 24 07:20:19 AM UTC 24 |
| Peak memory | 213972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116633031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.116633031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/8.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_lowpower_counter.3951494375 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 38242904981 ps |
| CPU time | 91.84 seconds |
| Started | Sep 24 07:04:41 AM UTC 24 |
| Finished | Sep 24 07:06:15 AM UTC 24 |
| Peak memory | 210568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951494375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.3951494375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/8.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_poweron_counter.4199491424 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 4498514249 ps |
| CPU time | 2.38 seconds |
| Started | Sep 24 07:04:37 AM UTC 24 |
| Finished | Sep 24 07:04:41 AM UTC 24 |
| Peak memory | 210496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199491424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.4199491424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/8.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_smoke.3026422456 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 5947254599 ps |
| CPU time | 14.79 seconds |
| Started | Sep 24 07:03:21 AM UTC 24 |
| Finished | Sep 24 07:03:37 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026422456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3026422456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/8.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all.3933539755 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 548698565522 ps |
| CPU time | 877.56 seconds |
| Started | Sep 24 07:04:52 AM UTC 24 |
| Finished | Sep 24 07:19:39 AM UTC 24 |
| Peak memory | 213364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933539755 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.3933539755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/8.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3829976456 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1450851939 ps |
| CPU time | 7 seconds |
| Started | Sep 24 07:04:52 AM UTC 24 |
| Finished | Sep 24 07:05:00 AM UTC 24 |
| Peak memory | 210568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3829976456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 8.adc_ctrl_stress_all_with_rand_reset.3829976456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/8.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_alert_test.2713601818 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 583678549 ps |
| CPU time | 1.13 seconds |
| Started | Sep 24 07:06:17 AM UTC 24 |
| Finished | Sep 24 07:06:19 AM UTC 24 |
| Peak memory | 210384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713601818 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.2713601818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/9.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_clock_gating.2716304357 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 436370736989 ps |
| CPU time | 812.46 seconds |
| Started | Sep 24 07:05:37 AM UTC 24 |
| Finished | Sep 24 07:19:18 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716304357 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gating.2716304357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/9.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_both.3906944380 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 328806518378 ps |
| CPU time | 962.36 seconds |
| Started | Sep 24 07:05:39 AM UTC 24 |
| Finished | Sep 24 07:21:51 AM UTC 24 |
| Peak memory | 213760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906944380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.3906944380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/9.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt.2357032266 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 158867906327 ps |
| CPU time | 160.32 seconds |
| Started | Sep 24 07:05:02 AM UTC 24 |
| Finished | Sep 24 07:07:45 AM UTC 24 |
| Peak memory | 210724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357032266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2357032266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/9.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt_fixed.3854732178 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 325551394752 ps |
| CPU time | 275.43 seconds |
| Started | Sep 24 07:05:24 AM UTC 24 |
| Finished | Sep 24 07:10:03 AM UTC 24 |
| Peak memory | 210840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854732178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt_fixed.3854732178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/9.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled.2433595436 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 503201094522 ps |
| CPU time | 1508.57 seconds |
| Started | Sep 24 07:04:58 AM UTC 24 |
| Finished | Sep 24 07:30:21 AM UTC 24 |
| Peak memory | 213636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433595436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2433595436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/9.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled_fixed.2108499878 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 327596830802 ps |
| CPU time | 189.85 seconds |
| Started | Sep 24 07:05:02 AM UTC 24 |
| Finished | Sep 24 07:08:14 AM UTC 24 |
| Peak memory | 210684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108499878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed.2108499878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/9.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup.4286326434 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 185748954098 ps |
| CPU time | 411.5 seconds |
| Started | Sep 24 07:05:25 AM UTC 24 |
| Finished | Sep 24 07:12:21 AM UTC 24 |
| Peak memory | 210708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286326434 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_wakeup.4286326434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/9.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup_fixed.461886992 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 584854435472 ps |
| CPU time | 442.08 seconds |
| Started | Sep 24 07:05:31 AM UTC 24 |
| Finished | Sep 24 07:12:58 AM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461886992 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_wakeup_fixed.461886992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/9.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.3823647754 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 111236624875 ps |
| CPU time | 409.92 seconds |
| Started | Sep 24 07:05:56 AM UTC 24 |
| Finished | Sep 24 07:12:51 AM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823647754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.3823647754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/9.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_lowpower_counter.3135293276 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 35462364966 ps |
| CPU time | 26.62 seconds |
| Started | Sep 24 07:05:51 AM UTC 24 |
| Finished | Sep 24 07:06:19 AM UTC 24 |
| Peak memory | 210496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135293276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3135293276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/9.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_poweron_counter.1042881359 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 4825194297 ps |
| CPU time | 5.88 seconds |
| Started | Sep 24 07:05:43 AM UTC 24 |
| Finished | Sep 24 07:05:50 AM UTC 24 |
| Peak memory | 210480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042881359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1042881359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/9.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_smoke.170439314 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 5894854372 ps |
| CPU time | 4.15 seconds |
| Started | Sep 24 07:04:56 AM UTC 24 |
| Finished | Sep 24 07:05:01 AM UTC 24 |
| Peak memory | 210572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170439314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.170439314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/9.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.972146016 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 625307760 ps |
| CPU time | 5.69 seconds |
| Started | Sep 24 07:06:09 AM UTC 24 |
| Finished | Sep 24 07:06:16 AM UTC 24 |
| Peak memory | 210628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=972146016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.972146016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_23/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all_with_rand_reset/latest |
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