Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1081836	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1057948

1

T1

62

T3

3

T23

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1877904	1			T1	81		T2	1		T3	1
values[0x0]	130910	1			T1	23		T2	1		T3	2
values[0x1]	130970	1			T1	40		T2	1		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	865545	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1274239

1

T1

78

T2

1

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6702	1			T5	1		T6	1		T8	2
valid_sources[0x01]	7003	1			T5	2		T72	2		T14	3
valid_sources[0x02]	6659	1			T8	1		T10	2		T11	1
valid_sources[0x03]	6575	1			T23	2		T6	3		T11	3
valid_sources[0x04]	11872	1			T5	1		T8	2		T11	1
valid_sources[0x05]	7216	1			T8	2		T11	1		T14	1
valid_sources[0x06]	9348	1			T72	2		T14	6		T42	1
valid_sources[0x07]	14377	1			T6	3		T8	2		T11	1
valid_sources[0x08]	6321	1			T6	1		T8	3		T104	1
valid_sources[0x09]	7409	1			T5	1		T7	1		T104	1
valid_sources[0x0a]	9760	1			T6	1		T7	1		T8	1
valid_sources[0x0b]	8016	1			T104	1		T72	1		T42	2
valid_sources[0x0c]	9252	1			T5	3		T6	1		T8	2
valid_sources[0x0d]	11488	1			T6	2		T11	1		T104	2
valid_sources[0x0e]	8495	1			T8	2		T11	1		T104	1
valid_sources[0x0f]	7793	1			T3	1		T8	1		T72	1
valid_sources[0x10]	6734	1			T6	2		T8	2		T11	1
valid_sources[0x11]	6555	1			T11	1		T104	1		T72	2
valid_sources[0x12]	14843	1			T8	1		T11	1		T72	1
valid_sources[0x13]	19483	1			T6	1		T11	1		T104	1
valid_sources[0x14]	6902	1			T6	2		T7	2		T8	1
valid_sources[0x15]	6522	1			T8	2		T11	1		T14	2
valid_sources[0x16]	10709	1			T6	1		T11	2		T14	4
valid_sources[0x17]	6190	1			T104	1		T72	1		T14	2
valid_sources[0x18]	9100	1			T6	1		T8	1		T104	1
valid_sources[0x19]	6733	1			T7	2		T8	1		T11	1
valid_sources[0x1a]	6827	1			T5	4		T8	1		T12	4
valid_sources[0x1b]	6518	1			T5	4		T6	1		T7	1
valid_sources[0x1c]	6663	1			T5	1		T14	4		T42	2
valid_sources[0x1d]	11085	1			T6	1		T8	2		T10	1
valid_sources[0x1e]	6823	1			T6	2		T104	2		T72	1
valid_sources[0x1f]	7775	1			T72	4		T14	2		T16	1
valid_sources[0x20]	15181	1			T5	3		T6	3		T7	1
valid_sources[0x21]	6340	1			T6	1		T10	1		T14	3
valid_sources[0x22]	6901	1			T5	6		T104	1		T48	18
valid_sources[0x23]	8794	1			T14	1		T16	7		T17	15
valid_sources[0x24]	8443	1			T3	1		T8	1		T11	1
valid_sources[0x25]	7805	1			T5	1		T8	3		T11	1
valid_sources[0x26]	8859	1			T6	2		T10	2		T72	2
valid_sources[0x27]	11458	1			T3	1		T8	1		T11	1
valid_sources[0x28]	7414	1			T5	2		T72	2		T14	6
valid_sources[0x29]	10915	1			T6	1		T8	2		T11	1
valid_sources[0x2a]	6409	1			T6	1		T7	1		T8	1
valid_sources[0x2b]	10669	1			T5	4		T8	1		T25	1
valid_sources[0x2c]	18149	1			T10	4		T104	1		T72	1
valid_sources[0x2d]	6792	1			T5	7		T6	2		T8	2
valid_sources[0x2e]	27767	1			T7	1		T8	2		T104	2
valid_sources[0x2f]	6618	1			T6	3		T8	1		T11	1
valid_sources[0x30]	10190	1			T5	2		T104	1		T72	1
valid_sources[0x31]	6176	1			T11	1		T72	1		T14	4
valid_sources[0x32]	9361	1			T6	1		T7	1		T11	1
valid_sources[0x33]	8541	1			T7	1		T8	1		T11	1
valid_sources[0x34]	7267	1			T5	3		T6	1		T8	1
valid_sources[0x35]	8391	1			T23	5		T6	1		T8	1
valid_sources[0x36]	6527	1			T5	2		T6	1		T7	1
valid_sources[0x37]	6397	1			T5	1		T72	2		T14	1
valid_sources[0x38]	7232	1			T5	3		T8	2		T14	3
valid_sources[0x39]	6491	1			T5	1		T14	5		T17	22
valid_sources[0x3a]	12020	1			T5	1		T6	4		T14	2
valid_sources[0x3b]	6668	1			T7	1		T11	1		T104	1
valid_sources[0x3c]	7090	1			T8	1		T11	2		T104	2
valid_sources[0x3d]	6268	1			T5	1		T7	1		T8	3
valid_sources[0x3e]	6425	1			T4	46		T5	2		T6	3
valid_sources[0x3f]	6241	1			T5	2		T6	1		T7	1
valid_sources[0x40]	6829	1			T5	1		T8	1		T104	1
valid_sources[0x41]	6484	1			T6	1		T8	1		T26	1
valid_sources[0x42]	7176	1			T104	1		T13	1		T14	1
valid_sources[0x43]	6508	1			T5	2		T6	1		T10	2
valid_sources[0x44]	9289	1			T6	4		T72	1		T14	2
valid_sources[0x45]	7754	1			T8	2		T14	2		T15	8
valid_sources[0x46]	6744	1			T8	3		T10	1		T11	1
valid_sources[0x47]	6584	1			T6	1		T8	2		T11	1
valid_sources[0x48]	6334	1			T8	1		T11	1		T14	1
valid_sources[0x49]	7389	1			T7	1		T8	1		T104	2
valid_sources[0x4a]	11861	1			T8	1		T104	1		T16	4
valid_sources[0x4b]	11838	1			T11	2		T72	1		T14	2
valid_sources[0x4c]	6306	1			T6	1		T8	1		T11	1
valid_sources[0x4d]	13170	1			T7	1		T8	1		T11	1
valid_sources[0x4e]	7472	1			T5	2		T8	2		T11	2
valid_sources[0x4f]	6545	1			T7	1		T10	1		T11	1
valid_sources[0x50]	6771	1			T8	1		T11	1		T72	1
valid_sources[0x51]	10789	1			T72	1		T42	1		T16	6
valid_sources[0x52]	7328	1			T6	1		T8	1		T11	1
valid_sources[0x53]	6323	1			T6	2		T8	1		T14	2
valid_sources[0x54]	6948	1			T6	1		T7	1		T11	1
valid_sources[0x55]	6210	1			T5	2		T7	1		T8	2
valid_sources[0x56]	6727	1			T104	1		T14	2		T16	3
valid_sources[0x57]	9123	1			T5	2		T14	1		T42	1
valid_sources[0x58]	7629	1			T6	2		T10	1		T11	1
valid_sources[0x59]	7214	1			T6	2		T8	1		T11	1
valid_sources[0x5a]	10943	1			T8	1		T11	1		T104	1
valid_sources[0x5b]	9596	1			T5	1		T6	1		T8	1
valid_sources[0x5c]	7263	1			T8	1		T42	1		T16	2
valid_sources[0x5d]	7333	1			T5	1		T104	1		T15	9
valid_sources[0x5e]	5969	1			T6	1		T8	3		T11	1
valid_sources[0x5f]	6200	1			T5	3		T8	1		T11	2
valid_sources[0x60]	7192	1			T8	2		T11	1		T14	3
valid_sources[0x61]	6474	1			T5	1		T8	1		T42	1
valid_sources[0x62]	6571	1			T11	1		T104	1		T14	3
valid_sources[0x63]	10537	1			T5	2		T11	1		T104	1
valid_sources[0x64]	6668	1			T6	1		T72	2		T14	1
valid_sources[0x65]	6136	1			T5	2		T6	1		T7	1
valid_sources[0x66]	11534	1			T11	1		T14	5		T42	1
valid_sources[0x67]	7418	1			T8	1		T72	2		T17	14
valid_sources[0x68]	8545	1			T6	1		T8	2		T11	1
valid_sources[0x69]	10974	1			T5	3		T7	1		T104	1
valid_sources[0x6a]	6249	1			T6	1		T104	1		T14	1
valid_sources[0x6b]	7762	1			T6	1		T7	1		T11	1
valid_sources[0x6c]	7516	1			T8	1		T14	6		T42	1
valid_sources[0x6d]	9316	1			T11	1		T14	2		T16	6
valid_sources[0x6e]	6892	1			T6	1		T8	2		T11	1
valid_sources[0x6f]	7651	1			T8	1		T10	2		T104	1
valid_sources[0x70]	11465	1			T5	3		T25	1		T11	3
valid_sources[0x71]	7244	1			T5	1		T6	2		T8	1
valid_sources[0x72]	8669	1			T8	2		T11	1		T104	1
valid_sources[0x73]	6346	1			T5	1		T6	1		T104	1
valid_sources[0x74]	6921	1			T42	1		T16	1		T17	8
valid_sources[0x75]	6662	1			T25	2		T11	1		T104	2
valid_sources[0x76]	6771	1			T5	1		T8	2		T10	1
valid_sources[0x77]	6320	1			T6	1		T8	1		T16	6
valid_sources[0x78]	7332	1			T6	1		T11	2		T72	3
valid_sources[0x79]	6832	1			T11	1		T104	1		T14	2
valid_sources[0x7a]	11515	1			T6	3		T8	1		T10	4
valid_sources[0x7b]	6505	1			T5	1		T8	1		T11	2
valid_sources[0x7c]	6231	1			T6	1		T8	1		T10	1
valid_sources[0x7d]	6494	1			T5	1		T6	1		T7	1
valid_sources[0x7e]	11480	1			T104	2		T14	4		T42	2
valid_sources[0x7f]	6309	1			T5	1		T6	2		T8	1
valid_sources[0x80]	7231	1			T6	3		T10	1		T14	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

934526

1

T1

42

T5

36

T6

35

values[0x0]

all_enables

biggest_size

71663

1

T1

10

T3

2

T23

2

values[0x1]

all_enables

biggest_size

51759

1

T1

10

T3

1

T4

15