Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
84.44	84.44	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	84.44	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	7	38	84.44

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	6	10	62.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	26696	1			T16	8		T17	10		T18	10
auto[PWRUP]	96	1			T56	2		T52	1		T54	1
auto[ONEST_0]	56	1			T56	3		T187	1		T188	1
auto[ONEST_021]	15	1			T53	2		T54	1		T55	1
auto[ONEST_1]	70	1			T53	1		T56	1		T57	3
auto[ONEST_DONE]	3	1			T189	1		T190	1		T191	1
auto[LP_0]	95	1			T53	4		T56	2		T52	1
auto[LP_021]	28	1			T53	1		T54	1		T187	1
auto[LP_1]	138	1			T56	1		T57	2		T54	1
auto[LP_EVAL]	63	1			T52	1		T187	1		T188	2
auto[LP_SLP]	405	1			T53	9		T56	7		T52	3
auto[LP_PWRUP]	28	1			T53	1		T56	1		T52	1
auto[NP_0]	135	1			T53	3		T57	2		T54	3
auto[NP_021]	27	1			T53	1		T57	1		T55	1
auto[NP_1]	148	1			T56	2		T52	1		T57	1
auto[NP_EVAL]	30	1			T53	1		T187	1		T59	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

5

1

T60

1

T192

1

T193

1

min

26238

1

T16

8

T17

10

T18

10

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	26248	1			T16	8		T17	10		T18	10
pow[0x1]	4	1			T53	1		T194	1		T189	1
pow[0x2]	20	1			T187	1		T195	1		T59	1
pow[0x3]	24	1			T56	1		T52	2		T57	1
pow[0x4]	62	1			T56	1		T54	1		T55	3
pow[0x5]	94	1			T56	1		T57	2		T54	1
pow[0x6]	235	1			T53	5		T56	3		T57	4
pow[0x7]	463	1			T30	1		T53	5		T56	6

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

158

1

T53

1

T52

2

T57

2

min

25871

1

T16

8

T17

10

T18

10

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	6	10	62.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	25871	1			T16	8		T17	10		T18	10
pow[0x7]	1	1			T196	1		-	-		-	-
pow[0x8]	2	1			T190	1		T197	1		-	-
pow[0x9]	8	1			T54	1		T55	1		T198	1
pow[0xa]	21	1			T53	1		T56	1		T195	1
pow[0xb]	28	1			T53	1		T55	2		T58	2
pow[0xc]	56	1			T53	1		T56	1		T57	1
pow[0xd]	114	1			T53	1		T56	2		T57	3
pow[0xe]	246	1			T53	5		T56	10		T52	2
pow[0xf]	507	1			T53	6		T56	7		T52	6