Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2105	1			T2	20		T24	20		T8	5
auto[PWRUP]	115	1			T13	1		T15	1		T31	1
auto[ONEST_0]	57	1			T46	1		T53	1		T56	2
auto[ONEST_021]	20	1			T53	1		T187	1		T195	1
auto[ONEST_1]	68	1			T13	1		T14	1		T47	1
auto[ONEST_DONE]	2	1			T344	1		T345	1		-	-
auto[LP_0]	120	1			T13	1		T53	4		T56	1
auto[LP_021]	22	1			T54	1		T55	1		T187	1
auto[LP_1]	131	1			T15	1		T30	1		T31	1
auto[LP_EVAL]	49	1			T15	1		T30	1		T53	1
auto[LP_SLP]	476	1			T15	2		T22	2		T53	7
auto[LP_PWRUP]	30	1			T15	1		T56	2		T194	1
auto[NP_0]	191	1			T8	3		T13	1		T14	3
auto[NP_021]	42	1			T52	1		T54	1		T55	1
auto[NP_1]	156	1			T15	1		T22	1		T30	1
auto[NP_EVAL]	24	1			T14	1		T15	1		T46	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

11

1

T56

1

T188

1

T194

2

min

1823

1

T2

20

T24

20

T8

8

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1834	1			T2	20		T24	20		T8	8
pow[0x1]	9	1			T57	1		T314	1		T346	1
pow[0x2]	14	1			T15	1		T198	1		T58	1
pow[0x3]	26	1			T52	2		T54	1		T55	1
pow[0x4]	66	1			T53	1		T56	1		T52	1
pow[0x5]	118	1			T15	1		T30	2		T53	1
pow[0x6]	217	1			T46	1		T53	1		T56	3
pow[0x7]	436	1			T53	6		T56	8		T52	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

185

1

T53

7

T56

3

T57

1

min

1311

1

T2

20

T24

20

T8

5

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1323	1			T2	20		T24	20		T8	6
pow[0x1]	13	1			T8	1		T14	1		T32	1
pow[0x2]	11	1			T8	1		T15	2		T22	1
pow[0x3]	21	1			T14	2		T22	2		T47	1
pow[0x4]	15	1			T30	1		T31	1		T47	2
pow[0x5]	2	1			T198	1		T347	1		-	-
pow[0x7]	1	1			T198	1		-	-		-	-
pow[0x8]	4	1			T194	1		T58	1		T348	1
pow[0x9]	7	1			T195	1		T271	1		T349	1
pow[0xa]	14	1			T53	1		T55	1		T187	1
pow[0xb]	34	1			T56	1		T57	2		T194	1
pow[0xc]	63	1			T46	1		T53	1		T56	2
pow[0xd]	133	1			T30	1		T53	1		T56	5
pow[0xe]	249	1			T53	5		T56	4		T52	2
pow[0xf]	506	1			T53	7		T56	4		T52	9