Module Definition
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Module : prim_subreg_arb
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv

Module self-instances :
NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
tb.dut.u_reg.u_adc_chn_val_0_adc_chn_value_ext_0.wr_en_data_arb 0.00 0.00
tb.dut.u_reg.u_adc_chn_val_0_adc_chn_value_intr_ext_0.wr_en_data_arb 0.00 0.00
tb.dut.u_reg.u_adc_chn_val_1_adc_chn_value_ext_1.wr_en_data_arb 0.00 0.00
tb.dut.u_reg.u_adc_chn_val_1_adc_chn_value_intr_ext_1.wr_en_data_arb 0.00 0.00
tb.dut.u_reg.u_intr_state.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_intr_enable.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_en_ctl_adc_enable.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_en_ctl_oneshot_mode.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_pd_ctl_lp_mode.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_pd_ctl_pwrup_time.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_pd_ctl_wakeup_time.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_lp_sample_ctl.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_sample_ctl.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_fsm_rst.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_min_v_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cond_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_max_v_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_min_v_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cond_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_max_v_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_min_v_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cond_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_max_v_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_en_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_min_v_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cond_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_max_v_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_en_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_min_v_4.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cond_4.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_max_v_4.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_en_4.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_min_v_5.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cond_5.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_max_v_5.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_en_5.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_min_v_6.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cond_6.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_max_v_6.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_en_6.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_min_v_7.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cond_7.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_max_v_7.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_en_7.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_min_v_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cond_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_max_v_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_min_v_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cond_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_max_v_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_min_v_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cond_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_max_v_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_en_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_min_v_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cond_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_max_v_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_en_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_min_v_4.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cond_4.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_max_v_4.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_en_4.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_min_v_5.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cond_5.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_max_v_5.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_en_5.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_min_v_6.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cond_6.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_max_v_6.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_en_6.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_min_v_7.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cond_7.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_max_v_7.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_en_7.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn_val_0_adc_chn_value_0.wr_en_data_arb 100.00 100.00
tb.dut.u_reg.u_adc_chn_val_0_adc_chn_value_intr_0.wr_en_data_arb 100.00 100.00
tb.dut.u_reg.u_adc_chn_val_1_adc_chn_value_1.wr_en_data_arb 100.00 100.00
tb.dut.u_reg.u_adc_chn_val_1_adc_chn_value_intr_1.wr_en_data_arb 100.00 100.00
tb.dut.u_reg.u_adc_wakeup_ctl_match_en.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_wakeup_ctl_trans_en.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_filter_status_match.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_filter_status_trans.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_intr_ctl_match_en.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_intr_ctl_trans_en.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_intr_ctl_oneshot_en.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_adc_intr_status_match.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_intr_status_trans.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_intr_status_oneshot.wr_en_data_arb 100.00 100.00 100.00

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=1,Mubi=0 + DW=2,SwAccess=1,Mubi=0 + DW=10,SwAccess=1,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
50.00 50.00
tb.dut.u_reg.u_intr_state.wr_en_data_arb

SCORELINE
0.00 0.00
tb.dut.u_reg.u_adc_chn_val_0_adc_chn_value_ext_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn_val_0_adc_chn_value_0.wr_en_data_arb

SCORELINE
0.00 0.00
tb.dut.u_reg.u_adc_chn_val_0_adc_chn_value_intr_ext_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn_val_0_adc_chn_value_intr_0.wr_en_data_arb

SCORELINE
0.00 0.00
tb.dut.u_reg.u_adc_chn_val_1_adc_chn_value_ext_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn_val_1_adc_chn_value_1.wr_en_data_arb

SCORELINE
0.00 0.00
tb.dut.u_reg.u_adc_chn_val_1_adc_chn_value_intr_ext_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn_val_1_adc_chn_value_intr_1.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300

42 end else if (SwAccess == SwAccessRO) begin : gen_ro 43 1/1 assign wr_en = de; Tests: T1 T2 T3  44 1/1 assign wr_data = d; Tests: T1 T2 T3  45 // Unused we, wd, q - Prevent lint errors. 46 logic unused_we; 47 logic [DW-1:0] unused_wd; 48 logic [DW-1:0] unused_q; 49 //VCS coverage off 50 // pragma coverage off 51 unreachable assign unused_we = we; 52 unreachable assign unused_wd = wd; 53 unreachable assign unused_q = q;

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 + DW=4,SwAccess=0,Mubi=0 + DW=24,SwAccess=0,Mubi=0 + DW=8,SwAccess=0,Mubi=0 + DW=16,SwAccess=0,Mubi=0 + DW=10,SwAccess=0,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_en_ctl_adc_enable.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_en_ctl_oneshot_mode.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_pd_ctl_lp_mode.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_pd_ctl_pwrup_time.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_pd_ctl_wakeup_time.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_lp_sample_ctl.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_sample_ctl.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_fsm_rst.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_min_v_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cond_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_max_v_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_en_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_min_v_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cond_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_max_v_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_en_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_min_v_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cond_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_max_v_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_en_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_min_v_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cond_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_max_v_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_en_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_min_v_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cond_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_max_v_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_en_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_min_v_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cond_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_max_v_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_en_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_min_v_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cond_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_max_v_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_en_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_min_v_7.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cond_7.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_max_v_7.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_en_7.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_min_v_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cond_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_max_v_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_en_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_min_v_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cond_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_max_v_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_en_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_min_v_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cond_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_max_v_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_en_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_min_v_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cond_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_max_v_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_en_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_min_v_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cond_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_max_v_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_en_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_min_v_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cond_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_max_v_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_en_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_min_v_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cond_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_max_v_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_en_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_min_v_7.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cond_7.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_max_v_7.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_en_7.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_wakeup_ctl_match_en.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_wakeup_ctl_trans_en.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_intr_ctl_match_en.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_intr_ctl_trans_en.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_intr_ctl_oneshot_en.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T1 T2 T3  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Line Coverage for Module : prim_subreg_arb ( parameter DW=8,SwAccess=3,Mubi=0 + DW=1,SwAccess=3,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_filter_status_match.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_filter_status_trans.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_intr_status_match.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_intr_status_trans.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_intr_status_oneshot.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN11011100.00

87 // If both try to set/clr at the same bit pos, SW wins. 88 1/1 assign wr_en = we | de; Tests: T1 T2 T3  89 if (Mubi) begin : gen_mubi 90 if (DW == 4) begin : gen_mubi4 91 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 92 (we ? prim_mubi_pkg::mubi4_t'(~wd) : 93 prim_mubi_pkg::MuBi4True)); 94 end else if (DW == 8) begin : gen_mubi8 95 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 96 (we ? prim_mubi_pkg::mubi8_t'(~wd) : 97 prim_mubi_pkg::MuBi8True)); 98 end else if (DW == 12) begin : gen_mubi12 99 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 100 (we ? prim_mubi_pkg::mubi12_t'(~wd) : 101 prim_mubi_pkg::MuBi12True)); 102 end else if (DW == 16) begin : gen_mubi16 103 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 104 (we ? prim_mubi_pkg::mubi16_t'(~wd) : 105 prim_mubi_pkg::MuBi16True)); 106 end else begin : gen_invalid_mubi 107 $error("%m: Invalid width for MuBi"); 108 end 109 end else begin : gen_non_mubi 110 1/1 assign wr_data = (de ? d : q) & (we ? ~wd : '1); Tests: T1 T2 T3 

Cond Coverage for Module : prim_subreg_arb ( parameter DW=8,SwAccess=3,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_filter_status_match.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_intr_status_match.wr_en_data_arb

TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT14,T16,T17
10CoveredT1,T5,T6

Cond Coverage for Module : prim_subreg_arb ( parameter DW=10,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_min_v_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_max_v_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_min_v_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_max_v_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_min_v_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_max_v_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_min_v_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_max_v_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_min_v_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_max_v_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_min_v_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_max_v_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_min_v_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_max_v_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_min_v_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_max_v_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_min_v_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_max_v_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_min_v_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_max_v_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_min_v_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_max_v_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_min_v_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_max_v_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_min_v_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_max_v_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_min_v_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_max_v_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_min_v_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_max_v_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_min_v_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_max_v_7.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT8,T13,T14

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T13,T14

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T13,T14

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_en_ctl_adc_enable.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_en_ctl_oneshot_mode.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_pd_ctl_lp_mode.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_fsm_rst.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cond_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cond_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cond_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_en_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cond_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_en_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cond_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_en_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cond_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_en_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cond_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_en_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cond_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_en_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cond_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cond_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cond_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_en_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cond_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_en_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cond_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_en_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cond_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_en_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cond_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_en_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cond_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_en_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_wakeup_ctl_trans_en.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_intr_ctl_trans_en.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_intr_ctl_oneshot_en.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T4,T5

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_filter_status_trans.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_intr_status_trans.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_intr_status_oneshot.wr_en_data_arb

TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T5,T6
10CoveredT1,T5,T6

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T5,T6
11CoveredT1,T5,T6

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T5,T6

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T5,T6

Cond Coverage for Module : prim_subreg_arb ( parameter DW=16,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_sample_ctl.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT2,T3,T23

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T23

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T23

Cond Coverage for Module : prim_subreg_arb ( parameter DW=4,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_pd_ctl_pwrup_time.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T4,T5

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

Cond Coverage for Module : prim_subreg_arb ( parameter DW=8,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_lp_sample_ctl.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_wakeup_ctl_match_en.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_intr_ctl_match_en.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg_arb ( parameter DW=24,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_pd_ctl_wakeup_time.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T4,T5

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

Branch Coverage for Module : prim_subreg_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3