Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2369	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2273	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2117	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2314	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2247	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2245	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2507	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2296	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2252	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2413	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2314	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2307	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2438	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2067	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2340	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2398	0	0
adc_en_ctl_rd_A	2147483647	1808	0	0
adc_fsm_rst_rd_A	2147483647	1648	0	0
adc_intr_ctl_rd_A	2147483647	2285	0	0
adc_lp_sample_ctl_rd_A	2147483647	1608	0	0
adc_pd_ctl_rd_A	2147483647	1974	0	0
adc_sample_ctl_rd_A	2147483647	1621	0	0
adc_wakeup_ctl_rd_A	2147483647	1751	0	0
intr_enable_rd_A	2147483647	2164	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2369	0	0
T8	139754	20	0	0
T9	501631	0	0	0
T10	110921	0	0	0
T11	889676	0	0	0
T12	582064	0	0	0
T25	10073	0	0	0
T26	12172	0	0	0
T27	387520	0	0	0
T28	195467	0	0	0
T29	746984	0	0	0
T30	0	13	0	0
T31	0	52	0	0
T32	0	27	0	0
T33	0	32	0	0
T34	0	39	0	0
T35	0	16	0	0
T36	0	15	0	0
T37	0	28	0	0
T38	0	17	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2273	0	0
T8	139754	35	0	0
T9	501631	0	0	0
T10	110921	0	0	0
T11	889676	0	0	0
T12	582064	0	0	0
T25	10073	0	0	0
T26	12172	0	0	0
T27	387520	0	0	0
T28	195467	0	0	0
T29	746984	0	0	0
T30	0	18	0	0
T31	0	29	0	0
T32	0	12	0	0
T33	0	45	0	0
T34	0	54	0	0
T35	0	11	0	0
T36	0	13	0	0
T37	0	35	0	0
T38	0	9	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2117	0	0
T8	139754	20	0	0
T9	501631	0	0	0
T10	110921	0	0	0
T11	889676	0	0	0
T12	582064	0	0	0
T25	10073	0	0	0
T26	12172	0	0	0
T27	387520	0	0	0
T28	195467	0	0	0
T29	746984	0	0	0
T30	0	16	0	0
T31	0	18	0	0
T32	0	24	0	0
T33	0	30	0	0
T34	0	38	0	0
T35	0	3	0	0
T36	0	4	0	0
T37	0	23	0	0
T38	0	22	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2314	0	0
T8	139754	17	0	0
T9	501631	0	0	0
T10	110921	0	0	0
T11	889676	0	0	0
T12	582064	0	0	0
T25	10073	0	0	0
T26	12172	0	0	0
T27	387520	0	0	0
T28	195467	0	0	0
T29	746984	0	0	0
T30	0	27	0	0
T31	0	48	0	0
T32	0	13	0	0
T33	0	29	0	0
T34	0	36	0	0
T35	0	3	0	0
T36	0	18	0	0
T37	0	47	0	0
T38	0	18	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2247	0	0
T8	139754	19	0	0
T9	501631	0	0	0
T10	110921	0	0	0
T11	889676	0	0	0
T12	582064	0	0	0
T25	10073	0	0	0
T26	12172	0	0	0
T27	387520	0	0	0
T28	195467	0	0	0
T29	746984	0	0	0
T30	0	13	0	0
T31	0	37	0	0
T32	0	16	0	0
T33	0	34	0	0
T34	0	46	0	0
T35	0	8	0	0
T36	0	18	0	0
T37	0	43	0	0
T38	0	10	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2245	0	0
T8	139754	19	0	0
T9	501631	0	0	0
T10	110921	0	0	0
T11	889676	0	0	0
T12	582064	0	0	0
T25	10073	0	0	0
T26	12172	0	0	0
T27	387520	0	0	0
T28	195467	0	0	0
T29	746984	0	0	0
T30	0	11	0	0
T31	0	34	0	0
T32	0	25	0	0
T33	0	32	0	0
T34	0	51	0	0
T35	0	11	0	0
T36	0	10	0	0
T37	0	35	0	0
T38	0	17	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2507	0	0
T8	139754	18	0	0
T9	501631	0	0	0
T10	110921	0	0	0
T11	889676	0	0	0
T12	582064	0	0	0
T25	10073	0	0	0
T26	12172	0	0	0
T27	387520	0	0	0
T28	195467	0	0	0
T29	746984	0	0	0
T30	0	17	0	0
T31	0	32	0	0
T32	0	24	0	0
T33	0	39	0	0
T34	0	26	0	0
T35	0	16	0	0
T36	0	11	0	0
T37	0	48	0	0
T38	0	12	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2296	0	0
T8	139754	11	0	0
T9	501631	0	0	0
T10	110921	0	0	0
T11	889676	0	0	0
T12	582064	0	0	0
T25	10073	0	0	0
T26	12172	0	0	0
T27	387520	0	0	0
T28	195467	0	0	0
T29	746984	0	0	0
T30	0	17	0	0
T31	0	36	0	0
T32	0	13	0	0
T33	0	41	0	0
T34	0	39	0	0
T35	0	10	0	0
T36	0	5	0	0
T37	0	31	0	0
T38	0	11	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2252	0	0
T8	139754	28	0	0
T9	501631	0	0	0
T10	110921	0	0	0
T11	889676	0	0	0
T12	582064	0	0	0
T25	10073	0	0	0
T26	12172	0	0	0
T27	387520	0	0	0
T28	195467	0	0	0
T29	746984	0	0	0
T30	0	14	0	0
T31	0	31	0	0
T32	0	17	0	0
T33	0	24	0	0
T34	0	45	0	0
T35	0	13	0	0
T36	0	4	0	0
T37	0	33	0	0
T39	0	5	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2413	0	0
T8	139754	21	0	0
T9	501631	0	0	0
T10	110921	0	0	0
T11	889676	0	0	0
T12	582064	0	0	0
T25	10073	0	0	0
T26	12172	0	0	0
T27	387520	0	0	0
T28	195467	0	0	0
T29	746984	0	0	0
T30	0	7	0	0
T31	0	42	0	0
T32	0	16	0	0
T33	0	33	0	0
T34	0	60	0	0
T35	0	8	0	0
T37	0	31	0	0
T38	0	12	0	0
T39	0	29	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2314	0	0
T8	139754	26	0	0
T9	501631	0	0	0
T10	110921	0	0	0
T11	889676	0	0	0
T12	582064	0	0	0
T25	10073	0	0	0
T26	12172	0	0	0
T27	387520	0	0	0
T28	195467	0	0	0
T29	746984	0	0	0
T30	0	28	0	0
T31	0	41	0	0
T32	0	22	0	0
T33	0	36	0	0
T34	0	44	0	0
T35	0	8	0	0
T36	0	15	0	0
T37	0	40	0	0
T38	0	21	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2307	0	0
T8	139754	18	0	0
T9	501631	0	0	0
T10	110921	0	0	0
T11	889676	0	0	0
T12	582064	0	0	0
T25	10073	0	0	0
T26	12172	0	0	0
T27	387520	0	0	0
T28	195467	0	0	0
T29	746984	0	0	0
T30	0	26	0	0
T31	0	20	0	0
T32	0	18	0	0
T33	0	41	0	0
T34	0	42	0	0
T35	0	25	0	0
T36	0	17	0	0
T37	0	36	0	0
T38	0	3	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2438	0	0
T8	139754	21	0	0
T9	501631	0	0	0
T10	110921	0	0	0
T11	889676	0	0	0
T12	582064	0	0	0
T25	10073	0	0	0
T26	12172	0	0	0
T27	387520	0	0	0
T28	195467	0	0	0
T29	746984	0	0	0
T30	0	19	0	0
T31	0	33	0	0
T32	0	24	0	0
T33	0	39	0	0
T34	0	40	0	0
T35	0	11	0	0
T36	0	11	0	0
T37	0	48	0	0
T38	0	4	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2067	0	0
T8	139754	18	0	0
T9	501631	0	0	0
T10	110921	0	0	0
T11	889676	0	0	0
T12	582064	0	0	0
T25	10073	0	0	0
T26	12172	0	0	0
T27	387520	0	0	0
T28	195467	0	0	0
T29	746984	0	0	0
T30	0	17	0	0
T31	0	46	0	0
T32	0	12	0	0
T33	0	37	0	0
T34	0	54	0	0
T35	0	10	0	0
T36	0	10	0	0
T37	0	46	0	0
T39	0	10	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2340	0	0
T8	139754	27	0	0
T9	501631	0	0	0
T10	110921	0	0	0
T11	889676	0	0	0
T12	582064	0	0	0
T25	10073	0	0	0
T26	12172	0	0	0
T27	387520	0	0	0
T28	195467	0	0	0
T29	746984	0	0	0
T30	0	12	0	0
T31	0	35	0	0
T32	0	17	0	0
T33	0	40	0	0
T34	0	28	0	0
T35	0	20	0	0
T36	0	5	0	0
T37	0	49	0	0
T38	0	18	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2398	0	0
T8	139754	19	0	0
T9	501631	0	0	0
T10	110921	0	0	0
T11	889676	0	0	0
T12	582064	0	0	0
T25	10073	0	0	0
T26	12172	0	0	0
T27	387520	0	0	0
T28	195467	0	0	0
T29	746984	0	0	0
T30	0	20	0	0
T31	0	40	0	0
T32	0	29	0	0
T33	0	24	0	0
T34	0	27	0	0
T35	0	14	0	0
T36	0	10	0	0
T37	0	41	0	0
T38	0	18	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1808	0	0
T8	139754	18	0	0
T9	501631	0	0	0
T10	110921	0	0	0
T11	889676	0	0	0
T12	582064	0	0	0
T25	10073	0	0	0
T26	12172	0	0	0
T27	387520	0	0	0
T28	195467	0	0	0
T29	746984	0	0	0
T30	0	22	0	0
T31	0	40	0	0
T32	0	20	0	0
T33	0	29	0	0
T34	0	38	0	0
T35	0	10	0	0
T36	0	4	0	0
T37	0	23	0	0
T38	0	4	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1648	0	0
T8	139754	20	0	0
T9	501631	0	0	0
T10	110921	0	0	0
T11	889676	0	0	0
T12	582064	0	0	0
T25	10073	0	0	0
T26	12172	0	0	0
T27	387520	0	0	0
T28	195467	0	0	0
T29	746984	0	0	0
T30	0	11	0	0
T31	0	45	0	0
T32	0	18	0	0
T33	0	48	0	0
T34	0	43	0	0
T35	0	5	0	0
T36	0	12	0	0
T37	0	33	0	0
T38	0	4	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2285	0	0
T8	139754	14	0	0
T9	501631	0	0	0
T10	110921	0	0	0
T11	889676	0	0	0
T12	582064	0	0	0
T25	10073	0	0	0
T26	12172	0	0	0
T27	387520	0	0	0
T28	195467	0	0	0
T29	746984	0	0	0
T30	0	22	0	0
T31	0	33	0	0
T32	0	18	0	0
T33	0	38	0	0
T34	0	22	0	0
T35	0	7	0	0
T36	0	1	0	0
T37	0	60	0	0
T38	0	4	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1608	0	0
T8	139754	23	0	0
T9	501631	0	0	0
T10	110921	0	0	0
T11	889676	0	0	0
T12	582064	0	0	0
T25	10073	0	0	0
T26	12172	0	0	0
T27	387520	0	0	0
T28	195467	0	0	0
T29	746984	0	0	0
T30	0	24	0	0
T31	0	54	0	0
T32	0	19	0	0
T33	0	34	0	0
T34	0	31	0	0
T35	0	13	0	0
T36	0	5	0	0
T37	0	45	0	0
T38	0	16	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1974	0	0
T8	139754	21	0	0
T9	501631	0	0	0
T10	110921	0	0	0
T11	889676	0	0	0
T12	582064	0	0	0
T25	10073	0	0	0
T26	12172	0	0	0
T27	387520	0	0	0
T28	195467	0	0	0
T29	746984	0	0	0
T30	0	23	0	0
T31	0	41	0	0
T32	0	26	0	0
T33	0	21	0	0
T34	0	32	0	0
T35	0	4	0	0
T36	0	8	0	0
T37	0	33	0	0
T38	0	15	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1621	0	0
T8	139754	21	0	0
T9	501631	0	0	0
T10	110921	0	0	0
T11	889676	0	0	0
T12	582064	0	0	0
T25	10073	0	0	0
T26	12172	0	0	0
T27	387520	0	0	0
T28	195467	0	0	0
T29	746984	0	0	0
T30	0	27	0	0
T31	0	46	0	0
T32	0	28	0	0
T33	0	37	0	0
T34	0	26	0	0
T35	0	15	0	0
T36	0	21	0	0
T37	0	27	0	0
T38	0	12	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1751	0	0
T8	139754	26	0	0
T9	501631	0	0	0
T10	110921	0	0	0
T11	889676	0	0	0
T12	582064	0	0	0
T25	10073	0	0	0
T26	12172	0	0	0
T27	387520	0	0	0
T28	195467	0	0	0
T29	746984	0	0	0
T30	0	16	0	0
T31	0	37	0	0
T32	0	19	0	0
T33	0	35	0	0
T34	0	38	0	0
T35	0	4	0	0
T36	0	6	0	0
T37	0	45	0	0
T38	0	10	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2164	0	0
T8	139754	24	0	0
T9	501631	0	0	0
T10	110921	0	0	0
T11	889676	0	0	0
T12	582064	0	0	0
T25	10073	0	0	0
T26	12172	0	0	0
T27	387520	0	0	0
T28	195467	0	0	0
T29	746984	0	0	0
T30	0	19	0	0
T31	0	71	0	0
T32	0	49	0	0
T33	0	20	0	0
T34	0	33	0	0
T35	0	14	0	0
T36	0	3	0	0
T37	0	41	0	0
T38	0	1	0	0