| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.70 | 99.07 | 96.67 | 100.00 | 100.00 | 98.82 | 98.33 | 90.99 |
| T341 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all.2302792478 | Oct 12 01:41:50 AM UTC 24 | Oct 12 02:36:51 AM UTC 24 | 1469520526831 ps | ||
| T801 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1681548232 | Oct 12 02:15:02 AM UTC 24 | Oct 12 02:45:00 AM UTC 24 | 589350691587 ps | ||
| T108 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2372273704 | Oct 12 12:36:36 AM UTC 24 | Oct 12 12:36:38 AM UTC 24 | 689032330 ps | ||
| T802 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.382023511 | Oct 12 12:36:36 AM UTC 24 | Oct 12 12:36:39 AM UTC 24 | 399895052 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3507320779 | Oct 12 12:36:36 AM UTC 24 | Oct 12 12:36:40 AM UTC 24 | 326377845 ps | ||
| T803 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.369388674 | Oct 12 12:37:18 AM UTC 24 | Oct 12 12:37:21 AM UTC 24 | 338238903 ps | ||
| T86 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.964986581 | Oct 12 12:36:37 AM UTC 24 | Oct 12 12:36:40 AM UTC 24 | 660066794 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2926505144 | Oct 12 12:36:36 AM UTC 24 | Oct 12 12:36:40 AM UTC 24 | 492396068 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3064658302 | Oct 12 12:36:37 AM UTC 24 | Oct 12 12:36:40 AM UTC 24 | 567018195 ps | ||
| T804 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.3598377990 | Oct 12 12:36:38 AM UTC 24 | Oct 12 12:36:41 AM UTC 24 | 389089795 ps | ||
| T87 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1805632618 | Oct 12 12:36:40 AM UTC 24 | Oct 12 12:36:42 AM UTC 24 | 553342287 ps | ||
| T123 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2270341954 | Oct 12 12:36:38 AM UTC 24 | Oct 12 12:36:43 AM UTC 24 | 411384537 ps | ||
| T109 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1022587825 | Oct 12 12:36:38 AM UTC 24 | Oct 12 12:36:43 AM UTC 24 | 1037084188 ps | ||
| T128 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1325482735 | Oct 12 12:36:37 AM UTC 24 | Oct 12 12:36:43 AM UTC 24 | 887788954 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3299917665 | Oct 12 12:36:36 AM UTC 24 | Oct 12 12:36:43 AM UTC 24 | 4571531853 ps | ||
| T805 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.3874035771 | Oct 12 12:36:41 AM UTC 24 | Oct 12 12:36:44 AM UTC 24 | 448169714 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2208810563 | Oct 12 12:36:41 AM UTC 24 | Oct 12 12:36:44 AM UTC 24 | 1162298766 ps | ||
| T129 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2867386346 | Oct 12 12:36:41 AM UTC 24 | Oct 12 12:36:45 AM UTC 24 | 850739354 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1703555608 | Oct 12 12:36:42 AM UTC 24 | Oct 12 12:36:45 AM UTC 24 | 429377962 ps | ||
| T110 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3504491954 | Oct 12 12:36:39 AM UTC 24 | Oct 12 12:36:47 AM UTC 24 | 980068475 ps | ||
| T88 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.4163224210 | Oct 12 12:36:44 AM UTC 24 | Oct 12 12:36:47 AM UTC 24 | 474668160 ps | ||
| T111 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.637845867 | Oct 12 12:36:43 AM UTC 24 | Oct 12 12:36:47 AM UTC 24 | 648321672 ps | ||
| T125 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2468351266 | Oct 12 12:36:40 AM UTC 24 | Oct 12 12:36:48 AM UTC 24 | 2319644411 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.20938024 | Oct 12 12:36:37 AM UTC 24 | Oct 12 12:36:49 AM UTC 24 | 8291204437 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2489728958 | Oct 12 12:36:44 AM UTC 24 | Oct 12 12:36:50 AM UTC 24 | 552409694 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1981001322 | Oct 12 12:36:44 AM UTC 24 | Oct 12 12:36:50 AM UTC 24 | 4409831202 ps | ||
| T806 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.3500336668 | Oct 12 12:36:49 AM UTC 24 | Oct 12 12:36:51 AM UTC 24 | 382950433 ps | ||
| T98 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.972413789 | Oct 12 12:36:49 AM UTC 24 | Oct 12 12:36:52 AM UTC 24 | 525164691 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1521376396 | Oct 12 12:36:49 AM UTC 24 | Oct 12 12:36:52 AM UTC 24 | 329384390 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_errors.513778769 | Oct 12 12:36:49 AM UTC 24 | Oct 12 12:36:53 AM UTC 24 | 397264327 ps | ||
| T112 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2219459048 | Oct 12 12:36:51 AM UTC 24 | Oct 12 12:36:54 AM UTC 24 | 880379807 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.592336614 | Oct 12 12:36:41 AM UTC 24 | Oct 12 12:36:54 AM UTC 24 | 5007385162 ps | ||
| T807 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2433330824 | Oct 12 12:36:52 AM UTC 24 | Oct 12 12:36:55 AM UTC 24 | 313317039 ps | ||
| T808 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_intr_test.1696702307 | Oct 12 12:36:51 AM UTC 24 | Oct 12 12:36:55 AM UTC 24 | 477986264 ps | ||
| T113 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.542333127 | Oct 12 12:36:49 AM UTC 24 | Oct 12 12:36:56 AM UTC 24 | 1164880055 ps | ||
| T114 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2905381163 | Oct 12 12:36:49 AM UTC 24 | Oct 12 12:36:57 AM UTC 24 | 819454272 ps | ||
| T809 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1088112171 | Oct 12 12:36:54 AM UTC 24 | Oct 12 12:36:57 AM UTC 24 | 856685638 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.4201531973 | Oct 12 12:36:55 AM UTC 24 | Oct 12 12:36:57 AM UTC 24 | 479652292 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1030934971 | Oct 12 12:36:55 AM UTC 24 | Oct 12 12:36:58 AM UTC 24 | 439233022 ps | ||
| T810 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_intr_test.2786850345 | Oct 12 12:36:56 AM UTC 24 | Oct 12 12:36:58 AM UTC 24 | 463026125 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1998545888 | Oct 12 12:36:54 AM UTC 24 | Oct 12 12:37:00 AM UTC 24 | 5175843950 ps | ||
| T126 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_rw.490205150 | Oct 12 12:36:57 AM UTC 24 | Oct 12 12:37:00 AM UTC 24 | 371879410 ps | ||
| T811 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.155793172 | Oct 12 12:36:58 AM UTC 24 | Oct 12 12:37:01 AM UTC 24 | 605985353 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.529103825 | Oct 12 12:36:37 AM UTC 24 | Oct 12 12:37:02 AM UTC 24 | 4477308637 ps | ||
| T812 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_intr_test.764927382 | Oct 12 12:36:59 AM UTC 24 | Oct 12 12:37:03 AM UTC 24 | 290918832 ps | ||
| T127 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.573573598 | Oct 12 12:36:49 AM UTC 24 | Oct 12 12:37:03 AM UTC 24 | 2729777963 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2077692864 | Oct 12 12:36:56 AM UTC 24 | Oct 12 12:37:03 AM UTC 24 | 3643055718 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2071495096 | Oct 12 12:36:50 AM UTC 24 | Oct 12 12:37:03 AM UTC 24 | 8150137935 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_errors.780147260 | Oct 12 12:36:58 AM UTC 24 | Oct 12 12:37:04 AM UTC 24 | 445858371 ps | ||
| T813 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.459150665 | Oct 12 12:36:58 AM UTC 24 | Oct 12 12:37:04 AM UTC 24 | 4929274683 ps | ||
| T115 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1240690075 | Oct 12 12:37:00 AM UTC 24 | Oct 12 12:37:04 AM UTC 24 | 419246528 ps | ||
| T814 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.970903052 | Oct 12 12:36:44 AM UTC 24 | Oct 12 12:37:05 AM UTC 24 | 4031108662 ps | ||
| T815 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3422088799 | Oct 12 12:37:03 AM UTC 24 | Oct 12 12:37:06 AM UTC 24 | 634995037 ps | ||
| T348 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2865772359 | Oct 12 12:36:59 AM UTC 24 | Oct 12 12:37:06 AM UTC 24 | 4385938720 ps | ||
| T816 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_intr_test.1507553829 | Oct 12 12:37:04 AM UTC 24 | Oct 12 12:37:06 AM UTC 24 | 304129315 ps | ||
| T817 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2727541558 | Oct 12 12:37:04 AM UTC 24 | Oct 12 12:37:07 AM UTC 24 | 495783715 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1883647850 | Oct 12 12:37:04 AM UTC 24 | Oct 12 12:37:08 AM UTC 24 | 759539947 ps | ||
| T818 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1267945834 | Oct 12 12:37:05 AM UTC 24 | Oct 12 12:37:08 AM UTC 24 | 489584646 ps | ||
| T819 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_intr_test.2260348310 | Oct 12 12:37:06 AM UTC 24 | Oct 12 12:37:08 AM UTC 24 | 415463293 ps | ||
| T820 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1227907382 | Oct 12 12:37:04 AM UTC 24 | Oct 12 12:37:09 AM UTC 24 | 4828871637 ps | ||
| T821 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3309334359 | Oct 12 12:37:05 AM UTC 24 | Oct 12 12:37:09 AM UTC 24 | 339057693 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.128207030 | Oct 12 12:36:39 AM UTC 24 | Oct 12 12:37:10 AM UTC 24 | 24081382617 ps | ||
| T822 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3046063807 | Oct 12 12:37:07 AM UTC 24 | Oct 12 12:37:11 AM UTC 24 | 412331105 ps | ||
| T823 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_rw.4050220654 | Oct 12 12:37:06 AM UTC 24 | Oct 12 12:37:11 AM UTC 24 | 572319324 ps | ||
| T824 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_intr_test.2432282134 | Oct 12 12:37:10 AM UTC 24 | Oct 12 12:37:12 AM UTC 24 | 455613305 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1228985821 | Oct 12 12:37:10 AM UTC 24 | Oct 12 12:37:12 AM UTC 24 | 491127130 ps | ||
| T825 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2629411592 | Oct 12 12:37:08 AM UTC 24 | Oct 12 12:37:13 AM UTC 24 | 416281419 ps | ||
| T826 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2182753072 | Oct 12 12:37:05 AM UTC 24 | Oct 12 12:37:14 AM UTC 24 | 4425158057 ps | ||
| T827 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.4177878052 | Oct 12 12:37:11 AM UTC 24 | Oct 12 12:37:14 AM UTC 24 | 491967001 ps | ||
| T828 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.3121901533 | Oct 12 12:37:12 AM UTC 24 | Oct 12 12:37:14 AM UTC 24 | 424904415 ps | ||
| T829 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3038170485 | Oct 12 12:37:10 AM UTC 24 | Oct 12 12:37:15 AM UTC 24 | 540728091 ps | ||
| T830 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3162289067 | Oct 12 12:37:07 AM UTC 24 | Oct 12 12:37:16 AM UTC 24 | 3946807797 ps | ||
| T831 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1832717332 | Oct 12 12:37:00 AM UTC 24 | Oct 12 12:37:16 AM UTC 24 | 4566163940 ps | ||
| T832 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2327308973 | Oct 12 12:37:10 AM UTC 24 | Oct 12 12:37:16 AM UTC 24 | 4346364906 ps | ||
| T833 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1359596895 | Oct 12 12:37:14 AM UTC 24 | Oct 12 12:37:17 AM UTC 24 | 843917505 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.478917326 | Oct 12 12:37:13 AM UTC 24 | Oct 12 12:37:17 AM UTC 24 | 386987627 ps | ||
| T834 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1036567403 | Oct 12 12:37:16 AM UTC 24 | Oct 12 12:37:19 AM UTC 24 | 535524911 ps | ||
| T835 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.2870263481 | Oct 12 12:37:15 AM UTC 24 | Oct 12 12:37:19 AM UTC 24 | 332432635 ps | ||
| T836 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.125006931 | Oct 12 12:37:14 AM UTC 24 | Oct 12 12:37:19 AM UTC 24 | 313740920 ps | ||
| T837 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1854550318 | Oct 12 12:37:04 AM UTC 24 | Oct 12 12:37:19 AM UTC 24 | 8514225852 ps | ||
| T838 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1188141646 | Oct 12 12:37:17 AM UTC 24 | Oct 12 12:37:20 AM UTC 24 | 482632256 ps | ||
| T345 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.385900239 | Oct 12 12:37:14 AM UTC 24 | Oct 12 12:37:22 AM UTC 24 | 8957774135 ps | ||
| T839 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.515427769 | Oct 12 12:37:12 AM UTC 24 | Oct 12 12:37:22 AM UTC 24 | 8639467883 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.291220809 | Oct 12 12:37:20 AM UTC 24 | Oct 12 12:37:22 AM UTC 24 | 474732134 ps | ||
| T840 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.521905591 | Oct 12 12:37:20 AM UTC 24 | Oct 12 12:37:23 AM UTC 24 | 646200392 ps | ||
| T841 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2220988380 | Oct 12 12:37:18 AM UTC 24 | Oct 12 12:37:23 AM UTC 24 | 1018821510 ps | ||
| T842 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.680989401 | Oct 12 12:37:16 AM UTC 24 | Oct 12 12:37:23 AM UTC 24 | 2875294198 ps | ||
| T843 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2696235062 | Oct 12 12:37:20 AM UTC 24 | Oct 12 12:37:25 AM UTC 24 | 336637677 ps | ||
| T844 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2843362046 | Oct 12 12:37:13 AM UTC 24 | Oct 12 12:37:27 AM UTC 24 | 5087604258 ps | ||
| T845 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.742895611 | Oct 12 12:37:18 AM UTC 24 | Oct 12 12:37:27 AM UTC 24 | 4594676146 ps | ||
| T846 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.1802125102 | Oct 12 12:37:24 AM UTC 24 | Oct 12 12:37:28 AM UTC 24 | 453433682 ps | ||
| T119 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2169065031 | Oct 12 12:37:24 AM UTC 24 | Oct 12 12:37:28 AM UTC 24 | 377058321 ps | ||
| T847 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2572297427 | Oct 12 12:37:24 AM UTC 24 | Oct 12 12:37:28 AM UTC 24 | 478221534 ps | ||
| T120 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1265227915 | Oct 12 12:37:24 AM UTC 24 | Oct 12 12:37:28 AM UTC 24 | 485585608 ps | ||
| T848 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.1504533245 | Oct 12 12:37:24 AM UTC 24 | Oct 12 12:37:28 AM UTC 24 | 518140203 ps | ||
| T849 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1460823548 | Oct 12 12:37:24 AM UTC 24 | Oct 12 12:37:29 AM UTC 24 | 441893842 ps | ||
| T850 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3922925240 | Oct 12 12:37:24 AM UTC 24 | Oct 12 12:37:29 AM UTC 24 | 1777985287 ps | ||
| T851 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3536659088 | Oct 12 12:37:21 AM UTC 24 | Oct 12 12:37:29 AM UTC 24 | 4434991045 ps | ||
| T852 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1401948139 | Oct 12 12:37:29 AM UTC 24 | Oct 12 12:37:31 AM UTC 24 | 373054539 ps | ||
| T853 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.4081388709 | Oct 12 12:37:28 AM UTC 24 | Oct 12 12:37:32 AM UTC 24 | 532385604 ps | ||
| T854 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.2946781822 | Oct 12 12:37:29 AM UTC 24 | Oct 12 12:37:33 AM UTC 24 | 368865669 ps | ||
| T855 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1699759305 | Oct 12 12:37:28 AM UTC 24 | Oct 12 12:37:33 AM UTC 24 | 430213426 ps | ||
| T856 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2763616218 | Oct 12 12:37:26 AM UTC 24 | Oct 12 12:37:33 AM UTC 24 | 4749032768 ps | ||
| T857 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2528513201 | Oct 12 12:37:20 AM UTC 24 | Oct 12 12:37:35 AM UTC 24 | 4630440385 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.946877969 | Oct 12 12:36:53 AM UTC 24 | Oct 12 12:37:37 AM UTC 24 | 24486320297 ps | ||
| T346 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.561681611 | Oct 12 12:37:24 AM UTC 24 | Oct 12 12:37:38 AM UTC 24 | 8744733261 ps | ||
| T858 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2980297732 | Oct 12 12:37:36 AM UTC 24 | Oct 12 12:37:39 AM UTC 24 | 620015815 ps | ||
| T859 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.2058671578 | Oct 12 12:37:36 AM UTC 24 | Oct 12 12:37:40 AM UTC 24 | 357343993 ps | ||
| T860 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.4011431033 | Oct 12 12:37:37 AM UTC 24 | Oct 12 12:37:40 AM UTC 24 | 545332310 ps | ||
| T861 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.813181117 | Oct 12 12:37:36 AM UTC 24 | Oct 12 12:37:40 AM UTC 24 | 662909648 ps | ||
| T862 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1672970727 | Oct 12 12:37:36 AM UTC 24 | Oct 12 12:37:40 AM UTC 24 | 443991086 ps | ||
| T863 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2462053208 | Oct 12 12:37:38 AM UTC 24 | Oct 12 12:37:41 AM UTC 24 | 2880264813 ps | ||
| T864 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3458106256 | Oct 12 12:37:38 AM UTC 24 | Oct 12 12:37:41 AM UTC 24 | 379122932 ps | ||
| T865 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.172753761 | Oct 12 12:37:37 AM UTC 24 | Oct 12 12:37:41 AM UTC 24 | 393583792 ps | ||
| T866 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1404069927 | Oct 12 12:37:39 AM UTC 24 | Oct 12 12:37:42 AM UTC 24 | 539036164 ps | ||
| T867 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/37.adc_ctrl_intr_test.2959481078 | Oct 12 12:37:50 AM UTC 24 | Oct 12 12:37:54 AM UTC 24 | 489957152 ps | ||
| T868 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1450882556 | Oct 12 12:37:37 AM UTC 24 | Oct 12 12:37:43 AM UTC 24 | 2396795777 ps | ||
| T869 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3466077962 | Oct 12 12:37:37 AM UTC 24 | Oct 12 12:37:43 AM UTC 24 | 828530766 ps | ||
| T870 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3988736814 | Oct 12 12:37:08 AM UTC 24 | Oct 12 12:37:44 AM UTC 24 | 8399445257 ps | ||
| T871 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.751666329 | Oct 12 12:37:28 AM UTC 24 | Oct 12 12:37:44 AM UTC 24 | 8198566566 ps | ||
| T872 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.643459693 | Oct 12 12:37:41 AM UTC 24 | Oct 12 12:37:44 AM UTC 24 | 495610837 ps | ||
| T873 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3919871660 | Oct 12 12:37:41 AM UTC 24 | Oct 12 12:37:45 AM UTC 24 | 1865590418 ps | ||
| T874 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1140861586 | Oct 12 12:37:40 AM UTC 24 | Oct 12 12:37:45 AM UTC 24 | 527186750 ps | ||
| T875 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.1899974864 | Oct 12 12:37:41 AM UTC 24 | Oct 12 12:37:45 AM UTC 24 | 455644291 ps | ||
| T876 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.532793903 | Oct 12 12:37:36 AM UTC 24 | Oct 12 12:37:45 AM UTC 24 | 4692681802 ps | ||
| T877 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1374492457 | Oct 12 12:37:42 AM UTC 24 | Oct 12 12:37:46 AM UTC 24 | 321431519 ps | ||
| T878 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1119230309 | Oct 12 12:37:43 AM UTC 24 | Oct 12 12:37:46 AM UTC 24 | 386458597 ps | ||
| T879 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.747998616 | Oct 12 12:37:43 AM UTC 24 | Oct 12 12:37:47 AM UTC 24 | 462567807 ps | ||
| T880 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1513084407 | Oct 12 12:37:42 AM UTC 24 | Oct 12 12:37:47 AM UTC 24 | 4734231539 ps | ||
| T881 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.94368987 | Oct 12 12:37:42 AM UTC 24 | Oct 12 12:37:47 AM UTC 24 | 390132701 ps | ||
| T882 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3980585994 | Oct 12 12:37:41 AM UTC 24 | Oct 12 12:37:48 AM UTC 24 | 8921920168 ps | ||
| T883 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1118614590 | Oct 12 12:37:44 AM UTC 24 | Oct 12 12:37:48 AM UTC 24 | 384330723 ps | ||
| T884 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.2796636180 | Oct 12 12:37:45 AM UTC 24 | Oct 12 12:37:48 AM UTC 24 | 358030595 ps | ||
| T347 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3840754188 | Oct 12 12:37:37 AM UTC 24 | Oct 12 12:37:48 AM UTC 24 | 8087536485 ps | ||
| T885 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1931242724 | Oct 12 12:37:43 AM UTC 24 | Oct 12 12:37:48 AM UTC 24 | 3653146768 ps | ||
| T886 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.2305681621 | Oct 12 12:37:46 AM UTC 24 | Oct 12 12:37:49 AM UTC 24 | 390489619 ps | ||
| T887 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.3543807138 | Oct 12 12:37:46 AM UTC 24 | Oct 12 12:37:49 AM UTC 24 | 307213948 ps | ||
| T888 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.2496306125 | Oct 12 12:37:47 AM UTC 24 | Oct 12 12:37:49 AM UTC 24 | 532975201 ps | ||
| T889 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.2311328846 | Oct 12 12:37:46 AM UTC 24 | Oct 12 12:37:49 AM UTC 24 | 370559406 ps | ||
| T890 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.2702721709 | Oct 12 12:37:47 AM UTC 24 | Oct 12 12:37:49 AM UTC 24 | 378781561 ps | ||
| T891 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.1479464155 | Oct 12 12:37:47 AM UTC 24 | Oct 12 12:37:49 AM UTC 24 | 501169781 ps | ||
| T892 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.953617781 | Oct 12 12:37:46 AM UTC 24 | Oct 12 12:37:50 AM UTC 24 | 466571933 ps | ||
| T893 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.311554048 | Oct 12 12:37:48 AM UTC 24 | Oct 12 12:37:50 AM UTC 24 | 329720820 ps | ||
| T894 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/33.adc_ctrl_intr_test.2161364099 | Oct 12 12:37:48 AM UTC 24 | Oct 12 12:37:50 AM UTC 24 | 360016682 ps | ||
| T895 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/32.adc_ctrl_intr_test.3725617848 | Oct 12 12:37:48 AM UTC 24 | Oct 12 12:37:51 AM UTC 24 | 541978990 ps | ||
| T896 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.2864619238 | Oct 12 12:37:48 AM UTC 24 | Oct 12 12:37:51 AM UTC 24 | 336651640 ps | ||
| T897 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/31.adc_ctrl_intr_test.3185851504 | Oct 12 12:37:48 AM UTC 24 | Oct 12 12:37:51 AM UTC 24 | 311334094 ps | ||
| T898 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/30.adc_ctrl_intr_test.595633606 | Oct 12 12:37:48 AM UTC 24 | Oct 12 12:37:51 AM UTC 24 | 339383060 ps | ||
| T899 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/35.adc_ctrl_intr_test.3150677781 | Oct 12 12:37:50 AM UTC 24 | Oct 12 12:37:52 AM UTC 24 | 572213367 ps | ||
| T900 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/34.adc_ctrl_intr_test.4063434764 | Oct 12 12:37:49 AM UTC 24 | Oct 12 12:37:52 AM UTC 24 | 502884523 ps | ||
| T901 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/38.adc_ctrl_intr_test.767822530 | Oct 12 12:37:50 AM UTC 24 | Oct 12 12:37:52 AM UTC 24 | 551787558 ps | ||
| T902 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/41.adc_ctrl_intr_test.2802304436 | Oct 12 12:37:50 AM UTC 24 | Oct 12 12:37:52 AM UTC 24 | 486202883 ps | ||
| T903 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/39.adc_ctrl_intr_test.3839661739 | Oct 12 12:37:50 AM UTC 24 | Oct 12 12:37:52 AM UTC 24 | 405944229 ps | ||
| T904 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/40.adc_ctrl_intr_test.470661411 | Oct 12 12:37:50 AM UTC 24 | Oct 12 12:37:52 AM UTC 24 | 483264832 ps | ||
| T905 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/44.adc_ctrl_intr_test.3254971176 | Oct 12 12:37:51 AM UTC 24 | Oct 12 12:37:53 AM UTC 24 | 425567359 ps | ||
| T906 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/45.adc_ctrl_intr_test.212259836 | Oct 12 12:37:51 AM UTC 24 | Oct 12 12:37:53 AM UTC 24 | 309246171 ps | ||
| T907 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/36.adc_ctrl_intr_test.2467756648 | Oct 12 12:37:50 AM UTC 24 | Oct 12 12:37:54 AM UTC 24 | 486723128 ps | ||
| T908 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/43.adc_ctrl_intr_test.3661117044 | Oct 12 12:37:51 AM UTC 24 | Oct 12 12:37:54 AM UTC 24 | 487782923 ps | ||
| T909 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/42.adc_ctrl_intr_test.3837007091 | Oct 12 12:37:51 AM UTC 24 | Oct 12 12:37:54 AM UTC 24 | 362987959 ps | ||
| T910 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/48.adc_ctrl_intr_test.1225028437 | Oct 12 12:37:52 AM UTC 24 | Oct 12 12:37:55 AM UTC 24 | 306346231 ps | ||
| T911 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/49.adc_ctrl_intr_test.4033327998 | Oct 12 12:37:52 AM UTC 24 | Oct 12 12:37:55 AM UTC 24 | 463117277 ps | ||
| T912 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/47.adc_ctrl_intr_test.2706600346 | Oct 12 12:37:52 AM UTC 24 | Oct 12 12:37:55 AM UTC 24 | 289842124 ps | ||
| T913 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/46.adc_ctrl_intr_test.105410432 | Oct 12 12:37:52 AM UTC 24 | Oct 12 12:37:56 AM UTC 24 | 404732430 ps | ||
| T914 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.764040759 | Oct 12 12:37:36 AM UTC 24 | Oct 12 12:38:08 AM UTC 24 | 8155076911 ps | ||
| T915 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2470732832 | Oct 12 12:36:37 AM UTC 24 | Oct 12 12:38:13 AM UTC 24 | 21194622664 ps | ||
| T916 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3631841995 | Oct 12 12:36:43 AM UTC 24 | Oct 12 12:38:36 AM UTC 24 | 26301986597 ps | ||
| T917 | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1491127770 | Oct 12 12:36:49 AM UTC 24 | Oct 12 12:38:47 AM UTC 24 | 45853590965 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.2902794237 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5075424445 ps |
| CPU time | 8.98 seconds |
| Started | Oct 12 01:14:00 AM UTC 24 |
| Finished | Oct 12 01:14:10 AM UTC 24 |
| Peak memory | 210452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2902794237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.adc_ctrl_stress_all_with_rand_reset.2902794237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.797586552 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 31595602871 ps |
| CPU time | 18.01 seconds |
| Started | Oct 12 01:14:17 AM UTC 24 |
| Finished | Oct 12 01:14:36 AM UTC 24 |
| Peak memory | 220716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=797586552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.797586552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_clock_gating.3784484088 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 491248104015 ps |
| CPU time | 62.88 seconds |
| Started | Oct 12 01:13:50 AM UTC 24 |
| Finished | Oct 12 01:14:54 AM UTC 24 |
| Peak memory | 210184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784484088 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gating.3784484088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_fsm_reset.3256083119 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 105810155891 ps |
| CPU time | 486.42 seconds |
| Started | Oct 12 01:14:16 AM UTC 24 |
| Finished | Oct 12 01:22:27 AM UTC 24 |
| Peak memory | 210740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256083119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3256083119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/2.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all.1793188336 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 501409154327 ps |
| CPU time | 299.14 seconds |
| Started | Oct 12 01:13:51 AM UTC 24 |
| Finished | Oct 12 01:18:55 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793188336 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.1793188336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2886256050 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 38407086973 ps |
| CPU time | 58.85 seconds |
| Started | Oct 12 01:15:37 AM UTC 24 |
| Finished | Oct 12 01:16:38 AM UTC 24 |
| Peak memory | 226916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2886256050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 5.adc_ctrl_stress_all_with_rand_reset.2886256050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_both.519098030 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 515430495513 ps |
| CPU time | 389.47 seconds |
| Started | Oct 12 01:20:13 AM UTC 24 |
| Finished | Oct 12 01:26:47 AM UTC 24 |
| Peak memory | 210336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519098030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.519098030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/8.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all.2086628276 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 357267358253 ps |
| CPU time | 153.36 seconds |
| Started | Oct 12 01:15:51 AM UTC 24 |
| Finished | Oct 12 01:18:27 AM UTC 24 |
| Peak memory | 210284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086628276 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.2086628276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/5.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all.827163083 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 686510997220 ps |
| CPU time | 152.67 seconds |
| Started | Oct 12 01:28:25 AM UTC 24 |
| Finished | Oct 12 01:31:01 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827163083 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.827163083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/13.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.3581418942 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 493417045714 ps |
| CPU time | 188.71 seconds |
| Started | Oct 12 01:14:34 AM UTC 24 |
| Finished | Oct 12 01:17:46 AM UTC 24 |
| Peak memory | 210344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581418942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.3581418942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/3.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3624903804 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 2925018836 ps |
| CPU time | 12.26 seconds |
| Started | Oct 12 01:25:17 AM UTC 24 |
| Finished | Oct 12 01:25:30 AM UTC 24 |
| Peak memory | 210108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3624903804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 11.adc_ctrl_stress_all_with_rand_reset.3624903804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/11.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.1601274574 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 3742360925 ps |
| CPU time | 7.96 seconds |
| Started | Oct 12 01:13:51 AM UTC 24 |
| Finished | Oct 12 01:14:01 AM UTC 24 |
| Peak memory | 242504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601274574 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1601274574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/0.adc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_both.972090919 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 524138609536 ps |
| CPU time | 320.73 seconds |
| Started | Oct 12 01:29:51 AM UTC 24 |
| Finished | Oct 12 01:35:16 AM UTC 24 |
| Peak memory | 210132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972090919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.972090919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/15.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3064658302 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 567018195 ps |
| CPU time | 2.13 seconds |
| Started | Oct 12 12:36:37 AM UTC 24 |
| Finished | Oct 12 12:36:40 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064658302 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.3064658302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/1.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_clock_gating.4215912683 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 492537837003 ps |
| CPU time | 446.42 seconds |
| Started | Oct 12 01:34:38 AM UTC 24 |
| Finished | Oct 12 01:42:10 AM UTC 24 |
| Peak memory | 210068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215912683 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gating.4215912683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/19.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt.4037820409 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 477665368705 ps |
| CPU time | 323.98 seconds |
| Started | Oct 12 01:31:35 AM UTC 24 |
| Finished | Oct 12 01:37:03 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037820409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.4037820409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/17.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1964172375 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 320331252300 ps |
| CPU time | 124.65 seconds |
| Started | Oct 12 01:13:49 AM UTC 24 |
| Finished | Oct 12 01:15:56 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964172375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt_fixed.1964172375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/0.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all.883188567 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 482051460165 ps |
| CPU time | 364.54 seconds |
| Started | Oct 12 01:22:50 AM UTC 24 |
| Finished | Oct 12 01:28:58 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883188567 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.883188567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_clock_gating.867994488 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 346227031050 ps |
| CPU time | 195.58 seconds |
| Started | Oct 12 01:31:52 AM UTC 24 |
| Finished | Oct 12 01:35:11 AM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867994488 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gating.867994488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/17.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3507320779 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 326377845 ps |
| CPU time | 3.02 seconds |
| Started | Oct 12 12:36:36 AM UTC 24 |
| Finished | Oct 12 12:36:40 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507320779 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.3507320779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/0.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all.2782539721 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 340346501022 ps |
| CPU time | 548.67 seconds |
| Started | Oct 12 01:18:27 AM UTC 24 |
| Finished | Oct 12 01:27:42 AM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782539721 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.2782539721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_both.3797245322 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 509358925071 ps |
| CPU time | 1405.78 seconds |
| Started | Oct 12 01:30:58 AM UTC 24 |
| Finished | Oct 12 01:54:38 AM UTC 24 |
| Peak memory | 212716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797245322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3797245322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/16.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.4292293804 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 348158024830 ps |
| CPU time | 965.05 seconds |
| Started | Oct 12 01:23:36 AM UTC 24 |
| Finished | Oct 12 01:39:51 AM UTC 24 |
| Peak memory | 212700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292293804 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gating.4292293804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/10.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.574529716 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 202062008496 ps |
| CPU time | 35.16 seconds |
| Started | Oct 12 01:13:51 AM UTC 24 |
| Finished | Oct 12 01:14:28 AM UTC 24 |
| Peak memory | 220828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=574529716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.574529716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup.3584976063 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 553316306555 ps |
| CPU time | 387.61 seconds |
| Started | Oct 12 01:13:56 AM UTC 24 |
| Finished | Oct 12 01:20:29 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584976063 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_wakeup.3584976063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/1.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_clock_gating.3058174538 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 496527104968 ps |
| CPU time | 163.06 seconds |
| Started | Oct 12 01:40:58 AM UTC 24 |
| Finished | Oct 12 01:43:44 AM UTC 24 |
| Peak memory | 210324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058174538 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gating.3058174538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/23.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup.1845032249 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 542441082447 ps |
| CPU time | 192.41 seconds |
| Started | Oct 12 01:25:50 AM UTC 24 |
| Finished | Oct 12 01:29:06 AM UTC 24 |
| Peak memory | 210068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845032249 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_wakeup.1845032249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/12.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_clock_gating.2170066134 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 499498739287 ps |
| CPU time | 887.33 seconds |
| Started | Oct 12 01:39:04 AM UTC 24 |
| Finished | Oct 12 01:54:00 AM UTC 24 |
| Peak memory | 213124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170066134 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gating.2170066134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/22.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_both.649403971 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 359696334611 ps |
| CPU time | 346.64 seconds |
| Started | Oct 12 01:17:12 AM UTC 24 |
| Finished | Oct 12 01:23:03 AM UTC 24 |
| Peak memory | 210128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649403971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.649403971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/6.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup_fixed.1941339616 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 394831405529 ps |
| CPU time | 273.7 seconds |
| Started | Oct 12 01:13:50 AM UTC 24 |
| Finished | Oct 12 01:18:27 AM UTC 24 |
| Peak memory | 210332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941339616 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_wakeup_fixed.1941339616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/0.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_both.3588193448 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 333029781983 ps |
| CPU time | 77.11 seconds |
| Started | Oct 12 01:24:52 AM UTC 24 |
| Finished | Oct 12 01:26:10 AM UTC 24 |
| Peak memory | 210128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588193448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3588193448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/11.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.413000921 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 8833240283 ps |
| CPU time | 24.54 seconds |
| Started | Oct 12 01:45:17 AM UTC 24 |
| Finished | Oct 12 01:45:42 AM UTC 24 |
| Peak memory | 220584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=413000921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.413000921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/26.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_alert_test.274752497 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 494921924 ps |
| CPU time | 2.37 seconds |
| Started | Oct 12 01:14:02 AM UTC 24 |
| Finished | Oct 12 01:14:05 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274752497 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.274752497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/1.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2071495096 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 8150137935 ps |
| CPU time | 11.86 seconds |
| Started | Oct 12 12:36:50 AM UTC 24 |
| Finished | Oct 12 12:37:03 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071495096 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_intg_err.2071495096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/4.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt.3686980597 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 494637763312 ps |
| CPU time | 564.64 seconds |
| Started | Oct 12 01:30:46 AM UTC 24 |
| Finished | Oct 12 01:40:17 AM UTC 24 |
| Peak memory | 210076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686980597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.3686980597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/16.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_both.2577174868 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 371044712924 ps |
| CPU time | 991.22 seconds |
| Started | Oct 12 02:19:02 AM UTC 24 |
| Finished | Oct 12 02:35:44 AM UTC 24 |
| Peak memory | 212788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577174868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2577174868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/49.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_clock_gating.1801671438 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 527697156195 ps |
| CPU time | 621.38 seconds |
| Started | Oct 12 01:45:03 AM UTC 24 |
| Finished | Oct 12 01:55:31 AM UTC 24 |
| Peak memory | 210336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801671438 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gating.1801671438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/26.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_fsm_reset.2861691413 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 128942811107 ps |
| CPU time | 670.76 seconds |
| Started | Oct 12 01:13:51 AM UTC 24 |
| Finished | Oct 12 01:25:08 AM UTC 24 |
| Peak memory | 213144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861691413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.2861691413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/0.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.2999003221 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 326977051633 ps |
| CPU time | 865.01 seconds |
| Started | Oct 12 01:14:11 AM UTC 24 |
| Finished | Oct 12 01:28:45 AM UTC 24 |
| Peak memory | 212796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999003221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.2999003221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/2.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt.1200529213 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 159865168208 ps |
| CPU time | 212.84 seconds |
| Started | Oct 12 01:28:46 AM UTC 24 |
| Finished | Oct 12 01:32:22 AM UTC 24 |
| Peak memory | 210084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200529213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.1200529213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/14.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.128207030 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 24081382617 ps |
| CPU time | 30.68 seconds |
| Started | Oct 12 12:36:39 AM UTC 24 |
| Finished | Oct 12 12:37:10 AM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128207030 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_bash.128207030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/1.adc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3309334359 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 339057693 ps |
| CPU time | 3.1 seconds |
| Started | Oct 12 12:37:05 AM UTC 24 |
| Finished | Oct 12 12:37:09 AM UTC 24 |
| Peak memory | 211364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309334359 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.3309334359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/8.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup.1531847929 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 346345548832 ps |
| CPU time | 572.28 seconds |
| Started | Oct 12 01:29:30 AM UTC 24 |
| Finished | Oct 12 01:39:08 AM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531847929 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_wakeup.1531847929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/15.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_both.16675357 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 168454184029 ps |
| CPU time | 308.78 seconds |
| Started | Oct 12 01:36:16 AM UTC 24 |
| Finished | Oct 12 01:41:29 AM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16675357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_ SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.16675357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/20.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_both.3566454788 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 518123356201 ps |
| CPU time | 189.77 seconds |
| Started | Oct 12 01:54:44 AM UTC 24 |
| Finished | Oct 12 01:57:56 AM UTC 24 |
| Peak memory | 210064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566454788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.3566454788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/32.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled.1650454450 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 324894848910 ps |
| CPU time | 247.13 seconds |
| Started | Oct 12 01:24:29 AM UTC 24 |
| Finished | Oct 12 01:28:39 AM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650454450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.1650454450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/11.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup.1103530067 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 397070144777 ps |
| CPU time | 51.58 seconds |
| Started | Oct 12 01:27:28 AM UTC 24 |
| Finished | Oct 12 01:28:21 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103530067 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_wakeup.1103530067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/13.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_stress_all.3252577496 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 207706710100 ps |
| CPU time | 195.82 seconds |
| Started | Oct 12 01:57:19 AM UTC 24 |
| Finished | Oct 12 02:00:38 AM UTC 24 |
| Peak memory | 210264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252577496 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.3252577496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/34.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.3493828632 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 7843949487 ps |
| CPU time | 32.68 seconds |
| Started | Oct 12 01:58:13 AM UTC 24 |
| Finished | Oct 12 01:58:47 AM UTC 24 |
| Peak memory | 220776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3493828632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 35.adc_ctrl_stress_all_with_rand_reset.3493828632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/35.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_interrupt.3450116123 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 499439293116 ps |
| CPU time | 1313.7 seconds |
| Started | Oct 12 01:38:53 AM UTC 24 |
| Finished | Oct 12 02:00:59 AM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450116123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3450116123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/22.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_interrupt.914720036 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 334283873720 ps |
| CPU time | 340.77 seconds |
| Started | Oct 12 01:52:28 AM UTC 24 |
| Finished | Oct 12 01:58:13 AM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914720036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.914720036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/31.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup.4110600090 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 369158743120 ps |
| CPU time | 280.21 seconds |
| Started | Oct 12 01:14:54 AM UTC 24 |
| Finished | Oct 12 01:19:38 AM UTC 24 |
| Peak memory | 210064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110600090 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_wakeup.4110600090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/4.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_both.4012633485 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 512030867438 ps |
| CPU time | 721.31 seconds |
| Started | Oct 12 02:14:15 AM UTC 24 |
| Finished | Oct 12 02:26:23 AM UTC 24 |
| Peak memory | 210120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012633485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.4012633485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/46.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.3883270240 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 168949955972 ps |
| CPU time | 71.04 seconds |
| Started | Oct 12 01:26:35 AM UTC 24 |
| Finished | Oct 12 01:27:47 AM UTC 24 |
| Peak memory | 210260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883270240 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gating.3883270240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/12.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.2979888075 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 1574914056 ps |
| CPU time | 4.43 seconds |
| Started | Oct 12 01:48:47 AM UTC 24 |
| Finished | Oct 12 01:48:53 AM UTC 24 |
| Peak memory | 210116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2979888075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 28.adc_ctrl_stress_all_with_rand_reset.2979888075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/28.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all.487721130 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 138856272809 ps |
| CPU time | 597.77 seconds |
| Started | Oct 12 01:14:17 AM UTC 24 |
| Finished | Oct 12 01:24:20 AM UTC 24 |
| Peak memory | 220940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487721130 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.487721130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_stress_all.642366107 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 495158690355 ps |
| CPU time | 783.38 seconds |
| Started | Oct 12 01:39:46 AM UTC 24 |
| Finished | Oct 12 01:52:57 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642366107 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.642366107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/22.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_clock_gating.152385443 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 522021021411 ps |
| CPU time | 294.03 seconds |
| Started | Oct 12 01:57:57 AM UTC 24 |
| Finished | Oct 12 02:02:54 AM UTC 24 |
| Peak memory | 210396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152385443 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gating.152385443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/35.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_both.152101942 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 531615659488 ps |
| CPU time | 1331.98 seconds |
| Started | Oct 12 02:01:00 AM UTC 24 |
| Finished | Oct 12 02:23:26 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152101942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.152101942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/37.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_wakeup.3015359021 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 337178489017 ps |
| CPU time | 448.03 seconds |
| Started | Oct 12 02:10:04 AM UTC 24 |
| Finished | Oct 12 02:17:37 AM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015359021 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_wakeup.3015359021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/44.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt.1199879733 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 325750430925 ps |
| CPU time | 779.09 seconds |
| Started | Oct 12 02:18:11 AM UTC 24 |
| Finished | Oct 12 02:31:18 AM UTC 24 |
| Peak memory | 210140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199879733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1199879733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/49.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt.1366292755 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 167426441877 ps |
| CPU time | 398.78 seconds |
| Started | Oct 12 01:17:52 AM UTC 24 |
| Finished | Oct 12 01:24:36 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366292755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1366292755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/7.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.385900239 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 8957774135 ps |
| CPU time | 6.44 seconds |
| Started | Oct 12 12:37:14 AM UTC 24 |
| Finished | Oct 12 12:37:22 AM UTC 24 |
| Peak memory | 211432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385900239 -assert nopostproc +UVM_TEST NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_intg_err.385900239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/11.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled.2306907989 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 332755163106 ps |
| CPU time | 874.12 seconds |
| Started | Oct 12 01:34:03 AM UTC 24 |
| Finished | Oct 12 01:48:46 AM UTC 24 |
| Peak memory | 210064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306907989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.2306907989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/19.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all.322763787 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 288286638534 ps |
| CPU time | 599.85 seconds |
| Started | Oct 12 01:35:22 AM UTC 24 |
| Finished | Oct 12 01:45:28 AM UTC 24 |
| Peak memory | 222700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322763787 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.322763787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/19.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_both.3160291791 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 326744926431 ps |
| CPU time | 1141.93 seconds |
| Started | Oct 12 01:49:26 AM UTC 24 |
| Finished | Oct 12 02:08:39 AM UTC 24 |
| Peak memory | 212664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160291791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3160291791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/29.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_interrupt.1200395236 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 495392836497 ps |
| CPU time | 717.58 seconds |
| Started | Oct 12 01:48:58 AM UTC 24 |
| Finished | Oct 12 02:01:04 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200395236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1200395236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/29.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_interrupt.878534640 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 322727799772 ps |
| CPU time | 798.99 seconds |
| Started | Oct 12 01:57:37 AM UTC 24 |
| Finished | Oct 12 02:11:05 AM UTC 24 |
| Peak memory | 212732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878534640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.878534640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/35.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_wakeup.1345145531 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 531047026079 ps |
| CPU time | 351.93 seconds |
| Started | Oct 12 02:18:15 AM UTC 24 |
| Finished | Oct 12 02:24:11 AM UTC 24 |
| Peak memory | 210064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345145531 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_wakeup.1345145531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/49.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.2928616463 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 327350433606 ps |
| CPU time | 250.43 seconds |
| Started | Oct 12 01:16:09 AM UTC 24 |
| Finished | Oct 12 01:20:23 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928616463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.2928616463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/6.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_both.976748219 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 182718235615 ps |
| CPU time | 237.56 seconds |
| Started | Oct 12 01:13:50 AM UTC 24 |
| Finished | Oct 12 01:17:51 AM UTC 24 |
| Peak memory | 210112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976748219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.976748219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/0.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled.1224294549 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 324376048818 ps |
| CPU time | 96.12 seconds |
| Started | Oct 12 01:13:45 AM UTC 24 |
| Finished | Oct 12 01:15:23 AM UTC 24 |
| Peak memory | 210128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224294549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.1224294549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/0.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.1533478309 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 125861996358 ps |
| CPU time | 669.14 seconds |
| Started | Oct 12 01:14:01 AM UTC 24 |
| Finished | Oct 12 01:25:17 AM UTC 24 |
| Peak memory | 210624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533478309 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.1533478309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3705796427 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 1573473551 ps |
| CPU time | 10.78 seconds |
| Started | Oct 12 01:29:07 AM UTC 24 |
| Finished | Oct 12 01:29:19 AM UTC 24 |
| Peak memory | 210116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3705796427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 14.adc_ctrl_stress_all_with_rand_reset.3705796427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/14.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_fsm_reset.1017935256 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 124829672261 ps |
| CPU time | 739.84 seconds |
| Started | Oct 12 01:36:58 AM UTC 24 |
| Finished | Oct 12 01:49:25 AM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017935256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.1017935256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/20.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_polled.1916429341 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 479308191733 ps |
| CPU time | 224.32 seconds |
| Started | Oct 12 01:43:23 AM UTC 24 |
| Finished | Oct 12 01:47:10 AM UTC 24 |
| Peak memory | 210336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916429341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1916429341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/25.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_wakeup.1886783908 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 531775974809 ps |
| CPU time | 747.71 seconds |
| Started | Oct 12 01:44:55 AM UTC 24 |
| Finished | Oct 12 01:57:31 AM UTC 24 |
| Peak memory | 210132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886783908 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_wakeup.1886783908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/26.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_wakeup.154414524 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 520511527253 ps |
| CPU time | 1235.77 seconds |
| Started | Oct 12 02:01:45 AM UTC 24 |
| Finished | Oct 12 02:22:33 AM UTC 24 |
| Peak memory | 212856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154414524 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_wakeup.154414524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/38.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_polled.3631849130 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 335611519039 ps |
| CPU time | 140.76 seconds |
| Started | Oct 12 02:04:52 AM UTC 24 |
| Finished | Oct 12 02:07:15 AM UTC 24 |
| Peak memory | 210344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631849130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.3631849130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/41.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_fsm_reset.261783981 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 104460848156 ps |
| CPU time | 648.16 seconds |
| Started | Oct 12 02:14:29 AM UTC 24 |
| Finished | Oct 12 02:25:24 AM UTC 24 |
| Peak memory | 210464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261783981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.261783981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/46.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_fsm_reset.633564558 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 71553073021 ps |
| CPU time | 471.49 seconds |
| Started | Oct 12 01:15:36 AM UTC 24 |
| Finished | Oct 12 01:23:33 AM UTC 24 |
| Peak memory | 210476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633564558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.633564558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/5.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_clock_gating.511513768 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 331708708044 ps |
| CPU time | 242.7 seconds |
| Started | Oct 12 01:19:38 AM UTC 24 |
| Finished | Oct 12 01:23:44 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511513768 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gating.511513768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/8.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_fsm_reset.2085324205 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 110083185618 ps |
| CPU time | 673.23 seconds |
| Started | Oct 12 01:13:59 AM UTC 24 |
| Finished | Oct 12 01:25:19 AM UTC 24 |
| Peak memory | 210432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085324205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2085324205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/1.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2374631421 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 10502400163 ps |
| CPU time | 14.44 seconds |
| Started | Oct 12 01:24:12 AM UTC 24 |
| Finished | Oct 12 01:24:27 AM UTC 24 |
| Peak memory | 220932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2374631421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 10.adc_ctrl_stress_all_with_rand_reset.2374631421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/10.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup.2750818573 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 196345066420 ps |
| CPU time | 159.85 seconds |
| Started | Oct 12 01:24:37 AM UTC 24 |
| Finished | Oct 12 01:27:20 AM UTC 24 |
| Peak memory | 210072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750818573 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_wakeup.2750818573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/11.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_clock_gating.2875310444 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 342259692003 ps |
| CPU time | 858.76 seconds |
| Started | Oct 12 01:28:59 AM UTC 24 |
| Finished | Oct 12 01:43:27 AM UTC 24 |
| Peak memory | 212920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875310444 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gating.2875310444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/14.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_fsm_reset.3170809368 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 86310080985 ps |
| CPU time | 433.34 seconds |
| Started | Oct 12 01:41:30 AM UTC 24 |
| Finished | Oct 12 01:48:49 AM UTC 24 |
| Peak memory | 210476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170809368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.3170809368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/23.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_wakeup.4007682123 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 549951408234 ps |
| CPU time | 349.75 seconds |
| Started | Oct 12 01:42:34 AM UTC 24 |
| Finished | Oct 12 01:48:28 AM UTC 24 |
| Peak memory | 210064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007682123 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_wakeup.4007682123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/24.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_stress_all.1708748118 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 550795875268 ps |
| CPU time | 2085.01 seconds |
| Started | Oct 12 01:43:00 AM UTC 24 |
| Finished | Oct 12 02:18:04 AM UTC 24 |
| Peak memory | 229420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708748118 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.1708748118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/24.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt.1135432490 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 499654225780 ps |
| CPU time | 218.74 seconds |
| Started | Oct 12 01:14:26 AM UTC 24 |
| Finished | Oct 12 01:18:08 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135432490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.1135432490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/3.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_clock_gating.333539736 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 506733171684 ps |
| CPU time | 335.58 seconds |
| Started | Oct 12 01:51:35 AM UTC 24 |
| Finished | Oct 12 01:57:15 AM UTC 24 |
| Peak memory | 210336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333539736 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gating.333539736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/30.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1907077146 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 7938957086 ps |
| CPU time | 18.69 seconds |
| Started | Oct 12 01:51:59 AM UTC 24 |
| Finished | Oct 12 01:52:19 AM UTC 24 |
| Peak memory | 220516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1907077146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 30.adc_ctrl_stress_all_with_rand_reset.1907077146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/30.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_clock_gating.2748293417 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 408267325985 ps |
| CPU time | 973.92 seconds |
| Started | Oct 12 01:52:51 AM UTC 24 |
| Finished | Oct 12 02:09:15 AM UTC 24 |
| Peak memory | 212864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748293417 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gating.2748293417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/31.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_fsm_reset.3804661584 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 115298548544 ps |
| CPU time | 702.22 seconds |
| Started | Oct 12 01:55:38 AM UTC 24 |
| Finished | Oct 12 02:07:28 AM UTC 24 |
| Peak memory | 210616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804661584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.3804661584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/33.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.1657209905 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 32053281243 ps |
| CPU time | 26.37 seconds |
| Started | Oct 12 02:05:40 AM UTC 24 |
| Finished | Oct 12 02:06:08 AM UTC 24 |
| Peak memory | 210456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1657209905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 41.adc_ctrl_stress_all_with_rand_reset.1657209905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/41.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1325482735 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 887788954 ps |
| CPU time | 5.29 seconds |
| Started | Oct 12 12:36:37 AM UTC 24 |
| Finished | Oct 12 12:36:43 AM UTC 24 |
| Peak memory | 211256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325482735 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_aliasing.1325482735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/0.adc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2470732832 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 21194622664 ps |
| CPU time | 93.84 seconds |
| Started | Oct 12 12:36:37 AM UTC 24 |
| Finished | Oct 12 12:38:13 AM UTC 24 |
| Peak memory | 211384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470732832 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_bash.2470732832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/0.adc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2372273704 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 689032330 ps |
| CPU time | 1.37 seconds |
| Started | Oct 12 12:36:36 AM UTC 24 |
| Finished | Oct 12 12:36:38 AM UTC 24 |
| Peak memory | 210384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372273704 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_reset.2372273704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/0.adc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.964986581 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 660066794 ps |
| CPU time | 1.86 seconds |
| Started | Oct 12 12:36:37 AM UTC 24 |
| Finished | Oct 12 12:36:40 AM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=964986581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr _mem_rw_with_rand_reset.964986581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.382023511 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 399895052 ps |
| CPU time | 2.47 seconds |
| Started | Oct 12 12:36:36 AM UTC 24 |
| Finished | Oct 12 12:36:39 AM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382023511 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.382023511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/0.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.529103825 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 4477308637 ps |
| CPU time | 23.95 seconds |
| Started | Oct 12 12:36:37 AM UTC 24 |
| Finished | Oct 12 12:37:02 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529103825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_same_csr_outstanding.529103825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/0.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2926505144 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 492396068 ps |
| CPU time | 3.35 seconds |
| Started | Oct 12 12:36:36 AM UTC 24 |
| Finished | Oct 12 12:36:40 AM UTC 24 |
| Peak memory | 227808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926505144 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2926505144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/0.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3299917665 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 4571531853 ps |
| CPU time | 6.7 seconds |
| Started | Oct 12 12:36:36 AM UTC 24 |
| Finished | Oct 12 12:36:43 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299917665 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_intg_err.3299917665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/0.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3504491954 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 980068475 ps |
| CPU time | 7.01 seconds |
| Started | Oct 12 12:36:39 AM UTC 24 |
| Finished | Oct 12 12:36:47 AM UTC 24 |
| Peak memory | 211572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504491954 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_aliasing.3504491954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/1.adc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1022587825 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1037084188 ps |
| CPU time | 3.74 seconds |
| Started | Oct 12 12:36:38 AM UTC 24 |
| Finished | Oct 12 12:36:43 AM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022587825 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_reset.1022587825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/1.adc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1805632618 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 553342287 ps |
| CPU time | 1.75 seconds |
| Started | Oct 12 12:36:40 AM UTC 24 |
| Finished | Oct 12 12:36:42 AM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1805632618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_cs r_mem_rw_with_rand_reset.1805632618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2270341954 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 411384537 ps |
| CPU time | 3.26 seconds |
| Started | Oct 12 12:36:38 AM UTC 24 |
| Finished | Oct 12 12:36:43 AM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270341954 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2270341954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/1.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.3598377990 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 389089795 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 12:36:38 AM UTC 24 |
| Finished | Oct 12 12:36:41 AM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598377990 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3598377990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/1.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2468351266 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 2319644411 ps |
| CPU time | 7.47 seconds |
| Started | Oct 12 12:36:40 AM UTC 24 |
| Finished | Oct 12 12:36:48 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468351266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_same_csr_outstanding.2468351266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/1.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.20938024 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 8291204437 ps |
| CPU time | 10.75 seconds |
| Started | Oct 12 12:36:37 AM UTC 24 |
| Finished | Oct 12 12:36:49 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20938024 -assert nopostproc +UVM_TESTN AME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_intg_err.20938024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/1.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1359596895 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 843917505 ps |
| CPU time | 1.54 seconds |
| Started | Oct 12 12:37:14 AM UTC 24 |
| Finished | Oct 12 12:37:17 AM UTC 24 |
| Peak memory | 210696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1359596895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_c sr_mem_rw_with_rand_reset.1359596895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.478917326 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 386987627 ps |
| CPU time | 2.76 seconds |
| Started | Oct 12 12:37:13 AM UTC 24 |
| Finished | Oct 12 12:37:17 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478917326 -assert nopostproc +UVM_TESTNAME=adc_ ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.478917326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/10.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.3121901533 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 424904415 ps |
| CPU time | 1.27 seconds |
| Started | Oct 12 12:37:12 AM UTC 24 |
| Finished | Oct 12 12:37:14 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121901533 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.3121901533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/10.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2843362046 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 5087604258 ps |
| CPU time | 13.22 seconds |
| Started | Oct 12 12:37:13 AM UTC 24 |
| Finished | Oct 12 12:37:27 AM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843362046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_same_csr_outstanding.2843362046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/10.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.4177878052 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 491967001 ps |
| CPU time | 1.95 seconds |
| Started | Oct 12 12:37:11 AM UTC 24 |
| Finished | Oct 12 12:37:14 AM UTC 24 |
| Peak memory | 221076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177878052 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.4177878052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/10.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.515427769 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 8639467883 ps |
| CPU time | 8.94 seconds |
| Started | Oct 12 12:37:12 AM UTC 24 |
| Finished | Oct 12 12:37:22 AM UTC 24 |
| Peak memory | 211392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515427769 -assert nopostproc +UVM_TEST NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_intg_err.515427769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/10.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1188141646 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 482632256 ps |
| CPU time | 2.68 seconds |
| Started | Oct 12 12:37:17 AM UTC 24 |
| Finished | Oct 12 12:37:20 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1188141646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_c sr_mem_rw_with_rand_reset.1188141646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1036567403 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 535524911 ps |
| CPU time | 1.59 seconds |
| Started | Oct 12 12:37:16 AM UTC 24 |
| Finished | Oct 12 12:37:19 AM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036567403 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1036567403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/11.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.2870263481 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 332432635 ps |
| CPU time | 2.61 seconds |
| Started | Oct 12 12:37:15 AM UTC 24 |
| Finished | Oct 12 12:37:19 AM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870263481 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.2870263481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/11.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.680989401 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 2875294198 ps |
| CPU time | 5.79 seconds |
| Started | Oct 12 12:37:16 AM UTC 24 |
| Finished | Oct 12 12:37:23 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680989401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_same_csr_outstanding.680989401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/11.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.125006931 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 313740920 ps |
| CPU time | 3.85 seconds |
| Started | Oct 12 12:37:14 AM UTC 24 |
| Finished | Oct 12 12:37:19 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125006931 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.125006931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/11.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.521905591 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 646200392 ps |
| CPU time | 1.74 seconds |
| Started | Oct 12 12:37:20 AM UTC 24 |
| Finished | Oct 12 12:37:23 AM UTC 24 |
| Peak memory | 211224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=521905591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_cs r_mem_rw_with_rand_reset.521905591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.291220809 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 474732134 ps |
| CPU time | 1.4 seconds |
| Started | Oct 12 12:37:20 AM UTC 24 |
| Finished | Oct 12 12:37:22 AM UTC 24 |
| Peak memory | 211040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291220809 -assert nopostproc +UVM_TESTNAME=adc_ ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.291220809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/12.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.369388674 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 338238903 ps |
| CPU time | 2.2 seconds |
| Started | Oct 12 12:37:18 AM UTC 24 |
| Finished | Oct 12 12:37:21 AM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369388674 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.369388674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/12.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2528513201 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 4630440385 ps |
| CPU time | 13.51 seconds |
| Started | Oct 12 12:37:20 AM UTC 24 |
| Finished | Oct 12 12:37:35 AM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528513201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_same_csr_outstanding.2528513201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/12.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2220988380 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 1018821510 ps |
| CPU time | 4.47 seconds |
| Started | Oct 12 12:37:18 AM UTC 24 |
| Finished | Oct 12 12:37:23 AM UTC 24 |
| Peak memory | 221468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220988380 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.2220988380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/12.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.742895611 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 4594676146 ps |
| CPU time | 8.71 seconds |
| Started | Oct 12 12:37:18 AM UTC 24 |
| Finished | Oct 12 12:37:27 AM UTC 24 |
| Peak memory | 211536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742895611 -assert nopostproc +UVM_TEST NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_intg_err.742895611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/12.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2572297427 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 478221534 ps |
| CPU time | 2.88 seconds |
| Started | Oct 12 12:37:24 AM UTC 24 |
| Finished | Oct 12 12:37:28 AM UTC 24 |
| Peak memory | 211036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2572297427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_c sr_mem_rw_with_rand_reset.2572297427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2169065031 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 377058321 ps |
| CPU time | 2.63 seconds |
| Started | Oct 12 12:37:24 AM UTC 24 |
| Finished | Oct 12 12:37:28 AM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169065031 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.2169065031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/13.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.1504533245 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 518140203 ps |
| CPU time | 3.36 seconds |
| Started | Oct 12 12:37:24 AM UTC 24 |
| Finished | Oct 12 12:37:28 AM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504533245 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1504533245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/13.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3922925240 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 1777985287 ps |
| CPU time | 3.49 seconds |
| Started | Oct 12 12:37:24 AM UTC 24 |
| Finished | Oct 12 12:37:29 AM UTC 24 |
| Peak memory | 211060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922925240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_same_csr_outstanding.3922925240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/13.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2696235062 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 336637677 ps |
| CPU time | 3.67 seconds |
| Started | Oct 12 12:37:20 AM UTC 24 |
| Finished | Oct 12 12:37:25 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696235062 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.2696235062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/13.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3536659088 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 4434991045 ps |
| CPU time | 6.27 seconds |
| Started | Oct 12 12:37:21 AM UTC 24 |
| Finished | Oct 12 12:37:29 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536659088 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_intg_err.3536659088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/13.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.4081388709 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 532385604 ps |
| CPU time | 1.89 seconds |
| Started | Oct 12 12:37:28 AM UTC 24 |
| Finished | Oct 12 12:37:32 AM UTC 24 |
| Peak memory | 211172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4081388709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_c sr_mem_rw_with_rand_reset.4081388709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1265227915 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 485585608 ps |
| CPU time | 2.77 seconds |
| Started | Oct 12 12:37:24 AM UTC 24 |
| Finished | Oct 12 12:37:28 AM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265227915 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1265227915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/14.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.1802125102 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 453433682 ps |
| CPU time | 2.03 seconds |
| Started | Oct 12 12:37:24 AM UTC 24 |
| Finished | Oct 12 12:37:28 AM UTC 24 |
| Peak memory | 211292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802125102 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.1802125102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/14.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2763616218 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 4749032768 ps |
| CPU time | 5.45 seconds |
| Started | Oct 12 12:37:26 AM UTC 24 |
| Finished | Oct 12 12:37:33 AM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763616218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_same_csr_outstanding.2763616218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/14.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1460823548 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 441893842 ps |
| CPU time | 3.28 seconds |
| Started | Oct 12 12:37:24 AM UTC 24 |
| Finished | Oct 12 12:37:29 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460823548 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1460823548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/14.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.561681611 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 8744733261 ps |
| CPU time | 12.2 seconds |
| Started | Oct 12 12:37:24 AM UTC 24 |
| Finished | Oct 12 12:37:38 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561681611 -assert nopostproc +UVM_TEST NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_intg_err.561681611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/14.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2980297732 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 620015815 ps |
| CPU time | 1.99 seconds |
| Started | Oct 12 12:37:36 AM UTC 24 |
| Finished | Oct 12 12:37:39 AM UTC 24 |
| Peak memory | 211024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2980297732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_c sr_mem_rw_with_rand_reset.2980297732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1401948139 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 373054539 ps |
| CPU time | 1.47 seconds |
| Started | Oct 12 12:37:29 AM UTC 24 |
| Finished | Oct 12 12:37:31 AM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401948139 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.1401948139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/15.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.2946781822 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 368865669 ps |
| CPU time | 2.88 seconds |
| Started | Oct 12 12:37:29 AM UTC 24 |
| Finished | Oct 12 12:37:33 AM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946781822 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.2946781822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/15.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.532793903 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 4692681802 ps |
| CPU time | 8.24 seconds |
| Started | Oct 12 12:37:36 AM UTC 24 |
| Finished | Oct 12 12:37:45 AM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532793903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_same_csr_outstanding.532793903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/15.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1699759305 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 430213426 ps |
| CPU time | 3.43 seconds |
| Started | Oct 12 12:37:28 AM UTC 24 |
| Finished | Oct 12 12:37:33 AM UTC 24 |
| Peak memory | 227856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699759305 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1699759305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/15.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.751666329 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 8198566566 ps |
| CPU time | 13.83 seconds |
| Started | Oct 12 12:37:28 AM UTC 24 |
| Finished | Oct 12 12:37:44 AM UTC 24 |
| Peak memory | 211432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751666329 -assert nopostproc +UVM_TEST NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_intg_err.751666329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/15.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.4011431033 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 545332310 ps |
| CPU time | 1.4 seconds |
| Started | Oct 12 12:37:37 AM UTC 24 |
| Finished | Oct 12 12:37:40 AM UTC 24 |
| Peak memory | 211232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4011431033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_c sr_mem_rw_with_rand_reset.4011431033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1672970727 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 443991086 ps |
| CPU time | 3.1 seconds |
| Started | Oct 12 12:37:36 AM UTC 24 |
| Finished | Oct 12 12:37:40 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672970727 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.1672970727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/16.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.2058671578 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 357343993 ps |
| CPU time | 2.54 seconds |
| Started | Oct 12 12:37:36 AM UTC 24 |
| Finished | Oct 12 12:37:40 AM UTC 24 |
| Peak memory | 211252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058671578 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.2058671578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/16.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1450882556 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 2396795777 ps |
| CPU time | 4.28 seconds |
| Started | Oct 12 12:37:37 AM UTC 24 |
| Finished | Oct 12 12:37:43 AM UTC 24 |
| Peak memory | 211188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450882556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_same_csr_outstanding.1450882556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/16.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.813181117 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 662909648 ps |
| CPU time | 3.01 seconds |
| Started | Oct 12 12:37:36 AM UTC 24 |
| Finished | Oct 12 12:37:40 AM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813181117 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.813181117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/16.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.764040759 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 8155076911 ps |
| CPU time | 30.72 seconds |
| Started | Oct 12 12:37:36 AM UTC 24 |
| Finished | Oct 12 12:38:08 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764040759 -assert nopostproc +UVM_TEST NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_intg_err.764040759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/16.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1404069927 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 539036164 ps |
| CPU time | 2.18 seconds |
| Started | Oct 12 12:37:39 AM UTC 24 |
| Finished | Oct 12 12:37:42 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1404069927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_c sr_mem_rw_with_rand_reset.1404069927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3458106256 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 379122932 ps |
| CPU time | 2.13 seconds |
| Started | Oct 12 12:37:38 AM UTC 24 |
| Finished | Oct 12 12:37:41 AM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458106256 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.3458106256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/17.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.172753761 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 393583792 ps |
| CPU time | 2.38 seconds |
| Started | Oct 12 12:37:37 AM UTC 24 |
| Finished | Oct 12 12:37:41 AM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172753761 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.172753761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/17.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2462053208 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 2880264813 ps |
| CPU time | 1.89 seconds |
| Started | Oct 12 12:37:38 AM UTC 24 |
| Finished | Oct 12 12:37:41 AM UTC 24 |
| Peak memory | 211108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462053208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_same_csr_outstanding.2462053208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/17.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3466077962 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 828530766 ps |
| CPU time | 4.24 seconds |
| Started | Oct 12 12:37:37 AM UTC 24 |
| Finished | Oct 12 12:37:43 AM UTC 24 |
| Peak memory | 227540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466077962 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.3466077962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/17.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3840754188 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 8087536485 ps |
| CPU time | 9.34 seconds |
| Started | Oct 12 12:37:37 AM UTC 24 |
| Finished | Oct 12 12:37:48 AM UTC 24 |
| Peak memory | 211452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840754188 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_intg_err.3840754188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/17.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1374492457 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 321431519 ps |
| CPU time | 2.67 seconds |
| Started | Oct 12 12:37:42 AM UTC 24 |
| Finished | Oct 12 12:37:46 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1374492457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_c sr_mem_rw_with_rand_reset.1374492457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.643459693 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 495610837 ps |
| CPU time | 2.24 seconds |
| Started | Oct 12 12:37:41 AM UTC 24 |
| Finished | Oct 12 12:37:44 AM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643459693 -assert nopostproc +UVM_TESTNAME=adc_ ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.643459693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/18.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.1899974864 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 455644291 ps |
| CPU time | 3.13 seconds |
| Started | Oct 12 12:37:41 AM UTC 24 |
| Finished | Oct 12 12:37:45 AM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899974864 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.1899974864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/18.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3919871660 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 1865590418 ps |
| CPU time | 2.86 seconds |
| Started | Oct 12 12:37:41 AM UTC 24 |
| Finished | Oct 12 12:37:45 AM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919871660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_same_csr_outstanding.3919871660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/18.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1140861586 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 527186750 ps |
| CPU time | 4.16 seconds |
| Started | Oct 12 12:37:40 AM UTC 24 |
| Finished | Oct 12 12:37:45 AM UTC 24 |
| Peak memory | 221484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140861586 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1140861586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/18.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3980585994 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 8921920168 ps |
| CPU time | 5.45 seconds |
| Started | Oct 12 12:37:41 AM UTC 24 |
| Finished | Oct 12 12:37:48 AM UTC 24 |
| Peak memory | 211432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980585994 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_intg_err.3980585994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/18.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1118614590 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 384330723 ps |
| CPU time | 1.78 seconds |
| Started | Oct 12 12:37:44 AM UTC 24 |
| Finished | Oct 12 12:37:48 AM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1118614590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_c sr_mem_rw_with_rand_reset.1118614590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1119230309 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 386458597 ps |
| CPU time | 1.92 seconds |
| Started | Oct 12 12:37:43 AM UTC 24 |
| Finished | Oct 12 12:37:46 AM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119230309 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.1119230309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/19.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.747998616 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 462567807 ps |
| CPU time | 2.67 seconds |
| Started | Oct 12 12:37:43 AM UTC 24 |
| Finished | Oct 12 12:37:47 AM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747998616 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.747998616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/19.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1931242724 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 3653146768 ps |
| CPU time | 3.92 seconds |
| Started | Oct 12 12:37:43 AM UTC 24 |
| Finished | Oct 12 12:37:48 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931242724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_same_csr_outstanding.1931242724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/19.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.94368987 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 390132701 ps |
| CPU time | 3.97 seconds |
| Started | Oct 12 12:37:42 AM UTC 24 |
| Finished | Oct 12 12:37:47 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94368987 -assert nopostproc +UVM_TESTNAME=adc_ctrl _base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.94368987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/19.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1513084407 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 4734231539 ps |
| CPU time | 3.85 seconds |
| Started | Oct 12 12:37:42 AM UTC 24 |
| Finished | Oct 12 12:37:47 AM UTC 24 |
| Peak memory | 211684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513084407 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_intg_err.1513084407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/19.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.637845867 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 648321672 ps |
| CPU time | 2.93 seconds |
| Started | Oct 12 12:36:43 AM UTC 24 |
| Finished | Oct 12 12:36:47 AM UTC 24 |
| Peak memory | 211180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637845867 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_aliasing.637845867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/2.adc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3631841995 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 26301986597 ps |
| CPU time | 110.46 seconds |
| Started | Oct 12 12:36:43 AM UTC 24 |
| Finished | Oct 12 12:38:36 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631841995 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_bash.3631841995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/2.adc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2867386346 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 850739354 ps |
| CPU time | 2.59 seconds |
| Started | Oct 12 12:36:41 AM UTC 24 |
| Finished | Oct 12 12:36:45 AM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867386346 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_reset.2867386346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/2.adc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.4163224210 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 474668160 ps |
| CPU time | 1.33 seconds |
| Started | Oct 12 12:36:44 AM UTC 24 |
| Finished | Oct 12 12:36:47 AM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4163224210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_cs r_mem_rw_with_rand_reset.4163224210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1703555608 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 429377962 ps |
| CPU time | 2.19 seconds |
| Started | Oct 12 12:36:42 AM UTC 24 |
| Finished | Oct 12 12:36:45 AM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703555608 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1703555608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/2.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.3874035771 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 448169714 ps |
| CPU time | 1.68 seconds |
| Started | Oct 12 12:36:41 AM UTC 24 |
| Finished | Oct 12 12:36:44 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874035771 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.3874035771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/2.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1981001322 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 4409831202 ps |
| CPU time | 4.76 seconds |
| Started | Oct 12 12:36:44 AM UTC 24 |
| Finished | Oct 12 12:36:50 AM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981001322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_same_csr_outstanding.1981001322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/2.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2208810563 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1162298766 ps |
| CPU time | 2.33 seconds |
| Started | Oct 12 12:36:41 AM UTC 24 |
| Finished | Oct 12 12:36:44 AM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208810563 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2208810563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/2.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.592336614 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 5007385162 ps |
| CPU time | 11.73 seconds |
| Started | Oct 12 12:36:41 AM UTC 24 |
| Finished | Oct 12 12:36:54 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592336614 -assert nopostproc +UVM_TEST NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_intg_err.592336614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/2.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.2796636180 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 358030595 ps |
| CPU time | 1.91 seconds |
| Started | Oct 12 12:37:45 AM UTC 24 |
| Finished | Oct 12 12:37:48 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796636180 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2796636180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/20.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.3543807138 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 307213948 ps |
| CPU time | 1.85 seconds |
| Started | Oct 12 12:37:46 AM UTC 24 |
| Finished | Oct 12 12:37:49 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543807138 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.3543807138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/21.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.2311328846 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 370559406 ps |
| CPU time | 2.06 seconds |
| Started | Oct 12 12:37:46 AM UTC 24 |
| Finished | Oct 12 12:37:49 AM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311328846 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.2311328846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/22.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.2305681621 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 390489619 ps |
| CPU time | 1.53 seconds |
| Started | Oct 12 12:37:46 AM UTC 24 |
| Finished | Oct 12 12:37:49 AM UTC 24 |
| Peak memory | 209580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305681621 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.2305681621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/23.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.953617781 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 466571933 ps |
| CPU time | 2.64 seconds |
| Started | Oct 12 12:37:46 AM UTC 24 |
| Finished | Oct 12 12:37:50 AM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953617781 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.953617781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/24.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.2496306125 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 532975201 ps |
| CPU time | 1.07 seconds |
| Started | Oct 12 12:37:47 AM UTC 24 |
| Finished | Oct 12 12:37:49 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496306125 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.2496306125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/25.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.2702721709 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 378781561 ps |
| CPU time | 1.1 seconds |
| Started | Oct 12 12:37:47 AM UTC 24 |
| Finished | Oct 12 12:37:49 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702721709 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2702721709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/26.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.1479464155 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 501169781 ps |
| CPU time | 1.14 seconds |
| Started | Oct 12 12:37:47 AM UTC 24 |
| Finished | Oct 12 12:37:49 AM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479464155 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.1479464155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/27.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.311554048 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 329720820 ps |
| CPU time | 1.08 seconds |
| Started | Oct 12 12:37:48 AM UTC 24 |
| Finished | Oct 12 12:37:50 AM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311554048 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.311554048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/28.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.2864619238 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 336651640 ps |
| CPU time | 1.69 seconds |
| Started | Oct 12 12:37:48 AM UTC 24 |
| Finished | Oct 12 12:37:51 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864619238 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.2864619238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/29.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2905381163 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 819454272 ps |
| CPU time | 6.61 seconds |
| Started | Oct 12 12:36:49 AM UTC 24 |
| Finished | Oct 12 12:36:57 AM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905381163 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_aliasing.2905381163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/3.adc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1491127770 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 45853590965 ps |
| CPU time | 116.3 seconds |
| Started | Oct 12 12:36:49 AM UTC 24 |
| Finished | Oct 12 12:38:47 AM UTC 24 |
| Peak memory | 211364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491127770 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_bash.1491127770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/3.adc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.542333127 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1164880055 ps |
| CPU time | 6.11 seconds |
| Started | Oct 12 12:36:49 AM UTC 24 |
| Finished | Oct 12 12:36:56 AM UTC 24 |
| Peak memory | 211304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542333127 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_reset.542333127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/3.adc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.972413789 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 525164691 ps |
| CPU time | 2.14 seconds |
| Started | Oct 12 12:36:49 AM UTC 24 |
| Finished | Oct 12 12:36:52 AM UTC 24 |
| Peak memory | 211168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=972413789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr _mem_rw_with_rand_reset.972413789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1521376396 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 329384390 ps |
| CPU time | 2.64 seconds |
| Started | Oct 12 12:36:49 AM UTC 24 |
| Finished | Oct 12 12:36:52 AM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521376396 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.1521376396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/3.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.3500336668 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 382950433 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 12:36:49 AM UTC 24 |
| Finished | Oct 12 12:36:51 AM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500336668 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.3500336668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/3.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.573573598 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 2729777963 ps |
| CPU time | 12.82 seconds |
| Started | Oct 12 12:36:49 AM UTC 24 |
| Finished | Oct 12 12:37:03 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573573598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_same_csr_outstanding.573573598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/3.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2489728958 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 552409694 ps |
| CPU time | 4.58 seconds |
| Started | Oct 12 12:36:44 AM UTC 24 |
| Finished | Oct 12 12:36:50 AM UTC 24 |
| Peak memory | 211696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489728958 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2489728958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/3.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.970903052 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 4031108662 ps |
| CPU time | 19.16 seconds |
| Started | Oct 12 12:36:44 AM UTC 24 |
| Finished | Oct 12 12:37:05 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970903052 -assert nopostproc +UVM_TEST NAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_intg_err.970903052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/3.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/30.adc_ctrl_intr_test.595633606 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 339383060 ps |
| CPU time | 1.92 seconds |
| Started | Oct 12 12:37:48 AM UTC 24 |
| Finished | Oct 12 12:37:51 AM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595633606 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.595633606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/30.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/31.adc_ctrl_intr_test.3185851504 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 311334094 ps |
| CPU time | 1.86 seconds |
| Started | Oct 12 12:37:48 AM UTC 24 |
| Finished | Oct 12 12:37:51 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185851504 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3185851504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/31.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/32.adc_ctrl_intr_test.3725617848 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 541978990 ps |
| CPU time | 1.16 seconds |
| Started | Oct 12 12:37:48 AM UTC 24 |
| Finished | Oct 12 12:37:51 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725617848 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.3725617848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/32.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/33.adc_ctrl_intr_test.2161364099 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 360016682 ps |
| CPU time | 1.05 seconds |
| Started | Oct 12 12:37:48 AM UTC 24 |
| Finished | Oct 12 12:37:50 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161364099 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.2161364099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/33.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/34.adc_ctrl_intr_test.4063434764 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 502884523 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 12:37:49 AM UTC 24 |
| Finished | Oct 12 12:37:52 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063434764 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.4063434764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/34.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/35.adc_ctrl_intr_test.3150677781 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 572213367 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 12:37:50 AM UTC 24 |
| Finished | Oct 12 12:37:52 AM UTC 24 |
| Peak memory | 211084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150677781 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.3150677781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/35.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/36.adc_ctrl_intr_test.2467756648 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 486723128 ps |
| CPU time | 2.93 seconds |
| Started | Oct 12 12:37:50 AM UTC 24 |
| Finished | Oct 12 12:37:54 AM UTC 24 |
| Peak memory | 211292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467756648 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2467756648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/36.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/37.adc_ctrl_intr_test.2959481078 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 489957152 ps |
| CPU time | 3.1 seconds |
| Started | Oct 12 12:37:50 AM UTC 24 |
| Finished | Oct 12 12:37:54 AM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959481078 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.2959481078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/37.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/38.adc_ctrl_intr_test.767822530 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 551787558 ps |
| CPU time | 1.04 seconds |
| Started | Oct 12 12:37:50 AM UTC 24 |
| Finished | Oct 12 12:37:52 AM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767822530 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.767822530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/38.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/39.adc_ctrl_intr_test.3839661739 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 405944229 ps |
| CPU time | 1.18 seconds |
| Started | Oct 12 12:37:50 AM UTC 24 |
| Finished | Oct 12 12:37:52 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839661739 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.3839661739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/39.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1088112171 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 856685638 ps |
| CPU time | 2.79 seconds |
| Started | Oct 12 12:36:54 AM UTC 24 |
| Finished | Oct 12 12:36:57 AM UTC 24 |
| Peak memory | 211176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088112171 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_aliasing.1088112171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/4.adc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.946877969 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 24486320297 ps |
| CPU time | 41.72 seconds |
| Started | Oct 12 12:36:53 AM UTC 24 |
| Finished | Oct 12 12:37:37 AM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946877969 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_bash.946877969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/4.adc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2219459048 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 880379807 ps |
| CPU time | 1.31 seconds |
| Started | Oct 12 12:36:51 AM UTC 24 |
| Finished | Oct 12 12:36:54 AM UTC 24 |
| Peak memory | 210884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219459048 -assert nopostproc +UVM_TESTNA ME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_reset.2219459048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/4.adc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.4201531973 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 479652292 ps |
| CPU time | 1.71 seconds |
| Started | Oct 12 12:36:55 AM UTC 24 |
| Finished | Oct 12 12:36:57 AM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4201531973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_cs r_mem_rw_with_rand_reset.4201531973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2433330824 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 313317039 ps |
| CPU time | 1.53 seconds |
| Started | Oct 12 12:36:52 AM UTC 24 |
| Finished | Oct 12 12:36:55 AM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433330824 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.2433330824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/4.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_intr_test.1696702307 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 477986264 ps |
| CPU time | 2.7 seconds |
| Started | Oct 12 12:36:51 AM UTC 24 |
| Finished | Oct 12 12:36:55 AM UTC 24 |
| Peak memory | 210832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696702307 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.1696702307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/4.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1998545888 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 5175843950 ps |
| CPU time | 4.98 seconds |
| Started | Oct 12 12:36:54 AM UTC 24 |
| Finished | Oct 12 12:37:00 AM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998545888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_same_csr_outstanding.1998545888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/4.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_errors.513778769 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 397264327 ps |
| CPU time | 2.67 seconds |
| Started | Oct 12 12:36:49 AM UTC 24 |
| Finished | Oct 12 12:36:53 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513778769 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.513778769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/4.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/40.adc_ctrl_intr_test.470661411 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 483264832 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 12:37:50 AM UTC 24 |
| Finished | Oct 12 12:37:52 AM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470661411 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.470661411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/40.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/41.adc_ctrl_intr_test.2802304436 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 486202883 ps |
| CPU time | 1.05 seconds |
| Started | Oct 12 12:37:50 AM UTC 24 |
| Finished | Oct 12 12:37:52 AM UTC 24 |
| Peak memory | 209580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802304436 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.2802304436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/41.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/42.adc_ctrl_intr_test.3837007091 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 362987959 ps |
| CPU time | 1.76 seconds |
| Started | Oct 12 12:37:51 AM UTC 24 |
| Finished | Oct 12 12:37:54 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837007091 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.3837007091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/42.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/43.adc_ctrl_intr_test.3661117044 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 487782923 ps |
| CPU time | 1.55 seconds |
| Started | Oct 12 12:37:51 AM UTC 24 |
| Finished | Oct 12 12:37:54 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661117044 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.3661117044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/43.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/44.adc_ctrl_intr_test.3254971176 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 425567359 ps |
| CPU time | 1.03 seconds |
| Started | Oct 12 12:37:51 AM UTC 24 |
| Finished | Oct 12 12:37:53 AM UTC 24 |
| Peak memory | 209520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254971176 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.3254971176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/44.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/45.adc_ctrl_intr_test.212259836 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 309246171 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 12:37:51 AM UTC 24 |
| Finished | Oct 12 12:37:53 AM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212259836 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.212259836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/45.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/46.adc_ctrl_intr_test.105410432 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 404732430 ps |
| CPU time | 2.51 seconds |
| Started | Oct 12 12:37:52 AM UTC 24 |
| Finished | Oct 12 12:37:56 AM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105410432 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.105410432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/46.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/47.adc_ctrl_intr_test.2706600346 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 289842124 ps |
| CPU time | 2.08 seconds |
| Started | Oct 12 12:37:52 AM UTC 24 |
| Finished | Oct 12 12:37:55 AM UTC 24 |
| Peak memory | 211036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706600346 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.2706600346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/47.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/48.adc_ctrl_intr_test.1225028437 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 306346231 ps |
| CPU time | 1.58 seconds |
| Started | Oct 12 12:37:52 AM UTC 24 |
| Finished | Oct 12 12:37:55 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225028437 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.1225028437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/48.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/49.adc_ctrl_intr_test.4033327998 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 463117277 ps |
| CPU time | 2.07 seconds |
| Started | Oct 12 12:37:52 AM UTC 24 |
| Finished | Oct 12 12:37:55 AM UTC 24 |
| Peak memory | 211292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033327998 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.4033327998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/49.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.155793172 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 605985353 ps |
| CPU time | 2.25 seconds |
| Started | Oct 12 12:36:58 AM UTC 24 |
| Finished | Oct 12 12:37:01 AM UTC 24 |
| Peak memory | 211168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=155793172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr _mem_rw_with_rand_reset.155793172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_rw.490205150 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 371879410 ps |
| CPU time | 1.68 seconds |
| Started | Oct 12 12:36:57 AM UTC 24 |
| Finished | Oct 12 12:37:00 AM UTC 24 |
| Peak memory | 211040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490205150 -assert nopostproc +UVM_TESTNAME=adc_ ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.490205150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/5.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_intr_test.2786850345 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 463026125 ps |
| CPU time | 1.41 seconds |
| Started | Oct 12 12:36:56 AM UTC 24 |
| Finished | Oct 12 12:36:58 AM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786850345 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.2786850345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/5.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.459150665 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 4929274683 ps |
| CPU time | 4.4 seconds |
| Started | Oct 12 12:36:58 AM UTC 24 |
| Finished | Oct 12 12:37:04 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459150665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_same_csr_outstanding.459150665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/5.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1030934971 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 439233022 ps |
| CPU time | 2.2 seconds |
| Started | Oct 12 12:36:55 AM UTC 24 |
| Finished | Oct 12 12:36:58 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030934971 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.1030934971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/5.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2077692864 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 3643055718 ps |
| CPU time | 6.18 seconds |
| Started | Oct 12 12:36:56 AM UTC 24 |
| Finished | Oct 12 12:37:03 AM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077692864 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_intg_err.2077692864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/5.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3422088799 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 634995037 ps |
| CPU time | 2.32 seconds |
| Started | Oct 12 12:37:03 AM UTC 24 |
| Finished | Oct 12 12:37:06 AM UTC 24 |
| Peak memory | 211176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3422088799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_cs r_mem_rw_with_rand_reset.3422088799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1240690075 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 419246528 ps |
| CPU time | 2.71 seconds |
| Started | Oct 12 12:37:00 AM UTC 24 |
| Finished | Oct 12 12:37:04 AM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240690075 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.1240690075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/6.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_intr_test.764927382 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 290918832 ps |
| CPU time | 2.26 seconds |
| Started | Oct 12 12:36:59 AM UTC 24 |
| Finished | Oct 12 12:37:03 AM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764927382 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.764927382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/6.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1832717332 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 4566163940 ps |
| CPU time | 14.38 seconds |
| Started | Oct 12 12:37:00 AM UTC 24 |
| Finished | Oct 12 12:37:16 AM UTC 24 |
| Peak memory | 211320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832717332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_same_csr_outstanding.1832717332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/6.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_errors.780147260 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 445858371 ps |
| CPU time | 4.38 seconds |
| Started | Oct 12 12:36:58 AM UTC 24 |
| Finished | Oct 12 12:37:04 AM UTC 24 |
| Peak memory | 211384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780147260 -assert nopostproc +UVM_TESTNAME=adc_ctr l_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.780147260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/6.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2865772359 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 4385938720 ps |
| CPU time | 6.18 seconds |
| Started | Oct 12 12:36:59 AM UTC 24 |
| Finished | Oct 12 12:37:06 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865772359 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_intg_err.2865772359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/6.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1267945834 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 489584646 ps |
| CPU time | 2.21 seconds |
| Started | Oct 12 12:37:05 AM UTC 24 |
| Finished | Oct 12 12:37:08 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1267945834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_cs r_mem_rw_with_rand_reset.1267945834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2727541558 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 495783715 ps |
| CPU time | 2.45 seconds |
| Started | Oct 12 12:37:04 AM UTC 24 |
| Finished | Oct 12 12:37:07 AM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727541558 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.2727541558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/7.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_intr_test.1507553829 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 304129315 ps |
| CPU time | 1.77 seconds |
| Started | Oct 12 12:37:04 AM UTC 24 |
| Finished | Oct 12 12:37:06 AM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507553829 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1507553829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/7.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1227907382 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 4828871637 ps |
| CPU time | 3.73 seconds |
| Started | Oct 12 12:37:04 AM UTC 24 |
| Finished | Oct 12 12:37:09 AM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227907382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_same_csr_outstanding.1227907382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/7.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1883647850 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 759539947 ps |
| CPU time | 2.9 seconds |
| Started | Oct 12 12:37:04 AM UTC 24 |
| Finished | Oct 12 12:37:08 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883647850 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.1883647850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/7.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1854550318 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 8514225852 ps |
| CPU time | 14.34 seconds |
| Started | Oct 12 12:37:04 AM UTC 24 |
| Finished | Oct 12 12:37:19 AM UTC 24 |
| Peak memory | 211456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854550318 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_intg_err.1854550318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/7.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3046063807 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 412331105 ps |
| CPU time | 2.48 seconds |
| Started | Oct 12 12:37:07 AM UTC 24 |
| Finished | Oct 12 12:37:11 AM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3046063807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_cs r_mem_rw_with_rand_reset.3046063807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_csr_rw.4050220654 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 572319324 ps |
| CPU time | 4.14 seconds |
| Started | Oct 12 12:37:06 AM UTC 24 |
| Finished | Oct 12 12:37:11 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050220654 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.4050220654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/8.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_intr_test.2260348310 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 415463293 ps |
| CPU time | 1.13 seconds |
| Started | Oct 12 12:37:06 AM UTC 24 |
| Finished | Oct 12 12:37:08 AM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260348310 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.2260348310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/8.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3162289067 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 3946807797 ps |
| CPU time | 7.45 seconds |
| Started | Oct 12 12:37:07 AM UTC 24 |
| Finished | Oct 12 12:37:16 AM UTC 24 |
| Peak memory | 211328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162289067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_same_csr_outstanding.3162289067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/8.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2182753072 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 4425158057 ps |
| CPU time | 7.58 seconds |
| Started | Oct 12 12:37:05 AM UTC 24 |
| Finished | Oct 12 12:37:14 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182753072 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_intg_err.2182753072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/8.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3038170485 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 540728091 ps |
| CPU time | 4.56 seconds |
| Started | Oct 12 12:37:10 AM UTC 24 |
| Finished | Oct 12 12:37:15 AM UTC 24 |
| Peak memory | 211176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3038170485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_cs r_mem_rw_with_rand_reset.3038170485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1228985821 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 491127130 ps |
| CPU time | 1.69 seconds |
| Started | Oct 12 12:37:10 AM UTC 24 |
| Finished | Oct 12 12:37:12 AM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228985821 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.1228985821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/9.adc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_intr_test.2432282134 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 455613305 ps |
| CPU time | 1.09 seconds |
| Started | Oct 12 12:37:10 AM UTC 24 |
| Finished | Oct 12 12:37:12 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432282134 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.2432282134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/9.adc_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2327308973 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 4346364906 ps |
| CPU time | 5.5 seconds |
| Started | Oct 12 12:37:10 AM UTC 24 |
| Finished | Oct 12 12:37:16 AM UTC 24 |
| Peak memory | 211724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327308973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_same_csr_outstanding.2327308973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/9.adc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2629411592 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 416281419 ps |
| CPU time | 3.65 seconds |
| Started | Oct 12 12:37:08 AM UTC 24 |
| Finished | Oct 12 12:37:13 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629411592 -assert nopostproc +UVM_TESTNAME=adc_ct rl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2629411592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/9.adc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3988736814 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 8399445257 ps |
| CPU time | 33.67 seconds |
| Started | Oct 12 12:37:08 AM UTC 24 |
| Finished | Oct 12 12:37:44 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988736814 -assert nopostproc +UVM_TES TNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_intg_err.3988736814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/9.adc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.3819577001 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 437913928 ps |
| CPU time | 2 seconds |
| Started | Oct 12 01:13:53 AM UTC 24 |
| Finished | Oct 12 01:13:56 AM UTC 24 |
| Peak memory | 208884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819577001 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.3819577001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/0.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt.301918559 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 490198295416 ps |
| CPU time | 420.22 seconds |
| Started | Oct 12 01:13:48 AM UTC 24 |
| Finished | Oct 12 01:20:54 AM UTC 24 |
| Peak memory | 210336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301918559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.301918559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/0.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled_fixed.95637061 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 327667153144 ps |
| CPU time | 224.86 seconds |
| Started | Oct 12 01:13:47 AM UTC 24 |
| Finished | Oct 12 01:17:36 AM UTC 24 |
| Peak memory | 210116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95637061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas e_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixed.95637061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/0.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup.2568711296 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 184311416861 ps |
| CPU time | 94.03 seconds |
| Started | Oct 12 01:13:50 AM UTC 24 |
| Finished | Oct 12 01:15:26 AM UTC 24 |
| Peak memory | 210116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568711296 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_wakeup.2568711296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/0.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_lowpower_counter.1632985573 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 31735463299 ps |
| CPU time | 23.01 seconds |
| Started | Oct 12 01:13:51 AM UTC 24 |
| Finished | Oct 12 01:14:16 AM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632985573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.1632985573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/0.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_poweron_counter.793380648 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 3594313977 ps |
| CPU time | 16.21 seconds |
| Started | Oct 12 01:13:51 AM UTC 24 |
| Finished | Oct 12 01:14:09 AM UTC 24 |
| Peak memory | 210064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793380648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.793380648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/0.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_smoke.1047836857 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5747716638 ps |
| CPU time | 9.12 seconds |
| Started | Oct 12 01:13:45 AM UTC 24 |
| Finished | Oct 12 01:13:56 AM UTC 24 |
| Peak memory | 210048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047836857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1047836857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/0.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.1096288808 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 492789845295 ps |
| CPU time | 1469.7 seconds |
| Started | Oct 12 01:13:57 AM UTC 24 |
| Finished | Oct 12 01:38:42 AM UTC 24 |
| Peak memory | 212792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096288808 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gating.1096288808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/1.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_both.2202627530 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 190489938834 ps |
| CPU time | 53.62 seconds |
| Started | Oct 12 01:13:57 AM UTC 24 |
| Finished | Oct 12 01:14:53 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202627530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.2202627530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/1.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt.1625851934 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 163540126564 ps |
| CPU time | 129.95 seconds |
| Started | Oct 12 01:13:53 AM UTC 24 |
| Finished | Oct 12 01:16:05 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625851934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1625851934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/1.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3273695092 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 329228591140 ps |
| CPU time | 1182.25 seconds |
| Started | Oct 12 01:13:53 AM UTC 24 |
| Finished | Oct 12 01:33:48 AM UTC 24 |
| Peak memory | 212772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273695092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt_fixed.3273695092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/1.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled.1379608244 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 332749400119 ps |
| CPU time | 194.93 seconds |
| Started | Oct 12 01:13:53 AM UTC 24 |
| Finished | Oct 12 01:17:11 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379608244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.1379608244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/1.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled_fixed.3727318133 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 482178796451 ps |
| CPU time | 899.68 seconds |
| Started | Oct 12 01:13:53 AM UTC 24 |
| Finished | Oct 12 01:29:03 AM UTC 24 |
| Peak memory | 212700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727318133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixed.3727318133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/1.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup_fixed.2810543656 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 603474916707 ps |
| CPU time | 1488.51 seconds |
| Started | Oct 12 01:13:56 AM UTC 24 |
| Finished | Oct 12 01:38:59 AM UTC 24 |
| Peak memory | 212852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810543656 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_wakeup_fixed.2810543656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/1.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_lowpower_counter.1531601611 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 43239068160 ps |
| CPU time | 108.41 seconds |
| Started | Oct 12 01:13:58 AM UTC 24 |
| Finished | Oct 12 01:15:49 AM UTC 24 |
| Peak memory | 210060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531601611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.1531601611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/1.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_poweron_counter.3077107148 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3357866111 ps |
| CPU time | 1.97 seconds |
| Started | Oct 12 01:13:57 AM UTC 24 |
| Finished | Oct 12 01:14:01 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077107148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.3077107148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/1.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_sec_cm.3756144601 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 8236421929 ps |
| CPU time | 21.75 seconds |
| Started | Oct 12 01:14:02 AM UTC 24 |
| Finished | Oct 12 01:14:25 AM UTC 24 |
| Peak memory | 242368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756144601 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.3756144601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/1.adc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_smoke.1854540048 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5751407881 ps |
| CPU time | 3.35 seconds |
| Started | Oct 12 01:13:53 AM UTC 24 |
| Finished | Oct 12 01:13:58 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854540048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.1854540048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/1.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_alert_test.4171955748 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 308491906 ps |
| CPU time | 1.19 seconds |
| Started | Oct 12 01:24:26 AM UTC 24 |
| Finished | Oct 12 01:24:28 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171955748 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.4171955748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/10.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_both.2781291309 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 171705962347 ps |
| CPU time | 498.24 seconds |
| Started | Oct 12 01:23:41 AM UTC 24 |
| Finished | Oct 12 01:32:05 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781291309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.2781291309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/10.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt.2542288779 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 163835862565 ps |
| CPU time | 104.96 seconds |
| Started | Oct 12 01:23:04 AM UTC 24 |
| Finished | Oct 12 01:24:51 AM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542288779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.2542288779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/10.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt_fixed.47377717 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 166395138854 ps |
| CPU time | 453.6 seconds |
| Started | Oct 12 01:23:11 AM UTC 24 |
| Finished | Oct 12 01:30:50 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47377717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas e_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt_fixed.47377717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/10.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled.3372734473 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 164570201190 ps |
| CPU time | 481.46 seconds |
| Started | Oct 12 01:23:01 AM UTC 24 |
| Finished | Oct 12 01:31:08 AM UTC 24 |
| Peak memory | 210096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372734473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.3372734473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/10.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled_fixed.474704777 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 162389742809 ps |
| CPU time | 86.86 seconds |
| Started | Oct 12 01:23:01 AM UTC 24 |
| Finished | Oct 12 01:24:29 AM UTC 24 |
| Peak memory | 210048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474704777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixed.474704777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/10.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.1387511458 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 316300560879 ps |
| CPU time | 456.78 seconds |
| Started | Oct 12 01:23:27 AM UTC 24 |
| Finished | Oct 12 01:31:09 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387511458 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_wakeup.1387511458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/10.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup_fixed.4219956074 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 618461091132 ps |
| CPU time | 1897.16 seconds |
| Started | Oct 12 01:23:33 AM UTC 24 |
| Finished | Oct 12 01:55:29 AM UTC 24 |
| Peak memory | 212792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219956074 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_wakeup_fixed.4219956074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/10.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_fsm_reset.3992475953 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 91241710191 ps |
| CPU time | 351.9 seconds |
| Started | Oct 12 01:24:12 AM UTC 24 |
| Finished | Oct 12 01:30:07 AM UTC 24 |
| Peak memory | 210460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992475953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.3992475953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/10.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_lowpower_counter.1726298154 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 44498749351 ps |
| CPU time | 180.67 seconds |
| Started | Oct 12 01:23:51 AM UTC 24 |
| Finished | Oct 12 01:26:55 AM UTC 24 |
| Peak memory | 210248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726298154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1726298154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/10.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_poweron_counter.3244844512 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 4414014351 ps |
| CPU time | 4.86 seconds |
| Started | Oct 12 01:23:44 AM UTC 24 |
| Finished | Oct 12 01:23:50 AM UTC 24 |
| Peak memory | 209984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244844512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3244844512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/10.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_smoke.4276759445 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 5566539617 ps |
| CPU time | 13.82 seconds |
| Started | Oct 12 01:22:56 AM UTC 24 |
| Finished | Oct 12 01:23:11 AM UTC 24 |
| Peak memory | 209992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276759445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.4276759445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/10.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all.3771631971 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 197612747026 ps |
| CPU time | 1242.67 seconds |
| Started | Oct 12 01:24:21 AM UTC 24 |
| Finished | Oct 12 01:45:16 AM UTC 24 |
| Peak memory | 223460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771631971 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.3771631971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/10.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_alert_test.239424210 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 470175653 ps |
| CPU time | 2.89 seconds |
| Started | Oct 12 01:25:20 AM UTC 24 |
| Finished | Oct 12 01:25:24 AM UTC 24 |
| Peak memory | 210060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239424210 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.239424210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/11.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_clock_gating.556811591 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 182918552568 ps |
| CPU time | 373.16 seconds |
| Started | Oct 12 01:24:38 AM UTC 24 |
| Finished | Oct 12 01:30:57 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556811591 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gating.556811591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/11.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt.1163650533 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 323126310416 ps |
| CPU time | 213.21 seconds |
| Started | Oct 12 01:24:30 AM UTC 24 |
| Finished | Oct 12 01:28:06 AM UTC 24 |
| Peak memory | 210232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163650533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.1163650533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/11.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1685295183 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 325284908986 ps |
| CPU time | 274.28 seconds |
| Started | Oct 12 01:24:37 AM UTC 24 |
| Finished | Oct 12 01:29:15 AM UTC 24 |
| Peak memory | 210048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685295183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt_fixed.1685295183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/11.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled_fixed.536058759 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 486988298082 ps |
| CPU time | 322.44 seconds |
| Started | Oct 12 01:24:29 AM UTC 24 |
| Finished | Oct 12 01:29:56 AM UTC 24 |
| Peak memory | 210064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536058759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixed.536058759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/11.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup_fixed.2190540702 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 607454216776 ps |
| CPU time | 1641.95 seconds |
| Started | Oct 12 01:24:37 AM UTC 24 |
| Finished | Oct 12 01:52:15 AM UTC 24 |
| Peak memory | 212704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190540702 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_wakeup_fixed.2190540702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/11.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_fsm_reset.3355886345 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 70239563221 ps |
| CPU time | 361.86 seconds |
| Started | Oct 12 01:25:10 AM UTC 24 |
| Finished | Oct 12 01:31:16 AM UTC 24 |
| Peak memory | 210540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355886345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3355886345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/11.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_lowpower_counter.2323977116 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 31692107894 ps |
| CPU time | 23.58 seconds |
| Started | Oct 12 01:25:09 AM UTC 24 |
| Finished | Oct 12 01:25:33 AM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323977116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.2323977116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/11.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_poweron_counter.4113237974 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 3650364549 ps |
| CPU time | 14.77 seconds |
| Started | Oct 12 01:25:03 AM UTC 24 |
| Finished | Oct 12 01:25:19 AM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113237974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.4113237974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/11.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_smoke.2065501474 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 5519561971 ps |
| CPU time | 6.91 seconds |
| Started | Oct 12 01:24:28 AM UTC 24 |
| Finished | Oct 12 01:24:36 AM UTC 24 |
| Peak memory | 210252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065501474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.2065501474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/11.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all.446799079 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 262351556270 ps |
| CPU time | 109.25 seconds |
| Started | Oct 12 01:25:19 AM UTC 24 |
| Finished | Oct 12 01:27:10 AM UTC 24 |
| Peak memory | 210124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446799079 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.446799079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/11.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_alert_test.91844477 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 386536792 ps |
| CPU time | 1.26 seconds |
| Started | Oct 12 01:27:10 AM UTC 24 |
| Finished | Oct 12 01:27:12 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91844477 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.91844477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/12.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_both.2890147554 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 165434275296 ps |
| CPU time | 268.14 seconds |
| Started | Oct 12 01:26:44 AM UTC 24 |
| Finished | Oct 12 01:31:15 AM UTC 24 |
| Peak memory | 210132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890147554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.2890147554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/12.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt.322161113 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 489070011484 ps |
| CPU time | 1308.38 seconds |
| Started | Oct 12 01:25:34 AM UTC 24 |
| Finished | Oct 12 01:47:36 AM UTC 24 |
| Peak memory | 212732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322161113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.322161113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/12.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1968706561 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 328997054516 ps |
| CPU time | 244.02 seconds |
| Started | Oct 12 01:25:35 AM UTC 24 |
| Finished | Oct 12 01:29:43 AM UTC 24 |
| Peak memory | 210028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968706561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt_fixed.1968706561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/12.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled.3862540084 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 163475031009 ps |
| CPU time | 81.59 seconds |
| Started | Oct 12 01:25:31 AM UTC 24 |
| Finished | Oct 12 01:26:55 AM UTC 24 |
| Peak memory | 210340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862540084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.3862540084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/12.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled_fixed.185081430 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 330511060430 ps |
| CPU time | 748.78 seconds |
| Started | Oct 12 01:25:34 AM UTC 24 |
| Finished | Oct 12 01:38:11 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185081430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fixed.185081430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/12.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup_fixed.589184937 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 592875948438 ps |
| CPU time | 2174.87 seconds |
| Started | Oct 12 01:26:12 AM UTC 24 |
| Finished | Oct 12 02:02:48 AM UTC 24 |
| Peak memory | 212836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589184937 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_wakeup_fixed.589184937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/12.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_fsm_reset.1157044442 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 133832704922 ps |
| CPU time | 586.45 seconds |
| Started | Oct 12 01:26:56 AM UTC 24 |
| Finished | Oct 12 01:36:48 AM UTC 24 |
| Peak memory | 210608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157044442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.1157044442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/12.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_lowpower_counter.1811894556 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 40420687796 ps |
| CPU time | 36.41 seconds |
| Started | Oct 12 01:26:56 AM UTC 24 |
| Finished | Oct 12 01:27:34 AM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811894556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.1811894556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/12.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_poweron_counter.1202365612 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 4045852953 ps |
| CPU time | 7.41 seconds |
| Started | Oct 12 01:26:48 AM UTC 24 |
| Finished | Oct 12 01:26:56 AM UTC 24 |
| Peak memory | 210060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202365612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.1202365612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/12.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_smoke.3843864918 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 5800789236 ps |
| CPU time | 6.76 seconds |
| Started | Oct 12 01:25:25 AM UTC 24 |
| Finished | Oct 12 01:25:33 AM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843864918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.3843864918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/12.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all.3759206460 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 163415842649 ps |
| CPU time | 115.74 seconds |
| Started | Oct 12 01:27:04 AM UTC 24 |
| Finished | Oct 12 01:29:02 AM UTC 24 |
| Peak memory | 210060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759206460 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.3759206460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/12.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.2497263574 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 6439030875 ps |
| CPU time | 28.59 seconds |
| Started | Oct 12 01:26:57 AM UTC 24 |
| Finished | Oct 12 01:27:27 AM UTC 24 |
| Peak memory | 220856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2497263574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 12.adc_ctrl_stress_all_with_rand_reset.2497263574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/12.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_alert_test.3166141750 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 516491823 ps |
| CPU time | 1.87 seconds |
| Started | Oct 12 01:28:34 AM UTC 24 |
| Finished | Oct 12 01:28:37 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166141750 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.3166141750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/13.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_clock_gating.2513169892 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 340436348778 ps |
| CPU time | 437.92 seconds |
| Started | Oct 12 01:27:43 AM UTC 24 |
| Finished | Oct 12 01:35:06 AM UTC 24 |
| Peak memory | 210060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513169892 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gating.2513169892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/13.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_both.1001836843 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 280996451701 ps |
| CPU time | 223.44 seconds |
| Started | Oct 12 01:27:48 AM UTC 24 |
| Finished | Oct 12 01:31:34 AM UTC 24 |
| Peak memory | 210328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001836843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.1001836843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/13.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt.2857028687 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 163725775769 ps |
| CPU time | 56.7 seconds |
| Started | Oct 12 01:27:24 AM UTC 24 |
| Finished | Oct 12 01:28:23 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857028687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.2857028687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/13.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt_fixed.505208817 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 497235614748 ps |
| CPU time | 347.03 seconds |
| Started | Oct 12 01:27:27 AM UTC 24 |
| Finished | Oct 12 01:33:18 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505208817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt_fixed.505208817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/13.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled.417865034 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 331447741409 ps |
| CPU time | 267.08 seconds |
| Started | Oct 12 01:27:13 AM UTC 24 |
| Finished | Oct 12 01:31:44 AM UTC 24 |
| Peak memory | 210132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417865034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.417865034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/13.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled_fixed.2770950383 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 164882977701 ps |
| CPU time | 104.62 seconds |
| Started | Oct 12 01:27:20 AM UTC 24 |
| Finished | Oct 12 01:29:07 AM UTC 24 |
| Peak memory | 210060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770950383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixed.2770950383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/13.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup_fixed.990733027 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 406843035738 ps |
| CPU time | 278.31 seconds |
| Started | Oct 12 01:27:35 AM UTC 24 |
| Finished | Oct 12 01:32:17 AM UTC 24 |
| Peak memory | 210172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990733027 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_wakeup_fixed.990733027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/13.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_fsm_reset.3267630937 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 127588488319 ps |
| CPU time | 712.69 seconds |
| Started | Oct 12 01:28:21 AM UTC 24 |
| Finished | Oct 12 01:40:22 AM UTC 24 |
| Peak memory | 213216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267630937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.3267630937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/13.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_lowpower_counter.3072612789 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 36536574872 ps |
| CPU time | 63.91 seconds |
| Started | Oct 12 01:28:20 AM UTC 24 |
| Finished | Oct 12 01:29:26 AM UTC 24 |
| Peak memory | 209992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072612789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3072612789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/13.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_poweron_counter.1995272959 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 4905467268 ps |
| CPU time | 11.12 seconds |
| Started | Oct 12 01:28:07 AM UTC 24 |
| Finished | Oct 12 01:28:20 AM UTC 24 |
| Peak memory | 209984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995272959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.1995272959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/13.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_smoke.4082756709 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 5900692594 ps |
| CPU time | 10.98 seconds |
| Started | Oct 12 01:27:11 AM UTC 24 |
| Finished | Oct 12 01:27:24 AM UTC 24 |
| Peak memory | 210124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082756709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.4082756709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/13.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1532785143 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 3738604312 ps |
| CPU time | 9.08 seconds |
| Started | Oct 12 01:28:23 AM UTC 24 |
| Finished | Oct 12 01:28:34 AM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1532785143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 13.adc_ctrl_stress_all_with_rand_reset.1532785143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/13.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_alert_test.4060954646 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 492700428 ps |
| CPU time | 2.92 seconds |
| Started | Oct 12 01:29:16 AM UTC 24 |
| Finished | Oct 12 01:29:20 AM UTC 24 |
| Peak memory | 210320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060954646 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.4060954646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/14.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_both.4175150865 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 512982639624 ps |
| CPU time | 593.45 seconds |
| Started | Oct 12 01:29:03 AM UTC 24 |
| Finished | Oct 12 01:39:03 AM UTC 24 |
| Peak memory | 210128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175150865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.4175150865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/14.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt_fixed.3945366477 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 324758305335 ps |
| CPU time | 832.18 seconds |
| Started | Oct 12 01:28:48 AM UTC 24 |
| Finished | Oct 12 01:42:48 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945366477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt_fixed.3945366477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/14.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled.3967716028 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 335785307114 ps |
| CPU time | 112.76 seconds |
| Started | Oct 12 01:28:41 AM UTC 24 |
| Finished | Oct 12 01:30:35 AM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967716028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3967716028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/14.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled_fixed.2718376760 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 173882423160 ps |
| CPU time | 574.08 seconds |
| Started | Oct 12 01:28:45 AM UTC 24 |
| Finished | Oct 12 01:38:25 AM UTC 24 |
| Peak memory | 210472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718376760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixed.2718376760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/14.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup.66416031 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 355227633671 ps |
| CPU time | 839.11 seconds |
| Started | Oct 12 01:28:51 AM UTC 24 |
| Finished | Oct 12 01:42:59 AM UTC 24 |
| Peak memory | 212784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66416031 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_wakeup.66416031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/14.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1930454600 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 602900783956 ps |
| CPU time | 1416.96 seconds |
| Started | Oct 12 01:28:52 AM UTC 24 |
| Finished | Oct 12 01:52:42 AM UTC 24 |
| Peak memory | 212784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930454600 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_wakeup_fixed.1930454600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/14.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_fsm_reset.764385278 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 96404020967 ps |
| CPU time | 575.64 seconds |
| Started | Oct 12 01:29:06 AM UTC 24 |
| Finished | Oct 12 01:38:48 AM UTC 24 |
| Peak memory | 210668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764385278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.764385278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/14.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_lowpower_counter.1187674377 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 25377690457 ps |
| CPU time | 10.24 seconds |
| Started | Oct 12 01:29:05 AM UTC 24 |
| Finished | Oct 12 01:29:17 AM UTC 24 |
| Peak memory | 210120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187674377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.1187674377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/14.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_poweron_counter.3610343491 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 3282409896 ps |
| CPU time | 7.66 seconds |
| Started | Oct 12 01:29:04 AM UTC 24 |
| Finished | Oct 12 01:29:13 AM UTC 24 |
| Peak memory | 209984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610343491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.3610343491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/14.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_smoke.3896349544 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 6074063170 ps |
| CPU time | 7.49 seconds |
| Started | Oct 12 01:28:38 AM UTC 24 |
| Finished | Oct 12 01:28:47 AM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896349544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.3896349544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/14.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all.1962523892 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 126082682633 ps |
| CPU time | 736.8 seconds |
| Started | Oct 12 01:29:13 AM UTC 24 |
| Finished | Oct 12 01:41:38 AM UTC 24 |
| Peak memory | 210400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962523892 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.1962523892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/14.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_alert_test.2577186627 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 473070289 ps |
| CPU time | 2.75 seconds |
| Started | Oct 12 01:30:18 AM UTC 24 |
| Finished | Oct 12 01:30:21 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577186627 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2577186627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/15.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_clock_gating.3910804606 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 330330329086 ps |
| CPU time | 245.61 seconds |
| Started | Oct 12 01:29:43 AM UTC 24 |
| Finished | Oct 12 01:33:52 AM UTC 24 |
| Peak memory | 210128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910804606 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gating.3910804606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/15.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt.664003990 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 163379685968 ps |
| CPU time | 192.47 seconds |
| Started | Oct 12 01:29:22 AM UTC 24 |
| Finished | Oct 12 01:32:38 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664003990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.664003990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/15.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3972581892 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 163860939575 ps |
| CPU time | 404.4 seconds |
| Started | Oct 12 01:29:27 AM UTC 24 |
| Finished | Oct 12 01:36:16 AM UTC 24 |
| Peak memory | 210108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972581892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt_fixed.3972581892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/15.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled.3477101519 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 336759783208 ps |
| CPU time | 931.53 seconds |
| Started | Oct 12 01:29:21 AM UTC 24 |
| Finished | Oct 12 01:45:01 AM UTC 24 |
| Peak memory | 212724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477101519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.3477101519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/15.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled_fixed.2846871157 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 484814886204 ps |
| CPU time | 510 seconds |
| Started | Oct 12 01:29:21 AM UTC 24 |
| Finished | Oct 12 01:37:56 AM UTC 24 |
| Peak memory | 210064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846871157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixed.2846871157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/15.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3905376765 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 412299656496 ps |
| CPU time | 1272.8 seconds |
| Started | Oct 12 01:29:34 AM UTC 24 |
| Finished | Oct 12 01:51:00 AM UTC 24 |
| Peak memory | 212772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905376765 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_wakeup_fixed.3905376765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/15.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_fsm_reset.2200529934 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 77827503249 ps |
| CPU time | 337.47 seconds |
| Started | Oct 12 01:30:06 AM UTC 24 |
| Finished | Oct 12 01:35:48 AM UTC 24 |
| Peak memory | 210420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200529934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.2200529934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/15.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_lowpower_counter.2524249568 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 37837820114 ps |
| CPU time | 37.9 seconds |
| Started | Oct 12 01:30:05 AM UTC 24 |
| Finished | Oct 12 01:30:45 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524249568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.2524249568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/15.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_poweron_counter.996220925 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 2981515670 ps |
| CPU time | 7.55 seconds |
| Started | Oct 12 01:29:56 AM UTC 24 |
| Finished | Oct 12 01:30:05 AM UTC 24 |
| Peak memory | 209996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996220925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.996220925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/15.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_smoke.2958579684 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 5879311769 ps |
| CPU time | 14.64 seconds |
| Started | Oct 12 01:29:18 AM UTC 24 |
| Finished | Oct 12 01:29:33 AM UTC 24 |
| Peak memory | 210252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958579684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.2958579684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/15.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all.1666023766 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 202349195911 ps |
| CPU time | 113.97 seconds |
| Started | Oct 12 01:30:12 AM UTC 24 |
| Finished | Oct 12 01:32:08 AM UTC 24 |
| Peak memory | 210128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666023766 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.1666023766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_alert_test.41338169 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 422035320 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 01:31:23 AM UTC 24 |
| Finished | Oct 12 01:31:25 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41338169 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.41338169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/16.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_clock_gating.1213180732 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 158414979527 ps |
| CPU time | 93.65 seconds |
| Started | Oct 12 01:30:57 AM UTC 24 |
| Finished | Oct 12 01:32:33 AM UTC 24 |
| Peak memory | 210244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213180732 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gating.1213180732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/16.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt_fixed.4091291340 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 327590702387 ps |
| CPU time | 764.28 seconds |
| Started | Oct 12 01:30:47 AM UTC 24 |
| Finished | Oct 12 01:43:39 AM UTC 24 |
| Peak memory | 210108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091291340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt_fixed.4091291340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/16.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled.831039643 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 324312470484 ps |
| CPU time | 236.19 seconds |
| Started | Oct 12 01:30:36 AM UTC 24 |
| Finished | Oct 12 01:34:35 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831039643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.831039643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/16.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled_fixed.1774833229 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 326990372503 ps |
| CPU time | 112.3 seconds |
| Started | Oct 12 01:30:40 AM UTC 24 |
| Finished | Oct 12 01:32:34 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774833229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixed.1774833229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/16.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup.3440863162 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 528055339568 ps |
| CPU time | 1281.14 seconds |
| Started | Oct 12 01:30:50 AM UTC 24 |
| Finished | Oct 12 01:52:24 AM UTC 24 |
| Peak memory | 213044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440863162 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_wakeup.3440863162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/16.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup_fixed.2187887404 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 201892844629 ps |
| CPU time | 134.86 seconds |
| Started | Oct 12 01:30:56 AM UTC 24 |
| Finished | Oct 12 01:33:13 AM UTC 24 |
| Peak memory | 210060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187887404 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_wakeup_fixed.2187887404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/16.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_fsm_reset.2902666334 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 128121910950 ps |
| CPU time | 758.4 seconds |
| Started | Oct 12 01:31:22 AM UTC 24 |
| Finished | Oct 12 01:44:07 AM UTC 24 |
| Peak memory | 210460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902666334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.2902666334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/16.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_lowpower_counter.2619350753 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 37291788535 ps |
| CPU time | 137.95 seconds |
| Started | Oct 12 01:31:09 AM UTC 24 |
| Finished | Oct 12 01:33:29 AM UTC 24 |
| Peak memory | 209984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619350753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2619350753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/16.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_poweron_counter.3905822228 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 3922831937 ps |
| CPU time | 13.07 seconds |
| Started | Oct 12 01:31:01 AM UTC 24 |
| Finished | Oct 12 01:31:16 AM UTC 24 |
| Peak memory | 210060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905822228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.3905822228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/16.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_smoke.1928218523 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 6042754482 ps |
| CPU time | 22.03 seconds |
| Started | Oct 12 01:30:23 AM UTC 24 |
| Finished | Oct 12 01:30:46 AM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928218523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1928218523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/16.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all.1153285281 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 52356145696 ps |
| CPU time | 157.59 seconds |
| Started | Oct 12 01:31:23 AM UTC 24 |
| Finished | Oct 12 01:34:03 AM UTC 24 |
| Peak memory | 210132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153285281 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.1153285281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/16.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.4069006573 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 7964748642 ps |
| CPU time | 13.7 seconds |
| Started | Oct 12 01:31:23 AM UTC 24 |
| Finished | Oct 12 01:31:38 AM UTC 24 |
| Peak memory | 210392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4069006573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 16.adc_ctrl_stress_all_with_rand_reset.4069006573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/16.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_alert_test.3498577623 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 530661103 ps |
| CPU time | 3.22 seconds |
| Started | Oct 12 01:32:34 AM UTC 24 |
| Finished | Oct 12 01:32:38 AM UTC 24 |
| Peak memory | 210048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498577623 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3498577623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/17.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_both.1370844705 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 214318860670 ps |
| CPU time | 335.21 seconds |
| Started | Oct 12 01:32:06 AM UTC 24 |
| Finished | Oct 12 01:37:45 AM UTC 24 |
| Peak memory | 210332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370844705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1370844705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/17.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1399019693 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 167977839408 ps |
| CPU time | 473.16 seconds |
| Started | Oct 12 01:31:38 AM UTC 24 |
| Finished | Oct 12 01:39:37 AM UTC 24 |
| Peak memory | 210116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399019693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt_fixed.1399019693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/17.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled.324488559 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 158656101808 ps |
| CPU time | 69.45 seconds |
| Started | Oct 12 01:31:27 AM UTC 24 |
| Finished | Oct 12 01:32:38 AM UTC 24 |
| Peak memory | 210132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324488559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.324488559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/17.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled_fixed.686169407 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 332945175800 ps |
| CPU time | 365.65 seconds |
| Started | Oct 12 01:31:35 AM UTC 24 |
| Finished | Oct 12 01:37:45 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686169407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixed.686169407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/17.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup.1173408755 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 463347014364 ps |
| CPU time | 787.99 seconds |
| Started | Oct 12 01:31:38 AM UTC 24 |
| Finished | Oct 12 01:44:54 AM UTC 24 |
| Peak memory | 210064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173408755 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_wakeup.1173408755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/17.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup_fixed.2139740379 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 617446572741 ps |
| CPU time | 1541.75 seconds |
| Started | Oct 12 01:31:45 AM UTC 24 |
| Finished | Oct 12 01:57:43 AM UTC 24 |
| Peak memory | 212704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139740379 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_wakeup_fixed.2139740379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/17.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_fsm_reset.1030159718 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 120791328431 ps |
| CPU time | 682.59 seconds |
| Started | Oct 12 01:32:23 AM UTC 24 |
| Finished | Oct 12 01:43:53 AM UTC 24 |
| Peak memory | 210676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030159718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.1030159718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/17.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_lowpower_counter.3589366814 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 27371283862 ps |
| CPU time | 38 seconds |
| Started | Oct 12 01:32:18 AM UTC 24 |
| Finished | Oct 12 01:32:57 AM UTC 24 |
| Peak memory | 209984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589366814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3589366814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/17.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_poweron_counter.2010568520 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 3431581863 ps |
| CPU time | 15.29 seconds |
| Started | Oct 12 01:32:09 AM UTC 24 |
| Finished | Oct 12 01:32:25 AM UTC 24 |
| Peak memory | 209984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010568520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.2010568520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/17.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_smoke.4196580649 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 5980474652 ps |
| CPU time | 11.9 seconds |
| Started | Oct 12 01:31:25 AM UTC 24 |
| Finished | Oct 12 01:31:38 AM UTC 24 |
| Peak memory | 209992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196580649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.4196580649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/17.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all.3800942763 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 522245778286 ps |
| CPU time | 1353.04 seconds |
| Started | Oct 12 01:32:26 AM UTC 24 |
| Finished | Oct 12 01:55:12 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800942763 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.3800942763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3915696294 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 3439758603 ps |
| CPU time | 14.21 seconds |
| Started | Oct 12 01:32:23 AM UTC 24 |
| Finished | Oct 12 01:32:38 AM UTC 24 |
| Peak memory | 221060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3915696294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 17.adc_ctrl_stress_all_with_rand_reset.3915696294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_alert_test.796952299 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 451822499 ps |
| CPU time | 2.82 seconds |
| Started | Oct 12 01:33:58 AM UTC 24 |
| Finished | Oct 12 01:34:02 AM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796952299 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.796952299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/18.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_clock_gating.3801515879 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 508098930125 ps |
| CPU time | 118.43 seconds |
| Started | Oct 12 01:33:14 AM UTC 24 |
| Finished | Oct 12 01:35:14 AM UTC 24 |
| Peak memory | 210060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801515879 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gating.3801515879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/18.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_both.3189463901 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 336447994906 ps |
| CPU time | 861.1 seconds |
| Started | Oct 12 01:33:19 AM UTC 24 |
| Finished | Oct 12 01:47:48 AM UTC 24 |
| Peak memory | 210116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189463901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.3189463901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/18.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt.2285060282 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 326119313999 ps |
| CPU time | 480.35 seconds |
| Started | Oct 12 01:32:39 AM UTC 24 |
| Finished | Oct 12 01:40:45 AM UTC 24 |
| Peak memory | 210080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285060282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.2285060282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/18.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt_fixed.3977266676 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 330492256932 ps |
| CPU time | 304.62 seconds |
| Started | Oct 12 01:32:39 AM UTC 24 |
| Finished | Oct 12 01:37:48 AM UTC 24 |
| Peak memory | 210128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977266676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt_fixed.3977266676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/18.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled.1313113860 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 331859072117 ps |
| CPU time | 238.91 seconds |
| Started | Oct 12 01:32:38 AM UTC 24 |
| Finished | Oct 12 01:36:40 AM UTC 24 |
| Peak memory | 210120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313113860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1313113860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/18.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled_fixed.1814676155 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 160821716444 ps |
| CPU time | 143.06 seconds |
| Started | Oct 12 01:32:39 AM UTC 24 |
| Finished | Oct 12 01:35:05 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814676155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixed.1814676155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/18.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_wakeup.2100943054 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 397437726478 ps |
| CPU time | 259.9 seconds |
| Started | Oct 12 01:32:43 AM UTC 24 |
| Finished | Oct 12 01:37:07 AM UTC 24 |
| Peak memory | 210072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100943054 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_wakeup.2100943054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/18.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_wakeup_fixed.3705944657 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 617362242614 ps |
| CPU time | 1660.3 seconds |
| Started | Oct 12 01:32:58 AM UTC 24 |
| Finished | Oct 12 02:00:54 AM UTC 24 |
| Peak memory | 212772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705944657 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_wakeup_fixed.3705944657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/18.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_fsm_reset.1756898959 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 116146265427 ps |
| CPU time | 515.21 seconds |
| Started | Oct 12 01:33:48 AM UTC 24 |
| Finished | Oct 12 01:42:28 AM UTC 24 |
| Peak memory | 210540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756898959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1756898959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/18.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_lowpower_counter.196860542 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 36544484946 ps |
| CPU time | 23.73 seconds |
| Started | Oct 12 01:33:32 AM UTC 24 |
| Finished | Oct 12 01:33:57 AM UTC 24 |
| Peak memory | 210252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196860542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.196860542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/18.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_poweron_counter.3601478717 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 3919628295 ps |
| CPU time | 15.89 seconds |
| Started | Oct 12 01:33:30 AM UTC 24 |
| Finished | Oct 12 01:33:47 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601478717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.3601478717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/18.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_smoke.3750464545 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 5925676720 ps |
| CPU time | 6.48 seconds |
| Started | Oct 12 01:32:35 AM UTC 24 |
| Finished | Oct 12 01:32:43 AM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750464545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.3750464545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/18.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all.2432441590 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 195240002125 ps |
| CPU time | 123.66 seconds |
| Started | Oct 12 01:33:53 AM UTC 24 |
| Finished | Oct 12 01:35:59 AM UTC 24 |
| Peak memory | 210128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432441590 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.2432441590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/18.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3023963792 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 2669138704 ps |
| CPU time | 28.41 seconds |
| Started | Oct 12 01:33:48 AM UTC 24 |
| Finished | Oct 12 01:34:18 AM UTC 24 |
| Peak memory | 220732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3023963792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 18.adc_ctrl_stress_all_with_rand_reset.3023963792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/18.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_alert_test.2832709298 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 469223899 ps |
| CPU time | 1.01 seconds |
| Started | Oct 12 01:35:29 AM UTC 24 |
| Finished | Oct 12 01:35:31 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832709298 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2832709298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/19.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_both.448514707 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 344399931393 ps |
| CPU time | 461.11 seconds |
| Started | Oct 12 01:35:05 AM UTC 24 |
| Finished | Oct 12 01:42:51 AM UTC 24 |
| Peak memory | 210324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448514707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.448514707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/19.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_interrupt.2946784556 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 327710177822 ps |
| CPU time | 270.29 seconds |
| Started | Oct 12 01:34:20 AM UTC 24 |
| Finished | Oct 12 01:38:54 AM UTC 24 |
| Peak memory | 210280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946784556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2946784556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/19.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_interrupt_fixed.610148691 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 331840858850 ps |
| CPU time | 687.21 seconds |
| Started | Oct 12 01:34:31 AM UTC 24 |
| Finished | Oct 12 01:46:05 AM UTC 24 |
| Peak memory | 210408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610148691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt_fixed.610148691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/19.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled_fixed.1941471652 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 166856454419 ps |
| CPU time | 399.32 seconds |
| Started | Oct 12 01:34:19 AM UTC 24 |
| Finished | Oct 12 01:41:02 AM UTC 24 |
| Peak memory | 210272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941471652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixed.1941471652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/19.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup.2233049009 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 187239724749 ps |
| CPU time | 74.68 seconds |
| Started | Oct 12 01:34:33 AM UTC 24 |
| Finished | Oct 12 01:35:49 AM UTC 24 |
| Peak memory | 210072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233049009 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_wakeup.2233049009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/19.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup_fixed.4225646981 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 393126470881 ps |
| CPU time | 164.87 seconds |
| Started | Oct 12 01:34:36 AM UTC 24 |
| Finished | Oct 12 01:37:24 AM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225646981 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_wakeup_fixed.4225646981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/19.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_fsm_reset.3673335583 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 140563781600 ps |
| CPU time | 630.28 seconds |
| Started | Oct 12 01:35:15 AM UTC 24 |
| Finished | Oct 12 01:45:51 AM UTC 24 |
| Peak memory | 210476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673335583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.3673335583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/19.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_lowpower_counter.116643972 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 44226464132 ps |
| CPU time | 15.22 seconds |
| Started | Oct 12 01:35:11 AM UTC 24 |
| Finished | Oct 12 01:35:28 AM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116643972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.116643972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/19.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_poweron_counter.2580365295 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 2865118970 ps |
| CPU time | 13.03 seconds |
| Started | Oct 12 01:35:07 AM UTC 24 |
| Finished | Oct 12 01:35:21 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580365295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.2580365295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/19.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_smoke.3639501811 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 5831584996 ps |
| CPU time | 14.34 seconds |
| Started | Oct 12 01:34:03 AM UTC 24 |
| Finished | Oct 12 01:34:19 AM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639501811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.3639501811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/19.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1886140076 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 4184681494 ps |
| CPU time | 11.9 seconds |
| Started | Oct 12 01:35:16 AM UTC 24 |
| Finished | Oct 12 01:35:29 AM UTC 24 |
| Peak memory | 220364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1886140076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 19.adc_ctrl_stress_all_with_rand_reset.1886140076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/19.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_alert_test.1522772736 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 341807009 ps |
| CPU time | 1.82 seconds |
| Started | Oct 12 01:14:19 AM UTC 24 |
| Finished | Oct 12 01:14:22 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522772736 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.1522772736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/2.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.1098708272 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 318717410042 ps |
| CPU time | 619.48 seconds |
| Started | Oct 12 01:14:10 AM UTC 24 |
| Finished | Oct 12 01:24:36 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098708272 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gating.1098708272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/2.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt.455423886 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 165258523098 ps |
| CPU time | 183.97 seconds |
| Started | Oct 12 01:14:07 AM UTC 24 |
| Finished | Oct 12 01:17:14 AM UTC 24 |
| Peak memory | 210140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455423886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.455423886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/2.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt_fixed.4175757853 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 492775233181 ps |
| CPU time | 1295.69 seconds |
| Started | Oct 12 01:14:07 AM UTC 24 |
| Finished | Oct 12 01:35:55 AM UTC 24 |
| Peak memory | 212784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175757853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt_fixed.4175757853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/2.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled.1683183566 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 166853922630 ps |
| CPU time | 232.42 seconds |
| Started | Oct 12 01:14:03 AM UTC 24 |
| Finished | Oct 12 01:17:59 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683183566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.1683183566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/2.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled_fixed.3316585293 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 165574167427 ps |
| CPU time | 647.88 seconds |
| Started | Oct 12 01:14:06 AM UTC 24 |
| Finished | Oct 12 01:25:02 AM UTC 24 |
| Peak memory | 210116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316585293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed.3316585293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/2.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup.4022563461 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 572337383884 ps |
| CPU time | 1457.12 seconds |
| Started | Oct 12 01:14:08 AM UTC 24 |
| Finished | Oct 12 01:38:40 AM UTC 24 |
| Peak memory | 212780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022563461 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_wakeup.4022563461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/2.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup_fixed.948737109 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 199658670457 ps |
| CPU time | 496.5 seconds |
| Started | Oct 12 01:14:10 AM UTC 24 |
| Finished | Oct 12 01:22:32 AM UTC 24 |
| Peak memory | 210452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948737109 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_wakeup_fixed.948737109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/2.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_lowpower_counter.3275743828 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 30658816148 ps |
| CPU time | 24.41 seconds |
| Started | Oct 12 01:14:16 AM UTC 24 |
| Finished | Oct 12 01:14:42 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275743828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.3275743828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/2.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_poweron_counter.2586001459 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3636206955 ps |
| CPU time | 2.95 seconds |
| Started | Oct 12 01:14:14 AM UTC 24 |
| Finished | Oct 12 01:14:18 AM UTC 24 |
| Peak memory | 210060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586001459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2586001459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/2.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_sec_cm.1380211785 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 4264345213 ps |
| CPU time | 17.63 seconds |
| Started | Oct 12 01:14:18 AM UTC 24 |
| Finished | Oct 12 01:14:37 AM UTC 24 |
| Peak memory | 242368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380211785 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.1380211785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/2.adc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_smoke.546876756 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5790999446 ps |
| CPU time | 10.54 seconds |
| Started | Oct 12 01:14:03 AM UTC 24 |
| Finished | Oct 12 01:14:15 AM UTC 24 |
| Peak memory | 209984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546876756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.546876756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/2.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_alert_test.2600948978 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 338341046 ps |
| CPU time | 2.19 seconds |
| Started | Oct 12 01:37:17 AM UTC 24 |
| Finished | Oct 12 01:37:20 AM UTC 24 |
| Peak memory | 210048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600948978 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.2600948978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/20.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_clock_gating.4099659240 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 322188203267 ps |
| CPU time | 392.87 seconds |
| Started | Oct 12 01:36:11 AM UTC 24 |
| Finished | Oct 12 01:42:48 AM UTC 24 |
| Peak memory | 210328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099659240 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gating.4099659240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/20.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_interrupt.3758589633 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 156347819764 ps |
| CPU time | 143.28 seconds |
| Started | Oct 12 01:35:50 AM UTC 24 |
| Finished | Oct 12 01:38:16 AM UTC 24 |
| Peak memory | 210072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758589633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.3758589633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/20.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_interrupt_fixed.1936578576 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 164353219516 ps |
| CPU time | 167.61 seconds |
| Started | Oct 12 01:35:56 AM UTC 24 |
| Finished | Oct 12 01:38:46 AM UTC 24 |
| Peak memory | 210108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936578576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt_fixed.1936578576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/20.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_polled.493175632 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 329138049350 ps |
| CPU time | 301.06 seconds |
| Started | Oct 12 01:35:32 AM UTC 24 |
| Finished | Oct 12 01:40:36 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493175632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.493175632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/20.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_polled_fixed.3446208715 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 489723059514 ps |
| CPU time | 913.99 seconds |
| Started | Oct 12 01:35:49 AM UTC 24 |
| Finished | Oct 12 01:51:12 AM UTC 24 |
| Peak memory | 212916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446208715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixed.3446208715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/20.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_wakeup.1077122687 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 573417860789 ps |
| CPU time | 602.07 seconds |
| Started | Oct 12 01:36:00 AM UTC 24 |
| Finished | Oct 12 01:46:09 AM UTC 24 |
| Peak memory | 210132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077122687 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_wakeup.1077122687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/20.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_wakeup_fixed.3956132082 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 198389810680 ps |
| CPU time | 541.41 seconds |
| Started | Oct 12 01:36:00 AM UTC 24 |
| Finished | Oct 12 01:45:07 AM UTC 24 |
| Peak memory | 210124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956132082 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_wakeup_fixed.3956132082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/20.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_lowpower_counter.3821704411 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 23744380966 ps |
| CPU time | 47.29 seconds |
| Started | Oct 12 01:36:49 AM UTC 24 |
| Finished | Oct 12 01:37:38 AM UTC 24 |
| Peak memory | 209984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821704411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.3821704411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/20.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_poweron_counter.1975184586 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 3073924231 ps |
| CPU time | 13.8 seconds |
| Started | Oct 12 01:36:41 AM UTC 24 |
| Finished | Oct 12 01:36:57 AM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975184586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1975184586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/20.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_smoke.3422364275 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 5605623097 ps |
| CPU time | 27.09 seconds |
| Started | Oct 12 01:35:31 AM UTC 24 |
| Finished | Oct 12 01:35:59 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422364275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3422364275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/20.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all.3898502400 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 172072130395 ps |
| CPU time | 110.46 seconds |
| Started | Oct 12 01:37:08 AM UTC 24 |
| Finished | Oct 12 01:39:00 AM UTC 24 |
| Peak memory | 210192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898502400 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.3898502400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/20.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.1527735678 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 2810606714 ps |
| CPU time | 10.88 seconds |
| Started | Oct 12 01:37:04 AM UTC 24 |
| Finished | Oct 12 01:37:16 AM UTC 24 |
| Peak memory | 220440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1527735678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 20.adc_ctrl_stress_all_with_rand_reset.1527735678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/20.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_alert_test.1310918886 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 517661767 ps |
| CPU time | 1.87 seconds |
| Started | Oct 12 01:38:47 AM UTC 24 |
| Finished | Oct 12 01:38:50 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310918886 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1310918886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/21.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_clock_gating.3395017121 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 208931959511 ps |
| CPU time | 84.12 seconds |
| Started | Oct 12 01:37:57 AM UTC 24 |
| Finished | Oct 12 01:39:24 AM UTC 24 |
| Peak memory | 210128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395017121 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gating.3395017121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/21.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_both.1423206728 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 333233217279 ps |
| CPU time | 257.6 seconds |
| Started | Oct 12 01:38:12 AM UTC 24 |
| Finished | Oct 12 01:42:33 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423206728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.1423206728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/21.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_interrupt.3289189286 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 165840947658 ps |
| CPU time | 512.91 seconds |
| Started | Oct 12 01:37:39 AM UTC 24 |
| Finished | Oct 12 01:46:18 AM UTC 24 |
| Peak memory | 210088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289189286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.3289189286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/21.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_interrupt_fixed.3349839683 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 162966855227 ps |
| CPU time | 432.95 seconds |
| Started | Oct 12 01:37:45 AM UTC 24 |
| Finished | Oct 12 01:45:03 AM UTC 24 |
| Peak memory | 210048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349839683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt_fixed.3349839683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/21.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_polled.724965603 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 488473463566 ps |
| CPU time | 1084.63 seconds |
| Started | Oct 12 01:37:25 AM UTC 24 |
| Finished | Oct 12 01:55:40 AM UTC 24 |
| Peak memory | 212788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724965603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.724965603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/21.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_polled_fixed.878170203 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 329760263894 ps |
| CPU time | 256.11 seconds |
| Started | Oct 12 01:37:30 AM UTC 24 |
| Finished | Oct 12 01:41:50 AM UTC 24 |
| Peak memory | 210128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878170203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fixed.878170203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/21.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_wakeup.3702600494 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 534180434878 ps |
| CPU time | 436.93 seconds |
| Started | Oct 12 01:37:45 AM UTC 24 |
| Finished | Oct 12 01:45:07 AM UTC 24 |
| Peak memory | 210068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702600494 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_wakeup.3702600494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/21.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_wakeup_fixed.4139442509 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 399876624206 ps |
| CPU time | 114.22 seconds |
| Started | Oct 12 01:37:48 AM UTC 24 |
| Finished | Oct 12 01:39:45 AM UTC 24 |
| Peak memory | 210060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139442509 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_wakeup_fixed.4139442509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/21.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_fsm_reset.2455384760 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 71954352092 ps |
| CPU time | 624.6 seconds |
| Started | Oct 12 01:38:26 AM UTC 24 |
| Finished | Oct 12 01:48:57 AM UTC 24 |
| Peak memory | 210400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455384760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.2455384760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/21.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_lowpower_counter.570300037 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 33248977719 ps |
| CPU time | 79.97 seconds |
| Started | Oct 12 01:38:24 AM UTC 24 |
| Finished | Oct 12 01:39:45 AM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570300037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.570300037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/21.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_poweron_counter.3322012744 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 3939553615 ps |
| CPU time | 4.89 seconds |
| Started | Oct 12 01:38:17 AM UTC 24 |
| Finished | Oct 12 01:38:23 AM UTC 24 |
| Peak memory | 209984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322012744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.3322012744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/21.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_smoke.2182975684 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 6168583929 ps |
| CPU time | 7.47 seconds |
| Started | Oct 12 01:37:21 AM UTC 24 |
| Finished | Oct 12 01:37:29 AM UTC 24 |
| Peak memory | 210060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182975684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2182975684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/21.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_stress_all.1961204851 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 300372060359 ps |
| CPU time | 1067.27 seconds |
| Started | Oct 12 01:38:43 AM UTC 24 |
| Finished | Oct 12 01:56:40 AM UTC 24 |
| Peak memory | 223304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961204851 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.1961204851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/21.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.996263573 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3377188689 ps |
| CPU time | 3.97 seconds |
| Started | Oct 12 01:38:41 AM UTC 24 |
| Finished | Oct 12 01:38:46 AM UTC 24 |
| Peak memory | 220840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=996263573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.996263573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/21.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_alert_test.3606012159 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 337380237 ps |
| CPU time | 2.17 seconds |
| Started | Oct 12 01:39:52 AM UTC 24 |
| Finished | Oct 12 01:39:55 AM UTC 24 |
| Peak memory | 210048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606012159 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3606012159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/22.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_both.2740451609 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 543162257366 ps |
| CPU time | 1445.61 seconds |
| Started | Oct 12 01:39:10 AM UTC 24 |
| Finished | Oct 12 02:03:29 AM UTC 24 |
| Peak memory | 212776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740451609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.2740451609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/22.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_interrupt_fixed.3063870813 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 326707230480 ps |
| CPU time | 246.51 seconds |
| Started | Oct 12 01:38:54 AM UTC 24 |
| Finished | Oct 12 01:43:04 AM UTC 24 |
| Peak memory | 210128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063870813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt_fixed.3063870813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/22.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_polled.3794292805 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 163995696865 ps |
| CPU time | 242.95 seconds |
| Started | Oct 12 01:38:49 AM UTC 24 |
| Finished | Oct 12 01:42:55 AM UTC 24 |
| Peak memory | 210140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794292805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.3794292805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/22.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_polled_fixed.3238027765 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 490736033441 ps |
| CPU time | 1197.03 seconds |
| Started | Oct 12 01:38:51 AM UTC 24 |
| Finished | Oct 12 01:59:00 AM UTC 24 |
| Peak memory | 212884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238027765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixed.3238027765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/22.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_wakeup.3422645491 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 175496764154 ps |
| CPU time | 300.14 seconds |
| Started | Oct 12 01:39:00 AM UTC 24 |
| Finished | Oct 12 01:44:04 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422645491 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_wakeup.3422645491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/22.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1390585911 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 203721073962 ps |
| CPU time | 210.12 seconds |
| Started | Oct 12 01:39:01 AM UTC 24 |
| Finished | Oct 12 01:42:35 AM UTC 24 |
| Peak memory | 210132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390585911 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_wakeup_fixed.1390585911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/22.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_fsm_reset.2377780244 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 73702977861 ps |
| CPU time | 551.31 seconds |
| Started | Oct 12 01:39:38 AM UTC 24 |
| Finished | Oct 12 01:48:55 AM UTC 24 |
| Peak memory | 210460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377780244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2377780244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/22.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_lowpower_counter.235772691 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 38283252373 ps |
| CPU time | 81.75 seconds |
| Started | Oct 12 01:39:33 AM UTC 24 |
| Finished | Oct 12 01:40:57 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235772691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.235772691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/22.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_poweron_counter.2108148443 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 4559207863 ps |
| CPU time | 6.03 seconds |
| Started | Oct 12 01:39:25 AM UTC 24 |
| Finished | Oct 12 01:39:32 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108148443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2108148443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/22.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_smoke.4192688760 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 5879894543 ps |
| CPU time | 4.49 seconds |
| Started | Oct 12 01:38:47 AM UTC 24 |
| Finished | Oct 12 01:38:53 AM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192688760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.4192688760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/22.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2509061760 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 10003521371 ps |
| CPU time | 19.36 seconds |
| Started | Oct 12 01:39:46 AM UTC 24 |
| Finished | Oct 12 01:40:07 AM UTC 24 |
| Peak memory | 220776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2509061760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 22.adc_ctrl_stress_all_with_rand_reset.2509061760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/22.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_alert_test.3863046427 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 361453814 ps |
| CPU time | 2.35 seconds |
| Started | Oct 12 01:41:54 AM UTC 24 |
| Finished | Oct 12 01:41:58 AM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863046427 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.3863046427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/23.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_both.4040375816 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 171547506421 ps |
| CPU time | 513.08 seconds |
| Started | Oct 12 01:41:03 AM UTC 24 |
| Finished | Oct 12 01:49:41 AM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040375816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.4040375816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/23.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_interrupt.1951333710 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 159654064956 ps |
| CPU time | 157.07 seconds |
| Started | Oct 12 01:40:17 AM UTC 24 |
| Finished | Oct 12 01:42:57 AM UTC 24 |
| Peak memory | 210084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951333710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.1951333710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/23.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2883629407 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 164654018324 ps |
| CPU time | 43.94 seconds |
| Started | Oct 12 01:40:22 AM UTC 24 |
| Finished | Oct 12 01:41:08 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883629407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt_fixed.2883629407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/23.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_polled.1014284904 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 165974688578 ps |
| CPU time | 223.11 seconds |
| Started | Oct 12 01:40:04 AM UTC 24 |
| Finished | Oct 12 01:43:50 AM UTC 24 |
| Peak memory | 210120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014284904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.1014284904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/23.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_polled_fixed.1302317442 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 161359732985 ps |
| CPU time | 367.51 seconds |
| Started | Oct 12 01:40:07 AM UTC 24 |
| Finished | Oct 12 01:46:19 AM UTC 24 |
| Peak memory | 210332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302317442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixed.1302317442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/23.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_wakeup.3925701531 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 171787781152 ps |
| CPU time | 483.29 seconds |
| Started | Oct 12 01:40:38 AM UTC 24 |
| Finished | Oct 12 01:48:46 AM UTC 24 |
| Peak memory | 210264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925701531 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_wakeup.3925701531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/23.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_filters_wakeup_fixed.226945702 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 421292072057 ps |
| CPU time | 1058.24 seconds |
| Started | Oct 12 01:40:46 AM UTC 24 |
| Finished | Oct 12 01:58:34 AM UTC 24 |
| Peak memory | 212704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226945702 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_wakeup_fixed.226945702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/23.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_lowpower_counter.511487992 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 25819146808 ps |
| CPU time | 27.71 seconds |
| Started | Oct 12 01:41:29 AM UTC 24 |
| Finished | Oct 12 01:41:58 AM UTC 24 |
| Peak memory | 209980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511487992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.511487992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/23.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_poweron_counter.832937102 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 4352773828 ps |
| CPU time | 17.63 seconds |
| Started | Oct 12 01:41:09 AM UTC 24 |
| Finished | Oct 12 01:41:28 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832937102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.832937102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/23.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_smoke.1850657043 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 5926442764 ps |
| CPU time | 6.72 seconds |
| Started | Oct 12 01:39:56 AM UTC 24 |
| Finished | Oct 12 01:40:04 AM UTC 24 |
| Peak memory | 209992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850657043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.1850657043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/23.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all.2302792478 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 1469520526831 ps |
| CPU time | 3270.19 seconds |
| Started | Oct 12 01:41:50 AM UTC 24 |
| Finished | Oct 12 02:36:51 AM UTC 24 |
| Peak memory | 225612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302792478 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.2302792478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/23.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.2772640264 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 6125474243 ps |
| CPU time | 13.31 seconds |
| Started | Oct 12 01:41:39 AM UTC 24 |
| Finished | Oct 12 01:41:54 AM UTC 24 |
| Peak memory | 210252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2772640264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 23.adc_ctrl_stress_all_with_rand_reset.2772640264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/23.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_alert_test.2036593512 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 441413755 ps |
| CPU time | 1.28 seconds |
| Started | Oct 12 01:43:05 AM UTC 24 |
| Finished | Oct 12 01:43:08 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036593512 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.2036593512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/24.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_clock_gating.1841605833 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 283032332956 ps |
| CPU time | 31.67 seconds |
| Started | Oct 12 01:42:49 AM UTC 24 |
| Finished | Oct 12 01:43:22 AM UTC 24 |
| Peak memory | 210064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841605833 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gating.1841605833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/24.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_both.1228194323 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 340044015508 ps |
| CPU time | 249.69 seconds |
| Started | Oct 12 01:42:49 AM UTC 24 |
| Finished | Oct 12 01:47:02 AM UTC 24 |
| Peak memory | 210108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228194323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1228194323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/24.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_interrupt.2553370179 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 154723027714 ps |
| CPU time | 114.51 seconds |
| Started | Oct 12 01:42:11 AM UTC 24 |
| Finished | Oct 12 01:44:07 AM UTC 24 |
| Peak memory | 210140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553370179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2553370179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/24.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_interrupt_fixed.1157445395 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 159250973672 ps |
| CPU time | 251.69 seconds |
| Started | Oct 12 01:42:29 AM UTC 24 |
| Finished | Oct 12 01:46:44 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157445395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt_fixed.1157445395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/24.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_polled.47125667 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 165899662585 ps |
| CPU time | 112.52 seconds |
| Started | Oct 12 01:42:00 AM UTC 24 |
| Finished | Oct 12 01:43:54 AM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47125667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_ SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.47125667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/24.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_polled_fixed.2010739725 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 162446960146 ps |
| CPU time | 166.61 seconds |
| Started | Oct 12 01:42:05 AM UTC 24 |
| Finished | Oct 12 01:44:54 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010739725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixed.2010739725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/24.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_filters_wakeup_fixed.1589064306 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 394432296980 ps |
| CPU time | 1000.2 seconds |
| Started | Oct 12 01:42:35 AM UTC 24 |
| Finished | Oct 12 01:59:24 AM UTC 24 |
| Peak memory | 212704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589064306 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_wakeup_fixed.1589064306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/24.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_fsm_reset.3627472821 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 99428297829 ps |
| CPU time | 612.77 seconds |
| Started | Oct 12 01:42:58 AM UTC 24 |
| Finished | Oct 12 01:53:17 AM UTC 24 |
| Peak memory | 210460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627472821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.3627472821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/24.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_lowpower_counter.1002309323 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 24966435922 ps |
| CPU time | 84.5 seconds |
| Started | Oct 12 01:42:56 AM UTC 24 |
| Finished | Oct 12 01:44:23 AM UTC 24 |
| Peak memory | 209984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002309323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1002309323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/24.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_poweron_counter.2580210986 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 4333709642 ps |
| CPU time | 3.87 seconds |
| Started | Oct 12 01:42:52 AM UTC 24 |
| Finished | Oct 12 01:42:57 AM UTC 24 |
| Peak memory | 209984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580210986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2580210986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/24.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_smoke.1910982243 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 5979504165 ps |
| CPU time | 3.87 seconds |
| Started | Oct 12 01:41:58 AM UTC 24 |
| Finished | Oct 12 01:42:03 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910982243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.1910982243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/24.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.507680692 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 4214763812 ps |
| CPU time | 23.21 seconds |
| Started | Oct 12 01:42:58 AM UTC 24 |
| Finished | Oct 12 01:43:23 AM UTC 24 |
| Peak memory | 220992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=507680692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.507680692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/24.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_alert_test.3359117036 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 491016465 ps |
| CPU time | 1.84 seconds |
| Started | Oct 12 01:44:10 AM UTC 24 |
| Finished | Oct 12 01:44:12 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359117036 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.3359117036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/25.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_clock_gating.472716172 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 162885516867 ps |
| CPU time | 203.49 seconds |
| Started | Oct 12 01:43:44 AM UTC 24 |
| Finished | Oct 12 01:47:10 AM UTC 24 |
| Peak memory | 210336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472716172 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gating.472716172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/25.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_both.1283710185 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 193336580077 ps |
| CPU time | 327.19 seconds |
| Started | Oct 12 01:43:51 AM UTC 24 |
| Finished | Oct 12 01:49:22 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283710185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.1283710185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/25.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_interrupt.2411860726 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 330948955742 ps |
| CPU time | 1216.22 seconds |
| Started | Oct 12 01:43:28 AM UTC 24 |
| Finished | Oct 12 02:03:56 AM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411860726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2411860726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/25.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3834540113 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 163650198491 ps |
| CPU time | 401.39 seconds |
| Started | Oct 12 01:43:36 AM UTC 24 |
| Finished | Oct 12 01:50:22 AM UTC 24 |
| Peak memory | 210120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834540113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt_fixed.3834540113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/25.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_polled_fixed.1420317075 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 160116567958 ps |
| CPU time | 206.39 seconds |
| Started | Oct 12 01:43:24 AM UTC 24 |
| Finished | Oct 12 01:46:53 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420317075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixed.1420317075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/25.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_wakeup.1795737153 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 175975399191 ps |
| CPU time | 92.69 seconds |
| Started | Oct 12 01:43:40 AM UTC 24 |
| Finished | Oct 12 01:45:14 AM UTC 24 |
| Peak memory | 210396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795737153 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_wakeup.1795737153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/25.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_filters_wakeup_fixed.3401009275 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 597932485314 ps |
| CPU time | 468.19 seconds |
| Started | Oct 12 01:43:43 AM UTC 24 |
| Finished | Oct 12 01:51:36 AM UTC 24 |
| Peak memory | 210252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401009275 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_wakeup_fixed.3401009275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/25.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_fsm_reset.1831002387 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 73676329117 ps |
| CPU time | 623.66 seconds |
| Started | Oct 12 01:44:05 AM UTC 24 |
| Finished | Oct 12 01:54:35 AM UTC 24 |
| Peak memory | 210488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831002387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1831002387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/25.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_lowpower_counter.348506679 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 29592223262 ps |
| CPU time | 36.18 seconds |
| Started | Oct 12 01:43:55 AM UTC 24 |
| Finished | Oct 12 01:44:33 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348506679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.348506679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/25.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_poweron_counter.2482202770 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 4146623454 ps |
| CPU time | 14.4 seconds |
| Started | Oct 12 01:43:53 AM UTC 24 |
| Finished | Oct 12 01:44:09 AM UTC 24 |
| Peak memory | 210120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482202770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.2482202770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/25.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_smoke.3154043240 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 5965519124 ps |
| CPU time | 24.96 seconds |
| Started | Oct 12 01:43:09 AM UTC 24 |
| Finished | Oct 12 01:43:35 AM UTC 24 |
| Peak memory | 210060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154043240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3154043240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/25.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_stress_all.453318153 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 309525829236 ps |
| CPU time | 1112.85 seconds |
| Started | Oct 12 01:44:09 AM UTC 24 |
| Finished | Oct 12 02:02:53 AM UTC 24 |
| Peak memory | 223564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453318153 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.453318153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/25.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2801573917 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 44577262024 ps |
| CPU time | 114.01 seconds |
| Started | Oct 12 01:44:07 AM UTC 24 |
| Finished | Oct 12 01:46:04 AM UTC 24 |
| Peak memory | 220696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2801573917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 25.adc_ctrl_stress_all_with_rand_reset.2801573917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/25.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_alert_test.758917740 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 386310731 ps |
| CPU time | 2.46 seconds |
| Started | Oct 12 01:45:43 AM UTC 24 |
| Finished | Oct 12 01:45:46 AM UTC 24 |
| Peak memory | 210060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758917740 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.758917740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/26.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_both.1555585894 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 162151722673 ps |
| CPU time | 384.18 seconds |
| Started | Oct 12 01:45:08 AM UTC 24 |
| Finished | Oct 12 01:51:37 AM UTC 24 |
| Peak memory | 210140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555585894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.1555585894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/26.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_interrupt.2920046429 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 496731732468 ps |
| CPU time | 111.02 seconds |
| Started | Oct 12 01:44:39 AM UTC 24 |
| Finished | Oct 12 01:46:32 AM UTC 24 |
| Peak memory | 210280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920046429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2920046429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/26.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3574273666 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 334498386676 ps |
| CPU time | 304.21 seconds |
| Started | Oct 12 01:44:55 AM UTC 24 |
| Finished | Oct 12 01:50:03 AM UTC 24 |
| Peak memory | 210376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574273666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt_fixed.3574273666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/26.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_polled.4255302636 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 326389752742 ps |
| CPU time | 115.38 seconds |
| Started | Oct 12 01:44:24 AM UTC 24 |
| Finished | Oct 12 01:46:21 AM UTC 24 |
| Peak memory | 210348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255302636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.4255302636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/26.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_polled_fixed.2036641655 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 163589212135 ps |
| CPU time | 477.28 seconds |
| Started | Oct 12 01:44:34 AM UTC 24 |
| Finished | Oct 12 01:52:37 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036641655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fixed.2036641655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/26.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_wakeup_fixed.4221739320 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 204936073875 ps |
| CPU time | 587.86 seconds |
| Started | Oct 12 01:45:02 AM UTC 24 |
| Finished | Oct 12 01:54:56 AM UTC 24 |
| Peak memory | 210448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221739320 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_wakeup_fixed.4221739320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/26.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_fsm_reset.3578845341 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 90823509638 ps |
| CPU time | 596.91 seconds |
| Started | Oct 12 01:45:16 AM UTC 24 |
| Finished | Oct 12 01:55:19 AM UTC 24 |
| Peak memory | 210608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578845341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.3578845341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/26.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_lowpower_counter.2574359921 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 28492157165 ps |
| CPU time | 26.14 seconds |
| Started | Oct 12 01:45:15 AM UTC 24 |
| Finished | Oct 12 01:45:43 AM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574359921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2574359921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/26.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_poweron_counter.641492983 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 3912408599 ps |
| CPU time | 4.78 seconds |
| Started | Oct 12 01:45:08 AM UTC 24 |
| Finished | Oct 12 01:45:14 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641492983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.641492983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/26.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_smoke.1334023869 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 5726653973 ps |
| CPU time | 22.81 seconds |
| Started | Oct 12 01:44:14 AM UTC 24 |
| Finished | Oct 12 01:44:38 AM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334023869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.1334023869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/26.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_stress_all.2383465807 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 634433342814 ps |
| CPU time | 1484.69 seconds |
| Started | Oct 12 01:45:29 AM UTC 24 |
| Finished | Oct 12 02:10:28 AM UTC 24 |
| Peak memory | 212720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383465807 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.2383465807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/26.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_alert_test.2010449438 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 357282774 ps |
| CPU time | 2.22 seconds |
| Started | Oct 12 01:46:54 AM UTC 24 |
| Finished | Oct 12 01:46:57 AM UTC 24 |
| Peak memory | 209920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010449438 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.2010449438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/27.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_clock_gating.407419231 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 353118498338 ps |
| CPU time | 945.76 seconds |
| Started | Oct 12 01:46:09 AM UTC 24 |
| Finished | Oct 12 02:02:05 AM UTC 24 |
| Peak memory | 212868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407419231 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gating.407419231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/27.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_both.2074385803 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 154013370793 ps |
| CPU time | 186.38 seconds |
| Started | Oct 12 01:46:18 AM UTC 24 |
| Finished | Oct 12 01:49:28 AM UTC 24 |
| Peak memory | 210396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074385803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.2074385803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/27.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_interrupt.2283998389 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 336969466776 ps |
| CPU time | 209.76 seconds |
| Started | Oct 12 01:45:52 AM UTC 24 |
| Finished | Oct 12 01:49:25 AM UTC 24 |
| Peak memory | 210280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283998389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2283998389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/27.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_interrupt_fixed.339665287 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 341786428834 ps |
| CPU time | 89.34 seconds |
| Started | Oct 12 01:45:57 AM UTC 24 |
| Finished | Oct 12 01:47:29 AM UTC 24 |
| Peak memory | 210016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339665287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt_fixed.339665287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/27.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_polled.3882203728 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 330239862795 ps |
| CPU time | 1028.59 seconds |
| Started | Oct 12 01:45:47 AM UTC 24 |
| Finished | Oct 12 02:03:06 AM UTC 24 |
| Peak memory | 212716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882203728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.3882203728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/27.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_polled_fixed.2083162018 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 161417736195 ps |
| CPU time | 362.91 seconds |
| Started | Oct 12 01:45:51 AM UTC 24 |
| Finished | Oct 12 01:51:58 AM UTC 24 |
| Peak memory | 210048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083162018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixed.2083162018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/27.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_wakeup.1146770028 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 578402678888 ps |
| CPU time | 850.45 seconds |
| Started | Oct 12 01:46:04 AM UTC 24 |
| Finished | Oct 12 02:00:23 AM UTC 24 |
| Peak memory | 210192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146770028 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_wakeup.1146770028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/27.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_filters_wakeup_fixed.1050878609 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 198425493709 ps |
| CPU time | 571.35 seconds |
| Started | Oct 12 01:46:06 AM UTC 24 |
| Finished | Oct 12 01:55:44 AM UTC 24 |
| Peak memory | 210132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050878609 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_wakeup_fixed.1050878609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/27.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_fsm_reset.383137454 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 116990172527 ps |
| CPU time | 676.75 seconds |
| Started | Oct 12 01:46:33 AM UTC 24 |
| Finished | Oct 12 01:57:56 AM UTC 24 |
| Peak memory | 210404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383137454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.383137454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/27.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_lowpower_counter.53186587 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 27308026927 ps |
| CPU time | 29.92 seconds |
| Started | Oct 12 01:46:23 AM UTC 24 |
| Finished | Oct 12 01:46:55 AM UTC 24 |
| Peak memory | 210252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53186587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_ SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.53186587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/27.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_poweron_counter.2738622638 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 3438952380 ps |
| CPU time | 15.51 seconds |
| Started | Oct 12 01:46:21 AM UTC 24 |
| Finished | Oct 12 01:46:37 AM UTC 24 |
| Peak memory | 209984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738622638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2738622638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/27.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_smoke.2988544649 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 6126010835 ps |
| CPU time | 5.29 seconds |
| Started | Oct 12 01:45:44 AM UTC 24 |
| Finished | Oct 12 01:45:50 AM UTC 24 |
| Peak memory | 210316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988544649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.2988544649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/27.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_stress_all.3376654114 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 562644774055 ps |
| CPU time | 502.07 seconds |
| Started | Oct 12 01:46:45 AM UTC 24 |
| Finished | Oct 12 01:55:13 AM UTC 24 |
| Peak memory | 210060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376654114 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all.3376654114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/27.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3453870115 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 10132841850 ps |
| CPU time | 15.68 seconds |
| Started | Oct 12 01:46:38 AM UTC 24 |
| Finished | Oct 12 01:46:55 AM UTC 24 |
| Peak memory | 220444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3453870115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 27.adc_ctrl_stress_all_with_rand_reset.3453870115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/27.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_alert_test.1176522147 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 440882182 ps |
| CPU time | 1.02 seconds |
| Started | Oct 12 01:48:49 AM UTC 24 |
| Finished | Oct 12 01:48:51 AM UTC 24 |
| Peak memory | 208944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176522147 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.1176522147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/28.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_clock_gating.2895820623 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 503333938879 ps |
| CPU time | 241.19 seconds |
| Started | Oct 12 01:47:29 AM UTC 24 |
| Finished | Oct 12 01:51:34 AM UTC 24 |
| Peak memory | 210068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895820623 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gating.2895820623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/28.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_both.1642731362 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 325343434540 ps |
| CPU time | 465.42 seconds |
| Started | Oct 12 01:47:37 AM UTC 24 |
| Finished | Oct 12 01:55:27 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642731362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.1642731362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/28.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_interrupt.1667133034 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 325027426642 ps |
| CPU time | 290.8 seconds |
| Started | Oct 12 01:47:03 AM UTC 24 |
| Finished | Oct 12 01:51:58 AM UTC 24 |
| Peak memory | 210076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667133034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.1667133034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/28.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1895616740 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 499039870385 ps |
| CPU time | 1579.35 seconds |
| Started | Oct 12 01:47:04 AM UTC 24 |
| Finished | Oct 12 02:13:39 AM UTC 24 |
| Peak memory | 212704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895616740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt_fixed.1895616740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/28.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_polled.989155246 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 326847535864 ps |
| CPU time | 489.09 seconds |
| Started | Oct 12 01:46:56 AM UTC 24 |
| Finished | Oct 12 01:55:11 AM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989155246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.989155246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/28.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_polled_fixed.1528584097 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 169962465338 ps |
| CPU time | 117.76 seconds |
| Started | Oct 12 01:46:58 AM UTC 24 |
| Finished | Oct 12 01:48:58 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528584097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixed.1528584097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/28.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_wakeup.773080974 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 339050037266 ps |
| CPU time | 446.64 seconds |
| Started | Oct 12 01:47:11 AM UTC 24 |
| Finished | Oct 12 01:54:43 AM UTC 24 |
| Peak memory | 210260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773080974 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_wakeup.773080974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/28.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1151496359 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 205989756075 ps |
| CPU time | 273.18 seconds |
| Started | Oct 12 01:47:11 AM UTC 24 |
| Finished | Oct 12 01:51:48 AM UTC 24 |
| Peak memory | 210260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151496359 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_wakeup_fixed.1151496359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/28.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_fsm_reset.3024787482 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 81210919221 ps |
| CPU time | 594.25 seconds |
| Started | Oct 12 01:48:29 AM UTC 24 |
| Finished | Oct 12 01:58:29 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024787482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3024787482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/28.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_lowpower_counter.152282717 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 41387911532 ps |
| CPU time | 84.48 seconds |
| Started | Oct 12 01:47:54 AM UTC 24 |
| Finished | Oct 12 01:49:20 AM UTC 24 |
| Peak memory | 209984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152282717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.152282717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/28.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_poweron_counter.3502741540 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 3691008103 ps |
| CPU time | 3.34 seconds |
| Started | Oct 12 01:47:49 AM UTC 24 |
| Finished | Oct 12 01:47:53 AM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502741540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.3502741540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/28.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_smoke.1944517215 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 5917696499 ps |
| CPU time | 6.57 seconds |
| Started | Oct 12 01:46:56 AM UTC 24 |
| Finished | Oct 12 01:47:04 AM UTC 24 |
| Peak memory | 209960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944517215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1944517215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/28.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_stress_all.264095551 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 669483386312 ps |
| CPU time | 1649.15 seconds |
| Started | Oct 12 01:48:47 AM UTC 24 |
| Finished | Oct 12 02:16:32 AM UTC 24 |
| Peak memory | 212712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264095551 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.264095551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/28.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_alert_test.1028065549 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 507329187 ps |
| CPU time | 1.41 seconds |
| Started | Oct 12 01:50:06 AM UTC 24 |
| Finished | Oct 12 01:50:09 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028065549 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.1028065549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/29.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_clock_gating.2985840978 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 191756338580 ps |
| CPU time | 370.72 seconds |
| Started | Oct 12 01:49:23 AM UTC 24 |
| Finished | Oct 12 01:55:38 AM UTC 24 |
| Peak memory | 210128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985840978 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gating.2985840978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/29.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_interrupt_fixed.843486518 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 482105923889 ps |
| CPU time | 314.66 seconds |
| Started | Oct 12 01:48:58 AM UTC 24 |
| Finished | Oct 12 01:54:17 AM UTC 24 |
| Peak memory | 210116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843486518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt_fixed.843486518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/29.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_polled.1687838782 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 167698741892 ps |
| CPU time | 109.31 seconds |
| Started | Oct 12 01:48:53 AM UTC 24 |
| Finished | Oct 12 01:50:45 AM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687838782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1687838782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/29.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_polled_fixed.4170111706 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 162662585046 ps |
| CPU time | 407.98 seconds |
| Started | Oct 12 01:48:56 AM UTC 24 |
| Finished | Oct 12 01:55:49 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170111706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixed.4170111706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/29.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_wakeup.1162333406 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 183204268297 ps |
| CPU time | 704.21 seconds |
| Started | Oct 12 01:49:11 AM UTC 24 |
| Finished | Oct 12 02:01:02 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162333406 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_wakeup.1162333406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/29.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_filters_wakeup_fixed.4129579925 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 198274243359 ps |
| CPU time | 221.58 seconds |
| Started | Oct 12 01:49:21 AM UTC 24 |
| Finished | Oct 12 01:53:05 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129579925 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_wakeup_fixed.4129579925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/29.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_fsm_reset.2522732750 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 122059267762 ps |
| CPU time | 731 seconds |
| Started | Oct 12 01:49:42 AM UTC 24 |
| Finished | Oct 12 02:02:00 AM UTC 24 |
| Peak memory | 210608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522732750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.2522732750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/29.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_lowpower_counter.533631155 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 39196443046 ps |
| CPU time | 35.3 seconds |
| Started | Oct 12 01:49:29 AM UTC 24 |
| Finished | Oct 12 01:50:06 AM UTC 24 |
| Peak memory | 210184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533631155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.533631155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/29.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_poweron_counter.2391493579 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 4985853369 ps |
| CPU time | 20.79 seconds |
| Started | Oct 12 01:49:26 AM UTC 24 |
| Finished | Oct 12 01:49:48 AM UTC 24 |
| Peak memory | 209808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391493579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.2391493579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/29.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_smoke.1435013015 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 5948781617 ps |
| CPU time | 16.45 seconds |
| Started | Oct 12 01:48:52 AM UTC 24 |
| Finished | Oct 12 01:49:10 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435013015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1435013015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/29.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all.3737625497 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 343182549295 ps |
| CPU time | 373.09 seconds |
| Started | Oct 12 01:50:04 AM UTC 24 |
| Finished | Oct 12 01:56:22 AM UTC 24 |
| Peak memory | 210392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737625497 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.3737625497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/29.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.2021550149 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 15730341829 ps |
| CPU time | 18.98 seconds |
| Started | Oct 12 01:49:49 AM UTC 24 |
| Finished | Oct 12 01:50:09 AM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2021550149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 29.adc_ctrl_stress_all_with_rand_reset.2021550149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/29.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_alert_test.2889898042 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 354937799 ps |
| CPU time | 2.27 seconds |
| Started | Oct 12 01:14:42 AM UTC 24 |
| Finished | Oct 12 01:14:46 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889898042 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2889898042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/3.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_clock_gating.3975531642 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 345161949640 ps |
| CPU time | 1030.71 seconds |
| Started | Oct 12 01:14:31 AM UTC 24 |
| Finished | Oct 12 01:31:52 AM UTC 24 |
| Peak memory | 212784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975531642 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gating.3975531642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/3.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt_fixed.501992862 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 163369258572 ps |
| CPU time | 391.54 seconds |
| Started | Oct 12 01:14:26 AM UTC 24 |
| Finished | Oct 12 01:21:02 AM UTC 24 |
| Peak memory | 210124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501992862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt_fixed.501992862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/3.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled.2203081930 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 167470051292 ps |
| CPU time | 482.71 seconds |
| Started | Oct 12 01:14:23 AM UTC 24 |
| Finished | Oct 12 01:22:31 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203081930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.2203081930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/3.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled_fixed.2703658489 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 324974143836 ps |
| CPU time | 52.11 seconds |
| Started | Oct 12 01:14:25 AM UTC 24 |
| Finished | Oct 12 01:15:18 AM UTC 24 |
| Peak memory | 210068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703658489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed.2703658489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/3.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup.2618650104 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 384222928966 ps |
| CPU time | 1062.79 seconds |
| Started | Oct 12 01:14:28 AM UTC 24 |
| Finished | Oct 12 01:32:22 AM UTC 24 |
| Peak memory | 212792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618650104 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_wakeup.2618650104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/3.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1718557747 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 414165993930 ps |
| CPU time | 496.5 seconds |
| Started | Oct 12 01:14:29 AM UTC 24 |
| Finished | Oct 12 01:22:52 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718557747 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_wakeup_fixed.1718557747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/3.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.1089769076 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 101875131632 ps |
| CPU time | 663.51 seconds |
| Started | Oct 12 01:14:39 AM UTC 24 |
| Finished | Oct 12 01:25:50 AM UTC 24 |
| Peak memory | 210612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089769076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1089769076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/3.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_lowpower_counter.2735061687 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 41964464315 ps |
| CPU time | 42.71 seconds |
| Started | Oct 12 01:14:38 AM UTC 24 |
| Finished | Oct 12 01:15:22 AM UTC 24 |
| Peak memory | 209984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735061687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2735061687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/3.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_poweron_counter.2713001562 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 4712022051 ps |
| CPU time | 5.9 seconds |
| Started | Oct 12 01:14:38 AM UTC 24 |
| Finished | Oct 12 01:14:45 AM UTC 24 |
| Peak memory | 210192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713001562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.2713001562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/3.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_sec_cm.3205983889 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 7348606136 ps |
| CPU time | 34.16 seconds |
| Started | Oct 12 01:14:42 AM UTC 24 |
| Finished | Oct 12 01:15:18 AM UTC 24 |
| Peak memory | 242504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205983889 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3205983889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/3.adc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_smoke.2984801301 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 5747623097 ps |
| CPU time | 15.93 seconds |
| Started | Oct 12 01:14:23 AM UTC 24 |
| Finished | Oct 12 01:14:40 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984801301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.2984801301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/3.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all.172616466 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 452532817512 ps |
| CPU time | 578.96 seconds |
| Started | Oct 12 01:14:41 AM UTC 24 |
| Finished | Oct 12 01:24:25 AM UTC 24 |
| Peak memory | 210396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172616466 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.172616466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2826270047 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 97031353944 ps |
| CPU time | 13.12 seconds |
| Started | Oct 12 01:14:40 AM UTC 24 |
| Finished | Oct 12 01:14:54 AM UTC 24 |
| Peak memory | 220784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2826270047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 3.adc_ctrl_stress_all_with_rand_reset.2826270047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_alert_test.2367631731 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 502371477 ps |
| CPU time | 1.37 seconds |
| Started | Oct 12 01:52:16 AM UTC 24 |
| Finished | Oct 12 01:52:18 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367631731 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2367631731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/30.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_both.1432652365 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 179101694902 ps |
| CPU time | 115.31 seconds |
| Started | Oct 12 01:51:37 AM UTC 24 |
| Finished | Oct 12 01:53:35 AM UTC 24 |
| Peak memory | 210332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432652365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1432652365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/30.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_interrupt.3639444593 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 166612873364 ps |
| CPU time | 145.31 seconds |
| Started | Oct 12 01:50:23 AM UTC 24 |
| Finished | Oct 12 01:52:50 AM UTC 24 |
| Peak memory | 210352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639444593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.3639444593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/30.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_interrupt_fixed.924929796 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 327325412492 ps |
| CPU time | 151.12 seconds |
| Started | Oct 12 01:50:46 AM UTC 24 |
| Finished | Oct 12 01:53:19 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924929796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt_fixed.924929796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/30.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_polled.3468695229 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 489702804397 ps |
| CPU time | 302.79 seconds |
| Started | Oct 12 01:50:10 AM UTC 24 |
| Finished | Oct 12 01:55:17 AM UTC 24 |
| Peak memory | 210336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468695229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.3468695229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/30.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_polled_fixed.3140720832 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 494726128847 ps |
| CPU time | 180.74 seconds |
| Started | Oct 12 01:50:14 AM UTC 24 |
| Finished | Oct 12 01:53:17 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140720832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixed.3140720832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/30.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_wakeup.3331918677 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 370505165844 ps |
| CPU time | 914.61 seconds |
| Started | Oct 12 01:51:01 AM UTC 24 |
| Finished | Oct 12 02:06:25 AM UTC 24 |
| Peak memory | 212732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331918677 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_wakeup.3331918677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/30.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_wakeup_fixed.145175453 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 606426352217 ps |
| CPU time | 789.68 seconds |
| Started | Oct 12 01:51:13 AM UTC 24 |
| Finished | Oct 12 02:04:31 AM UTC 24 |
| Peak memory | 210060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145175453 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_wakeup_fixed.145175453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/30.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_fsm_reset.3351414873 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 107101579001 ps |
| CPU time | 463.57 seconds |
| Started | Oct 12 01:51:49 AM UTC 24 |
| Finished | Oct 12 01:59:37 AM UTC 24 |
| Peak memory | 210480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351414873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.3351414873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/30.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_lowpower_counter.2463809748 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 32514516636 ps |
| CPU time | 60.8 seconds |
| Started | Oct 12 01:51:47 AM UTC 24 |
| Finished | Oct 12 01:52:50 AM UTC 24 |
| Peak memory | 209984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463809748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2463809748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/30.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_poweron_counter.1179521549 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 3439986317 ps |
| CPU time | 7.94 seconds |
| Started | Oct 12 01:51:37 AM UTC 24 |
| Finished | Oct 12 01:51:46 AM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179521549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.1179521549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/30.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_smoke.3822698765 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 5834841405 ps |
| CPU time | 2.34 seconds |
| Started | Oct 12 01:50:09 AM UTC 24 |
| Finished | Oct 12 01:50:13 AM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822698765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.3822698765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/30.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_stress_all.245400671 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 521313478581 ps |
| CPU time | 678.09 seconds |
| Started | Oct 12 01:52:00 AM UTC 24 |
| Finished | Oct 12 02:03:25 AM UTC 24 |
| Peak memory | 210104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245400671 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all.245400671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/30.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_alert_test.3843054481 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 462900447 ps |
| CPU time | 1.3 seconds |
| Started | Oct 12 01:53:36 AM UTC 24 |
| Finished | Oct 12 01:53:38 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843054481 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3843054481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/31.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_both.3118445616 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 492347282792 ps |
| CPU time | 306.95 seconds |
| Started | Oct 12 01:52:59 AM UTC 24 |
| Finished | Oct 12 01:58:09 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118445616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.3118445616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/31.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_interrupt_fixed.1144607509 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 165572503433 ps |
| CPU time | 436.11 seconds |
| Started | Oct 12 01:52:37 AM UTC 24 |
| Finished | Oct 12 01:59:58 AM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144607509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt_fixed.1144607509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/31.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_polled.2728799649 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 327083128114 ps |
| CPU time | 151.76 seconds |
| Started | Oct 12 01:52:20 AM UTC 24 |
| Finished | Oct 12 01:54:54 AM UTC 24 |
| Peak memory | 210064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728799649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2728799649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/31.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_polled_fixed.3525790813 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 493965246231 ps |
| CPU time | 665.83 seconds |
| Started | Oct 12 01:52:25 AM UTC 24 |
| Finished | Oct 12 02:03:38 AM UTC 24 |
| Peak memory | 210264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525790813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixed.3525790813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/31.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_wakeup.3167007886 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 163891416620 ps |
| CPU time | 147.56 seconds |
| Started | Oct 12 01:52:42 AM UTC 24 |
| Finished | Oct 12 01:55:12 AM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167007886 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_wakeup.3167007886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/31.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1765320675 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 398206457446 ps |
| CPU time | 499.16 seconds |
| Started | Oct 12 01:52:50 AM UTC 24 |
| Finished | Oct 12 02:01:15 AM UTC 24 |
| Peak memory | 210120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765320675 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_wakeup_fixed.1765320675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/31.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_fsm_reset.2221770686 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 132557235011 ps |
| CPU time | 596.88 seconds |
| Started | Oct 12 01:53:18 AM UTC 24 |
| Finished | Oct 12 02:03:21 AM UTC 24 |
| Peak memory | 210404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221770686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2221770686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/31.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_lowpower_counter.3866764935 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 28200300691 ps |
| CPU time | 41.88 seconds |
| Started | Oct 12 01:53:12 AM UTC 24 |
| Finished | Oct 12 01:53:55 AM UTC 24 |
| Peak memory | 209996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866764935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.3866764935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/31.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_poweron_counter.1108215880 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 3301856367 ps |
| CPU time | 3.84 seconds |
| Started | Oct 12 01:53:06 AM UTC 24 |
| Finished | Oct 12 01:53:11 AM UTC 24 |
| Peak memory | 210060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108215880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.1108215880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/31.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_smoke.2726615492 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 5601350131 ps |
| CPU time | 7.2 seconds |
| Started | Oct 12 01:52:19 AM UTC 24 |
| Finished | Oct 12 01:52:27 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726615492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.2726615492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/31.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_stress_all.1659501866 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 207067187414 ps |
| CPU time | 636.05 seconds |
| Started | Oct 12 01:53:20 AM UTC 24 |
| Finished | Oct 12 02:04:03 AM UTC 24 |
| Peak memory | 210068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659501866 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.1659501866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/31.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.402651688 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 3747603593 ps |
| CPU time | 16.48 seconds |
| Started | Oct 12 01:53:18 AM UTC 24 |
| Finished | Oct 12 01:53:35 AM UTC 24 |
| Peak memory | 220576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=402651688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.402651688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/31.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_alert_test.2628754920 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 323926551 ps |
| CPU time | 1.91 seconds |
| Started | Oct 12 01:55:11 AM UTC 24 |
| Finished | Oct 12 01:55:14 AM UTC 24 |
| Peak memory | 208944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628754920 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.2628754920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/32.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_clock_gating.16529577 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 528377722835 ps |
| CPU time | 570.94 seconds |
| Started | Oct 12 01:54:39 AM UTC 24 |
| Finished | Oct 12 02:04:16 AM UTC 24 |
| Peak memory | 210132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16529577 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gating.16529577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/32.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_interrupt.3939360111 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 156461560427 ps |
| CPU time | 89.34 seconds |
| Started | Oct 12 01:53:56 AM UTC 24 |
| Finished | Oct 12 01:55:27 AM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939360111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.3939360111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/32.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3207100473 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 163467003865 ps |
| CPU time | 60.74 seconds |
| Started | Oct 12 01:54:00 AM UTC 24 |
| Finished | Oct 12 01:55:03 AM UTC 24 |
| Peak memory | 210128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207100473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt_fixed.3207100473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/32.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_polled.2273694142 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 495890961554 ps |
| CPU time | 269.26 seconds |
| Started | Oct 12 01:53:39 AM UTC 24 |
| Finished | Oct 12 01:58:12 AM UTC 24 |
| Peak memory | 210072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273694142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2273694142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/32.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_polled_fixed.3384006198 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 495910352051 ps |
| CPU time | 1060.61 seconds |
| Started | Oct 12 01:53:42 AM UTC 24 |
| Finished | Oct 12 02:11:33 AM UTC 24 |
| Peak memory | 212712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384006198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixed.3384006198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/32.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_wakeup.1325958594 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 544729841191 ps |
| CPU time | 291.01 seconds |
| Started | Oct 12 01:54:17 AM UTC 24 |
| Finished | Oct 12 01:59:12 AM UTC 24 |
| Peak memory | 210140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325958594 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_wakeup.1325958594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/32.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3326960645 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 405201484884 ps |
| CPU time | 422.59 seconds |
| Started | Oct 12 01:54:37 AM UTC 24 |
| Finished | Oct 12 02:01:44 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326960645 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_wakeup_fixed.3326960645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/32.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_fsm_reset.1548097471 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 104244809778 ps |
| CPU time | 394.58 seconds |
| Started | Oct 12 01:55:02 AM UTC 24 |
| Finished | Oct 12 02:01:41 AM UTC 24 |
| Peak memory | 210540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548097471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.1548097471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/32.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_lowpower_counter.3447838682 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 30283254287 ps |
| CPU time | 49.69 seconds |
| Started | Oct 12 01:54:57 AM UTC 24 |
| Finished | Oct 12 01:55:48 AM UTC 24 |
| Peak memory | 210184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447838682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.3447838682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/32.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_poweron_counter.574697688 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 4966636530 ps |
| CPU time | 4.93 seconds |
| Started | Oct 12 01:54:55 AM UTC 24 |
| Finished | Oct 12 01:55:01 AM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574697688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.574697688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/32.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_smoke.3638408803 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 5920398458 ps |
| CPU time | 4.28 seconds |
| Started | Oct 12 01:53:36 AM UTC 24 |
| Finished | Oct 12 01:53:41 AM UTC 24 |
| Peak memory | 210192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638408803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.3638408803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/32.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_stress_all.1446532508 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 185156538430 ps |
| CPU time | 531.67 seconds |
| Started | Oct 12 01:55:10 AM UTC 24 |
| Finished | Oct 12 02:04:07 AM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446532508 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all.1446532508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/32.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.2539289020 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 3689278708 ps |
| CPU time | 5.03 seconds |
| Started | Oct 12 01:55:03 AM UTC 24 |
| Finished | Oct 12 01:55:09 AM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2539289020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 32.adc_ctrl_stress_all_with_rand_reset.2539289020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/32.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_alert_test.2376708385 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 492612088 ps |
| CPU time | 2.83 seconds |
| Started | Oct 12 01:55:49 AM UTC 24 |
| Finished | Oct 12 01:55:53 AM UTC 24 |
| Peak memory | 209920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376708385 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2376708385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/33.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_clock_gating.1438641877 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 177202641799 ps |
| CPU time | 104.85 seconds |
| Started | Oct 12 01:55:28 AM UTC 24 |
| Finished | Oct 12 01:57:15 AM UTC 24 |
| Peak memory | 210320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438641877 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gating.1438641877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/33.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_both.4272096657 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 355089918941 ps |
| CPU time | 851.73 seconds |
| Started | Oct 12 01:55:28 AM UTC 24 |
| Finished | Oct 12 02:09:48 AM UTC 24 |
| Peak memory | 212764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272096657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.4272096657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/33.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_interrupt.341237524 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 157191598337 ps |
| CPU time | 61.42 seconds |
| Started | Oct 12 01:55:14 AM UTC 24 |
| Finished | Oct 12 01:56:17 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341237524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.341237524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/33.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3249691560 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 164045358005 ps |
| CPU time | 508.21 seconds |
| Started | Oct 12 01:55:18 AM UTC 24 |
| Finished | Oct 12 02:03:52 AM UTC 24 |
| Peak memory | 210048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249691560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt_fixed.3249691560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/33.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_polled.1929492892 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 488284654238 ps |
| CPU time | 1147.72 seconds |
| Started | Oct 12 01:55:13 AM UTC 24 |
| Finished | Oct 12 02:14:32 AM UTC 24 |
| Peak memory | 212728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929492892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1929492892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/33.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_polled_fixed.3914226871 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 169425029977 ps |
| CPU time | 97.26 seconds |
| Started | Oct 12 01:55:13 AM UTC 24 |
| Finished | Oct 12 01:56:52 AM UTC 24 |
| Peak memory | 210068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914226871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixed.3914226871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/33.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_wakeup.565655372 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 175280139948 ps |
| CPU time | 282.27 seconds |
| Started | Oct 12 01:55:20 AM UTC 24 |
| Finished | Oct 12 02:00:05 AM UTC 24 |
| Peak memory | 210060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565655372 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_wakeup.565655372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/33.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_filters_wakeup_fixed.2762432490 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 611398624072 ps |
| CPU time | 408.52 seconds |
| Started | Oct 12 01:55:21 AM UTC 24 |
| Finished | Oct 12 02:02:14 AM UTC 24 |
| Peak memory | 210112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762432490 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_wakeup_fixed.2762432490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/33.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_lowpower_counter.3617794592 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 36633972318 ps |
| CPU time | 37.37 seconds |
| Started | Oct 12 01:55:32 AM UTC 24 |
| Finished | Oct 12 01:56:11 AM UTC 24 |
| Peak memory | 210060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617794592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3617794592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/33.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_poweron_counter.3566671133 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 5499513014 ps |
| CPU time | 24.07 seconds |
| Started | Oct 12 01:55:30 AM UTC 24 |
| Finished | Oct 12 01:55:55 AM UTC 24 |
| Peak memory | 210184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566671133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3566671133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/33.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_smoke.1340103027 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 5941258138 ps |
| CPU time | 6.92 seconds |
| Started | Oct 12 01:55:12 AM UTC 24 |
| Finished | Oct 12 01:55:20 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340103027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1340103027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/33.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_stress_all.4006007344 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 164938128208 ps |
| CPU time | 92.12 seconds |
| Started | Oct 12 01:55:44 AM UTC 24 |
| Finished | Oct 12 01:57:18 AM UTC 24 |
| Peak memory | 210064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006007344 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.4006007344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/33.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.756306185 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 1463337522 ps |
| CPU time | 7.12 seconds |
| Started | Oct 12 01:55:41 AM UTC 24 |
| Finished | Oct 12 01:55:49 AM UTC 24 |
| Peak memory | 210044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=756306185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.756306185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/33.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_alert_test.1165825236 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 558849303 ps |
| CPU time | 1.21 seconds |
| Started | Oct 12 01:57:21 AM UTC 24 |
| Finished | Oct 12 01:57:23 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165825236 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1165825236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/34.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_clock_gating.1372301194 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 341631946517 ps |
| CPU time | 920.02 seconds |
| Started | Oct 12 01:56:23 AM UTC 24 |
| Finished | Oct 12 02:11:52 AM UTC 24 |
| Peak memory | 212796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372301194 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gating.1372301194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/34.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_both.3874942026 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 198380902413 ps |
| CPU time | 200.55 seconds |
| Started | Oct 12 01:56:41 AM UTC 24 |
| Finished | Oct 12 02:00:04 AM UTC 24 |
| Peak memory | 210184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874942026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3874942026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/34.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_interrupt.3014281052 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 163914517388 ps |
| CPU time | 328.32 seconds |
| Started | Oct 12 01:55:56 AM UTC 24 |
| Finished | Oct 12 02:01:29 AM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014281052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.3014281052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/34.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3704167520 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 488714189819 ps |
| CPU time | 651.15 seconds |
| Started | Oct 12 01:55:58 AM UTC 24 |
| Finished | Oct 12 02:06:56 AM UTC 24 |
| Peak memory | 210300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704167520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt_fixed.3704167520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/34.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_polled.3695603925 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 167437178495 ps |
| CPU time | 128.16 seconds |
| Started | Oct 12 01:55:50 AM UTC 24 |
| Finished | Oct 12 01:58:01 AM UTC 24 |
| Peak memory | 210340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695603925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.3695603925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/34.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_polled_fixed.3316510842 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 494446137577 ps |
| CPU time | 321.54 seconds |
| Started | Oct 12 01:55:53 AM UTC 24 |
| Finished | Oct 12 02:01:19 AM UTC 24 |
| Peak memory | 210064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316510842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixed.3316510842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/34.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_wakeup.1506255835 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 181654781472 ps |
| CPU time | 77.86 seconds |
| Started | Oct 12 01:56:12 AM UTC 24 |
| Finished | Oct 12 01:57:31 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506255835 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_wakeup.1506255835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/34.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_wakeup_fixed.2153614725 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 197797711439 ps |
| CPU time | 267.22 seconds |
| Started | Oct 12 01:56:19 AM UTC 24 |
| Finished | Oct 12 02:00:49 AM UTC 24 |
| Peak memory | 210196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153614725 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_wakeup_fixed.2153614725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/34.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_fsm_reset.1734925058 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 92046864402 ps |
| CPU time | 332.47 seconds |
| Started | Oct 12 01:57:17 AM UTC 24 |
| Finished | Oct 12 02:02:53 AM UTC 24 |
| Peak memory | 210408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734925058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.1734925058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/34.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_lowpower_counter.47432076 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 41232202506 ps |
| CPU time | 12.58 seconds |
| Started | Oct 12 01:57:06 AM UTC 24 |
| Finished | Oct 12 01:57:20 AM UTC 24 |
| Peak memory | 210064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47432076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_ SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.47432076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/34.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_poweron_counter.3835960087 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 3987896728 ps |
| CPU time | 9.33 seconds |
| Started | Oct 12 01:56:53 AM UTC 24 |
| Finished | Oct 12 01:57:04 AM UTC 24 |
| Peak memory | 210184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835960087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.3835960087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/34.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_smoke.1446408930 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 5612006279 ps |
| CPU time | 6.74 seconds |
| Started | Oct 12 01:55:49 AM UTC 24 |
| Finished | Oct 12 01:55:57 AM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446408930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.1446408930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/34.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.2194144382 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 21118983374 ps |
| CPU time | 19.72 seconds |
| Started | Oct 12 01:57:17 AM UTC 24 |
| Finished | Oct 12 01:57:38 AM UTC 24 |
| Peak memory | 220984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2194144382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 34.adc_ctrl_stress_all_with_rand_reset.2194144382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/34.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_alert_test.570353735 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 538427592 ps |
| CPU time | 1.97 seconds |
| Started | Oct 12 01:58:30 AM UTC 24 |
| Finished | Oct 12 01:58:34 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570353735 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.570353735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/35.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_both.18837729 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 166177288060 ps |
| CPU time | 423.65 seconds |
| Started | Oct 12 01:57:57 AM UTC 24 |
| Finished | Oct 12 02:05:06 AM UTC 24 |
| Peak memory | 210124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18837729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_ SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.18837729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/35.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_interrupt_fixed.3834994261 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 333553069664 ps |
| CPU time | 197.56 seconds |
| Started | Oct 12 01:57:39 AM UTC 24 |
| Finished | Oct 12 02:00:59 AM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834994261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt_fixed.3834994261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/35.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_polled.1866594300 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 333667270065 ps |
| CPU time | 176.43 seconds |
| Started | Oct 12 01:57:32 AM UTC 24 |
| Finished | Oct 12 02:00:31 AM UTC 24 |
| Peak memory | 210060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866594300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.1866594300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/35.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_polled_fixed.1008436929 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 493725618584 ps |
| CPU time | 1189.97 seconds |
| Started | Oct 12 01:57:32 AM UTC 24 |
| Finished | Oct 12 02:17:33 AM UTC 24 |
| Peak memory | 212720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008436929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixed.1008436929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/35.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_wakeup.2295346101 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 690625886329 ps |
| CPU time | 392.04 seconds |
| Started | Oct 12 01:57:44 AM UTC 24 |
| Finished | Oct 12 02:04:20 AM UTC 24 |
| Peak memory | 210068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295346101 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_wakeup.2295346101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/35.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_wakeup_fixed.2525581337 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 387233800600 ps |
| CPU time | 235.74 seconds |
| Started | Oct 12 01:57:44 AM UTC 24 |
| Finished | Oct 12 02:01:43 AM UTC 24 |
| Peak memory | 210140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525581337 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_wakeup_fixed.2525581337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/35.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_fsm_reset.31175951 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 138410947991 ps |
| CPU time | 831.46 seconds |
| Started | Oct 12 01:58:10 AM UTC 24 |
| Finished | Oct 12 02:12:09 AM UTC 24 |
| Peak memory | 213144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31175951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_ SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.31175951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/35.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_lowpower_counter.2581782055 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 34358097626 ps |
| CPU time | 103.68 seconds |
| Started | Oct 12 01:58:07 AM UTC 24 |
| Finished | Oct 12 01:59:53 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581782055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2581782055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/35.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_poweron_counter.3840186733 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 4794491816 ps |
| CPU time | 3.4 seconds |
| Started | Oct 12 01:58:02 AM UTC 24 |
| Finished | Oct 12 01:58:06 AM UTC 24 |
| Peak memory | 209984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840186733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3840186733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/35.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_smoke.1064639446 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 6116860041 ps |
| CPU time | 16.42 seconds |
| Started | Oct 12 01:57:25 AM UTC 24 |
| Finished | Oct 12 01:57:43 AM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064639446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.1064639446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/35.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_stress_all.341053505 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 9802886079 ps |
| CPU time | 20.73 seconds |
| Started | Oct 12 01:58:14 AM UTC 24 |
| Finished | Oct 12 01:58:36 AM UTC 24 |
| Peak memory | 209976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341053505 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.341053505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/35.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_alert_test.3792835931 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 526677310 ps |
| CPU time | 1.15 seconds |
| Started | Oct 12 02:00:16 AM UTC 24 |
| Finished | Oct 12 02:00:18 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792835931 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.3792835931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/36.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_clock_gating.998025960 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 383769598128 ps |
| CPU time | 571.65 seconds |
| Started | Oct 12 01:59:25 AM UTC 24 |
| Finished | Oct 12 02:09:03 AM UTC 24 |
| Peak memory | 210064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998025960 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gating.998025960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/36.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_both.707419539 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 516876785943 ps |
| CPU time | 170.03 seconds |
| Started | Oct 12 01:59:38 AM UTC 24 |
| Finished | Oct 12 02:02:31 AM UTC 24 |
| Peak memory | 210132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707419539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.707419539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/36.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_interrupt.2774997680 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 161779081495 ps |
| CPU time | 154.62 seconds |
| Started | Oct 12 01:58:44 AM UTC 24 |
| Finished | Oct 12 02:01:21 AM UTC 24 |
| Peak memory | 210076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774997680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2774997680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/36.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_interrupt_fixed.1453698208 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 162341215581 ps |
| CPU time | 425.99 seconds |
| Started | Oct 12 01:58:48 AM UTC 24 |
| Finished | Oct 12 02:05:58 AM UTC 24 |
| Peak memory | 210316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453698208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt_fixed.1453698208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/36.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_polled.2492779117 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 329748523001 ps |
| CPU time | 306.14 seconds |
| Started | Oct 12 01:58:34 AM UTC 24 |
| Finished | Oct 12 02:03:44 AM UTC 24 |
| Peak memory | 209980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492779117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.2492779117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/36.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_polled_fixed.4019884056 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 489603755318 ps |
| CPU time | 1238.63 seconds |
| Started | Oct 12 01:58:37 AM UTC 24 |
| Finished | Oct 12 02:19:28 AM UTC 24 |
| Peak memory | 212780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019884056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixed.4019884056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/36.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_wakeup.1118604381 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 641149285649 ps |
| CPU time | 523.65 seconds |
| Started | Oct 12 01:59:01 AM UTC 24 |
| Finished | Oct 12 02:07:50 AM UTC 24 |
| Peak memory | 210140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118604381 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_wakeup.1118604381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/36.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_wakeup_fixed.4165370142 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 607999576770 ps |
| CPU time | 332.01 seconds |
| Started | Oct 12 01:59:13 AM UTC 24 |
| Finished | Oct 12 02:04:49 AM UTC 24 |
| Peak memory | 210048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165370142 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_wakeup_fixed.4165370142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/36.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_fsm_reset.1406005830 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 103025395646 ps |
| CPU time | 490.6 seconds |
| Started | Oct 12 02:00:06 AM UTC 24 |
| Finished | Oct 12 02:08:22 AM UTC 24 |
| Peak memory | 210488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406005830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1406005830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/36.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_lowpower_counter.2091985905 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 30824260478 ps |
| CPU time | 126.53 seconds |
| Started | Oct 12 01:59:58 AM UTC 24 |
| Finished | Oct 12 02:02:07 AM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091985905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2091985905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/36.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_poweron_counter.370464047 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 4041717500 ps |
| CPU time | 9.22 seconds |
| Started | Oct 12 01:59:53 AM UTC 24 |
| Finished | Oct 12 02:00:04 AM UTC 24 |
| Peak memory | 209980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370464047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.370464047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/36.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_smoke.4203195335 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 5728885171 ps |
| CPU time | 6.79 seconds |
| Started | Oct 12 01:58:34 AM UTC 24 |
| Finished | Oct 12 01:58:42 AM UTC 24 |
| Peak memory | 209928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203195335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.4203195335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/36.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_stress_all.1270038153 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 452201045548 ps |
| CPU time | 2159.22 seconds |
| Started | Oct 12 02:00:07 AM UTC 24 |
| Finished | Oct 12 02:36:28 AM UTC 24 |
| Peak memory | 225436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270038153 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.1270038153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/36.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.1697409908 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 4842384677 ps |
| CPU time | 6.87 seconds |
| Started | Oct 12 02:00:06 AM UTC 24 |
| Finished | Oct 12 02:00:14 AM UTC 24 |
| Peak memory | 210232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1697409908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 36.adc_ctrl_stress_all_with_rand_reset.1697409908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/36.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_alert_test.2730714747 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 342872417 ps |
| CPU time | 2.3 seconds |
| Started | Oct 12 02:01:20 AM UTC 24 |
| Finished | Oct 12 02:01:23 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730714747 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.2730714747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/37.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_clock_gating.2004090612 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 176550424707 ps |
| CPU time | 161.51 seconds |
| Started | Oct 12 02:00:59 AM UTC 24 |
| Finished | Oct 12 02:03:43 AM UTC 24 |
| Peak memory | 210260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004090612 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gating.2004090612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/37.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_interrupt.1061248081 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 321431816545 ps |
| CPU time | 821.11 seconds |
| Started | Oct 12 02:00:38 AM UTC 24 |
| Finished | Oct 12 02:14:27 AM UTC 24 |
| Peak memory | 212876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061248081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1061248081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/37.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_interrupt_fixed.784277201 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 321514050781 ps |
| CPU time | 287.26 seconds |
| Started | Oct 12 02:00:48 AM UTC 24 |
| Finished | Oct 12 02:05:39 AM UTC 24 |
| Peak memory | 210472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784277201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt_fixed.784277201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/37.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_polled.3295895111 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 326410011299 ps |
| CPU time | 500.76 seconds |
| Started | Oct 12 02:00:24 AM UTC 24 |
| Finished | Oct 12 02:08:50 AM UTC 24 |
| Peak memory | 210140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295895111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.3295895111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/37.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_polled_fixed.2370761504 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 329225755709 ps |
| CPU time | 1048.09 seconds |
| Started | Oct 12 02:00:32 AM UTC 24 |
| Finished | Oct 12 02:18:10 AM UTC 24 |
| Peak memory | 212792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370761504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixed.2370761504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/37.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_wakeup.1274905813 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 360803491036 ps |
| CPU time | 671.47 seconds |
| Started | Oct 12 02:00:50 AM UTC 24 |
| Finished | Oct 12 02:12:09 AM UTC 24 |
| Peak memory | 210264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274905813 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_wakeup.1274905813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/37.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2478182540 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 401242376838 ps |
| CPU time | 1132.72 seconds |
| Started | Oct 12 02:00:54 AM UTC 24 |
| Finished | Oct 12 02:19:58 AM UTC 24 |
| Peak memory | 212784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478182540 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_wakeup_fixed.2478182540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/37.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_fsm_reset.242534396 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 90648183191 ps |
| CPU time | 478.26 seconds |
| Started | Oct 12 02:01:14 AM UTC 24 |
| Finished | Oct 12 02:09:17 AM UTC 24 |
| Peak memory | 210476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242534396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.242534396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/37.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_lowpower_counter.3796753057 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 26610199334 ps |
| CPU time | 12.43 seconds |
| Started | Oct 12 02:01:05 AM UTC 24 |
| Finished | Oct 12 02:01:18 AM UTC 24 |
| Peak memory | 210184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796753057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.3796753057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/37.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_poweron_counter.2433343458 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 4382330074 ps |
| CPU time | 7.95 seconds |
| Started | Oct 12 02:01:03 AM UTC 24 |
| Finished | Oct 12 02:01:13 AM UTC 24 |
| Peak memory | 210060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433343458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.2433343458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/37.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_smoke.2563874762 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 6118859896 ps |
| CPU time | 26.56 seconds |
| Started | Oct 12 02:00:19 AM UTC 24 |
| Finished | Oct 12 02:00:47 AM UTC 24 |
| Peak memory | 210252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563874762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.2563874762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/37.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_stress_all.1455897953 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 335536716872 ps |
| CPU time | 780.76 seconds |
| Started | Oct 12 02:01:19 AM UTC 24 |
| Finished | Oct 12 02:14:28 AM UTC 24 |
| Peak memory | 210472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455897953 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.1455897953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/37.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.884748095 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 39839366007 ps |
| CPU time | 104.63 seconds |
| Started | Oct 12 02:01:16 AM UTC 24 |
| Finished | Oct 12 02:03:02 AM UTC 24 |
| Peak memory | 220984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=884748095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.884748095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/37.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_alert_test.1585358122 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 467654945 ps |
| CPU time | 1.32 seconds |
| Started | Oct 12 02:02:49 AM UTC 24 |
| Finished | Oct 12 02:02:51 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585358122 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.1585358122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/38.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_clock_gating.611149173 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 504843313011 ps |
| CPU time | 94.8 seconds |
| Started | Oct 12 02:02:01 AM UTC 24 |
| Finished | Oct 12 02:03:37 AM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611149173 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gating.611149173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/38.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_interrupt.493477629 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 486457888969 ps |
| CPU time | 663.9 seconds |
| Started | Oct 12 02:01:42 AM UTC 24 |
| Finished | Oct 12 02:12:53 AM UTC 24 |
| Peak memory | 210064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493477629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.493477629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/38.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_interrupt_fixed.4168131930 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 482094302338 ps |
| CPU time | 426.3 seconds |
| Started | Oct 12 02:01:43 AM UTC 24 |
| Finished | Oct 12 02:08:54 AM UTC 24 |
| Peak memory | 210048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168131930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt_fixed.4168131930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/38.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_polled.2598041874 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 494761034115 ps |
| CPU time | 340.96 seconds |
| Started | Oct 12 02:01:24 AM UTC 24 |
| Finished | Oct 12 02:07:09 AM UTC 24 |
| Peak memory | 210348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598041874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.2598041874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/38.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_polled_fixed.2596421380 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 492182593221 ps |
| CPU time | 1438.41 seconds |
| Started | Oct 12 02:01:29 AM UTC 24 |
| Finished | Oct 12 02:25:42 AM UTC 24 |
| Peak memory | 212916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596421380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fixed.2596421380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/38.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3744226441 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 604478218000 ps |
| CPU time | 1845.78 seconds |
| Started | Oct 12 02:01:49 AM UTC 24 |
| Finished | Oct 12 02:32:55 AM UTC 24 |
| Peak memory | 212712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744226441 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_wakeup_fixed.3744226441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/38.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_fsm_reset.2754273093 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 114734873098 ps |
| CPU time | 752.15 seconds |
| Started | Oct 12 02:02:21 AM UTC 24 |
| Finished | Oct 12 02:15:00 AM UTC 24 |
| Peak memory | 210680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754273093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.2754273093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/38.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_lowpower_counter.2305575442 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 36628339507 ps |
| CPU time | 23.43 seconds |
| Started | Oct 12 02:02:15 AM UTC 24 |
| Finished | Oct 12 02:02:39 AM UTC 24 |
| Peak memory | 209984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305575442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.2305575442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/38.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_poweron_counter.237627455 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 4811954263 ps |
| CPU time | 11.08 seconds |
| Started | Oct 12 02:02:08 AM UTC 24 |
| Finished | Oct 12 02:02:20 AM UTC 24 |
| Peak memory | 209980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237627455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.237627455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/38.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_smoke.1420962164 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 5908656842 ps |
| CPU time | 25.71 seconds |
| Started | Oct 12 02:01:22 AM UTC 24 |
| Finished | Oct 12 02:01:49 AM UTC 24 |
| Peak memory | 209992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420962164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1420962164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/38.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_stress_all.9773031 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 160396330216 ps |
| CPU time | 149.17 seconds |
| Started | Oct 12 02:02:40 AM UTC 24 |
| Finished | Oct 12 02:05:12 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9773031 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.9773031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/38.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.2904172527 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 183763850622 ps |
| CPU time | 45.1 seconds |
| Started | Oct 12 02:02:32 AM UTC 24 |
| Finished | Oct 12 02:03:18 AM UTC 24 |
| Peak memory | 210252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2904172527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 38.adc_ctrl_stress_all_with_rand_reset.2904172527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/38.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_alert_test.456277391 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 424941152 ps |
| CPU time | 2.6 seconds |
| Started | Oct 12 02:03:44 AM UTC 24 |
| Finished | Oct 12 02:03:48 AM UTC 24 |
| Peak memory | 210064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456277391 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.456277391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/39.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_clock_gating.37163309 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 497751016434 ps |
| CPU time | 108.53 seconds |
| Started | Oct 12 02:03:20 AM UTC 24 |
| Finished | Oct 12 02:05:10 AM UTC 24 |
| Peak memory | 210124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37163309 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gating.37163309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/39.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_both.74910948 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 171930586909 ps |
| CPU time | 482.28 seconds |
| Started | Oct 12 02:03:22 AM UTC 24 |
| Finished | Oct 12 02:11:29 AM UTC 24 |
| Peak memory | 210196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74910948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_ SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.74910948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/39.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_interrupt.412279338 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 160536969887 ps |
| CPU time | 363.18 seconds |
| Started | Oct 12 02:02:55 AM UTC 24 |
| Finished | Oct 12 02:09:03 AM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412279338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.412279338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/39.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_interrupt_fixed.3691669438 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 331784585657 ps |
| CPU time | 545.67 seconds |
| Started | Oct 12 02:03:01 AM UTC 24 |
| Finished | Oct 12 02:12:12 AM UTC 24 |
| Peak memory | 210116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691669438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt_fixed.3691669438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/39.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_polled.3717885807 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 492173224060 ps |
| CPU time | 1171.06 seconds |
| Started | Oct 12 02:02:53 AM UTC 24 |
| Finished | Oct 12 02:22:36 AM UTC 24 |
| Peak memory | 212716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717885807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.3717885807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/39.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_polled_fixed.1190813010 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 329124924744 ps |
| CPU time | 568.92 seconds |
| Started | Oct 12 02:02:53 AM UTC 24 |
| Finished | Oct 12 02:12:29 AM UTC 24 |
| Peak memory | 210272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190813010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixed.1190813010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/39.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_wakeup.4068116074 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 366239178645 ps |
| CPU time | 105.12 seconds |
| Started | Oct 12 02:03:04 AM UTC 24 |
| Finished | Oct 12 02:04:51 AM UTC 24 |
| Peak memory | 210332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068116074 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_wakeup.4068116074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/39.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_filters_wakeup_fixed.3922639025 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 205260214303 ps |
| CPU time | 150.29 seconds |
| Started | Oct 12 02:03:07 AM UTC 24 |
| Finished | Oct 12 02:05:39 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922639025 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_wakeup_fixed.3922639025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/39.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_fsm_reset.3907805467 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 131183121805 ps |
| CPU time | 747 seconds |
| Started | Oct 12 02:03:34 AM UTC 24 |
| Finished | Oct 12 02:16:09 AM UTC 24 |
| Peak memory | 210608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907805467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.3907805467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/39.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_lowpower_counter.2847272636 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 39203497987 ps |
| CPU time | 95.34 seconds |
| Started | Oct 12 02:03:30 AM UTC 24 |
| Finished | Oct 12 02:05:08 AM UTC 24 |
| Peak memory | 210184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847272636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.2847272636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/39.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_poweron_counter.3064348639 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 4133230600 ps |
| CPU time | 5.6 seconds |
| Started | Oct 12 02:03:26 AM UTC 24 |
| Finished | Oct 12 02:03:33 AM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064348639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.3064348639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/39.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_smoke.175345705 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 6058528176 ps |
| CPU time | 6.88 seconds |
| Started | Oct 12 02:02:52 AM UTC 24 |
| Finished | Oct 12 02:03:00 AM UTC 24 |
| Peak memory | 209984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175345705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.175345705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/39.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_stress_all.3853743628 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 171269484040 ps |
| CPU time | 117.38 seconds |
| Started | Oct 12 02:03:39 AM UTC 24 |
| Finished | Oct 12 02:05:39 AM UTC 24 |
| Peak memory | 210128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853743628 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.3853743628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/39.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.2908194925 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 10105388863 ps |
| CPU time | 9.36 seconds |
| Started | Oct 12 02:03:38 AM UTC 24 |
| Finished | Oct 12 02:03:49 AM UTC 24 |
| Peak memory | 210248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2908194925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 39.adc_ctrl_stress_all_with_rand_reset.2908194925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/39.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_alert_test.794680929 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 413956281 ps |
| CPU time | 0.97 seconds |
| Started | Oct 12 01:15:13 AM UTC 24 |
| Finished | Oct 12 01:15:15 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794680929 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.794680929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/4.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_clock_gating.239285609 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 339053105415 ps |
| CPU time | 549.81 seconds |
| Started | Oct 12 01:14:55 AM UTC 24 |
| Finished | Oct 12 01:24:11 AM UTC 24 |
| Peak memory | 210128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239285609 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gating.239285609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/4.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_both.3026394312 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 344670462456 ps |
| CPU time | 953.19 seconds |
| Started | Oct 12 01:14:55 AM UTC 24 |
| Finished | Oct 12 01:30:58 AM UTC 24 |
| Peak memory | 212776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026394312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.3026394312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/4.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt.1891574962 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 167402130347 ps |
| CPU time | 390.62 seconds |
| Started | Oct 12 01:14:47 AM UTC 24 |
| Finished | Oct 12 01:21:22 AM UTC 24 |
| Peak memory | 210328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891574962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.1891574962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/4.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt_fixed.166550460 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 163602740365 ps |
| CPU time | 175.55 seconds |
| Started | Oct 12 01:14:52 AM UTC 24 |
| Finished | Oct 12 01:17:50 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166550460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt_fixed.166550460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/4.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled.3427052751 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 166453367900 ps |
| CPU time | 158.24 seconds |
| Started | Oct 12 01:14:45 AM UTC 24 |
| Finished | Oct 12 01:17:26 AM UTC 24 |
| Peak memory | 210124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427052751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.3427052751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/4.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled_fixed.3577859847 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 161269773907 ps |
| CPU time | 199.66 seconds |
| Started | Oct 12 01:14:46 AM UTC 24 |
| Finished | Oct 12 01:18:09 AM UTC 24 |
| Peak memory | 210264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577859847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed.3577859847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/4.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3046687286 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 194106195224 ps |
| CPU time | 519.76 seconds |
| Started | Oct 12 01:14:55 AM UTC 24 |
| Finished | Oct 12 01:23:40 AM UTC 24 |
| Peak memory | 210116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046687286 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_wakeup_fixed.3046687286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/4.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_fsm_reset.730738237 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 75600880999 ps |
| CPU time | 458.75 seconds |
| Started | Oct 12 01:15:03 AM UTC 24 |
| Finished | Oct 12 01:22:47 AM UTC 24 |
| Peak memory | 210396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730738237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.730738237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/4.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_lowpower_counter.942368071 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 37252412135 ps |
| CPU time | 12.62 seconds |
| Started | Oct 12 01:14:58 AM UTC 24 |
| Finished | Oct 12 01:15:12 AM UTC 24 |
| Peak memory | 209996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942368071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.942368071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/4.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_poweron_counter.2930507995 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 3782728520 ps |
| CPU time | 4.44 seconds |
| Started | Oct 12 01:14:57 AM UTC 24 |
| Finished | Oct 12 01:15:03 AM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930507995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.2930507995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/4.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_sec_cm.320665433 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 8121188760 ps |
| CPU time | 20.69 seconds |
| Started | Oct 12 01:15:07 AM UTC 24 |
| Finished | Oct 12 01:15:29 AM UTC 24 |
| Peak memory | 242504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320665433 -assert nopostproc +UVM_TESTNAME=adc _ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.320665433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/4.adc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_smoke.4249706531 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 5984665325 ps |
| CPU time | 14.35 seconds |
| Started | Oct 12 01:14:42 AM UTC 24 |
| Finished | Oct 12 01:14:58 AM UTC 24 |
| Peak memory | 210060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249706531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.4249706531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/4.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all.2452975280 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 485578821111 ps |
| CPU time | 94.69 seconds |
| Started | Oct 12 01:15:06 AM UTC 24 |
| Finished | Oct 12 01:16:42 AM UTC 24 |
| Peak memory | 210228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452975280 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.2452975280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.7065158 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 2347829236 ps |
| CPU time | 10.71 seconds |
| Started | Oct 12 01:15:04 AM UTC 24 |
| Finished | Oct 12 01:15:15 AM UTC 24 |
| Peak memory | 210184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=7065158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4 .adc_ctrl_stress_all_with_rand_reset.7065158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_alert_test.3688252941 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 360712736 ps |
| CPU time | 0.99 seconds |
| Started | Oct 12 02:04:48 AM UTC 24 |
| Finished | Oct 12 02:04:50 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688252941 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.3688252941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/40.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_clock_gating.1170788282 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 349237196164 ps |
| CPU time | 156.4 seconds |
| Started | Oct 12 02:04:08 AM UTC 24 |
| Finished | Oct 12 02:06:47 AM UTC 24 |
| Peak memory | 210328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170788282 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gating.1170788282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/40.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_both.339887280 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 526751965264 ps |
| CPU time | 603.57 seconds |
| Started | Oct 12 02:04:16 AM UTC 24 |
| Finished | Oct 12 02:14:26 AM UTC 24 |
| Peak memory | 210112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339887280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.339887280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/40.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_interrupt.2862954726 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 485545914745 ps |
| CPU time | 1279.96 seconds |
| Started | Oct 12 02:03:53 AM UTC 24 |
| Finished | Oct 12 02:25:25 AM UTC 24 |
| Peak memory | 212744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862954726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.2862954726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/40.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1268670465 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 161771547204 ps |
| CPU time | 63.51 seconds |
| Started | Oct 12 02:03:55 AM UTC 24 |
| Finished | Oct 12 02:05:00 AM UTC 24 |
| Peak memory | 210128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268670465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt_fixed.1268670465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/40.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_polled.3522349078 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 327946661018 ps |
| CPU time | 38.95 seconds |
| Started | Oct 12 02:03:48 AM UTC 24 |
| Finished | Oct 12 02:04:29 AM UTC 24 |
| Peak memory | 210140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522349078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3522349078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/40.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_polled_fixed.1703696047 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 158925519681 ps |
| CPU time | 102.72 seconds |
| Started | Oct 12 02:03:49 AM UTC 24 |
| Finished | Oct 12 02:05:34 AM UTC 24 |
| Peak memory | 210344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703696047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixed.1703696047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/40.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_wakeup.4189676459 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 362402275497 ps |
| CPU time | 280.17 seconds |
| Started | Oct 12 02:03:57 AM UTC 24 |
| Finished | Oct 12 02:08:41 AM UTC 24 |
| Peak memory | 210068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189676459 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_wakeup.4189676459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/40.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_wakeup_fixed.509811563 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 405983789665 ps |
| CPU time | 1129.31 seconds |
| Started | Oct 12 02:04:04 AM UTC 24 |
| Finished | Oct 12 02:23:05 AM UTC 24 |
| Peak memory | 212776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509811563 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_wakeup_fixed.509811563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/40.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_fsm_reset.4248586815 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 88745066489 ps |
| CPU time | 458.19 seconds |
| Started | Oct 12 02:04:31 AM UTC 24 |
| Finished | Oct 12 02:12:14 AM UTC 24 |
| Peak memory | 210560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248586815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.4248586815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/40.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_lowpower_counter.1500846300 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 40593063231 ps |
| CPU time | 128.24 seconds |
| Started | Oct 12 02:04:30 AM UTC 24 |
| Finished | Oct 12 02:06:41 AM UTC 24 |
| Peak memory | 209984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500846300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.1500846300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/40.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_poweron_counter.3812755978 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 4052989532 ps |
| CPU time | 12.39 seconds |
| Started | Oct 12 02:04:21 AM UTC 24 |
| Finished | Oct 12 02:04:35 AM UTC 24 |
| Peak memory | 210252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812755978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3812755978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/40.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_smoke.2966392413 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 5708068454 ps |
| CPU time | 6.92 seconds |
| Started | Oct 12 02:03:45 AM UTC 24 |
| Finished | Oct 12 02:03:54 AM UTC 24 |
| Peak memory | 209992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966392413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.2966392413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/40.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_stress_all.3155038798 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 2317741501 ps |
| CPU time | 3.62 seconds |
| Started | Oct 12 02:04:43 AM UTC 24 |
| Finished | Oct 12 02:04:48 AM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155038798 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.3155038798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/40.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.1847811356 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 1381124738 ps |
| CPU time | 6.64 seconds |
| Started | Oct 12 02:04:35 AM UTC 24 |
| Finished | Oct 12 02:04:43 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1847811356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 40.adc_ctrl_stress_all_with_rand_reset.1847811356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/40.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_alert_test.1927310167 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 546913695 ps |
| CPU time | 1.32 seconds |
| Started | Oct 12 02:06:00 AM UTC 24 |
| Finished | Oct 12 02:06:02 AM UTC 24 |
| Peak memory | 208944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927310167 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.1927310167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/41.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_clock_gating.1027367121 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 356910668268 ps |
| CPU time | 524.78 seconds |
| Started | Oct 12 02:05:13 AM UTC 24 |
| Finished | Oct 12 02:14:04 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027367121 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gating.1027367121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/41.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_interrupt.349204963 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 496168204444 ps |
| CPU time | 95.83 seconds |
| Started | Oct 12 02:05:01 AM UTC 24 |
| Finished | Oct 12 02:06:38 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349204963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.349204963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/41.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_interrupt_fixed.447374466 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 488511400837 ps |
| CPU time | 645.97 seconds |
| Started | Oct 12 02:05:07 AM UTC 24 |
| Finished | Oct 12 02:16:00 AM UTC 24 |
| Peak memory | 210116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447374466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt_fixed.447374466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/41.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_polled_fixed.4011596395 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 164607453771 ps |
| CPU time | 359.4 seconds |
| Started | Oct 12 02:04:52 AM UTC 24 |
| Finished | Oct 12 02:10:55 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011596395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fixed.4011596395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/41.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_wakeup.212273199 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 547435182447 ps |
| CPU time | 475.56 seconds |
| Started | Oct 12 02:05:09 AM UTC 24 |
| Finished | Oct 12 02:13:10 AM UTC 24 |
| Peak memory | 210064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212273199 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_wakeup.212273199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/41.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1929870742 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 596530308459 ps |
| CPU time | 536.42 seconds |
| Started | Oct 12 02:05:11 AM UTC 24 |
| Finished | Oct 12 02:14:14 AM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929870742 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_wakeup_fixed.1929870742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/41.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_fsm_reset.2775198082 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 88513372371 ps |
| CPU time | 379.01 seconds |
| Started | Oct 12 02:05:40 AM UTC 24 |
| Finished | Oct 12 02:12:04 AM UTC 24 |
| Peak memory | 210548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775198082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.2775198082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/41.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_lowpower_counter.138895338 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 32868572508 ps |
| CPU time | 70.34 seconds |
| Started | Oct 12 02:05:39 AM UTC 24 |
| Finished | Oct 12 02:06:51 AM UTC 24 |
| Peak memory | 210184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138895338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.138895338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/41.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_poweron_counter.1490095677 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 3209425067 ps |
| CPU time | 13.34 seconds |
| Started | Oct 12 02:05:35 AM UTC 24 |
| Finished | Oct 12 02:05:50 AM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490095677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1490095677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/41.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_smoke.2003013651 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 5996967971 ps |
| CPU time | 25.97 seconds |
| Started | Oct 12 02:04:49 AM UTC 24 |
| Finished | Oct 12 02:05:17 AM UTC 24 |
| Peak memory | 210192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003013651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.2003013651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/41.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_stress_all.766956048 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 336785682982 ps |
| CPU time | 191.02 seconds |
| Started | Oct 12 02:05:50 AM UTC 24 |
| Finished | Oct 12 02:09:04 AM UTC 24 |
| Peak memory | 210116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766956048 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.766956048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/41.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_alert_test.1750368899 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 358644037 ps |
| CPU time | 2.19 seconds |
| Started | Oct 12 02:07:51 AM UTC 24 |
| Finished | Oct 12 02:07:54 AM UTC 24 |
| Peak memory | 210048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750368899 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1750368899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/42.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_clock_gating.1454130121 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 535209306066 ps |
| CPU time | 821.8 seconds |
| Started | Oct 12 02:06:52 AM UTC 24 |
| Finished | Oct 12 02:20:42 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454130121 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gating.1454130121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/42.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_both.2707210524 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 530690507220 ps |
| CPU time | 452.88 seconds |
| Started | Oct 12 02:06:56 AM UTC 24 |
| Finished | Oct 12 02:14:34 AM UTC 24 |
| Peak memory | 210128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707210524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.2707210524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/42.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_interrupt.1341197788 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 166476381699 ps |
| CPU time | 46.38 seconds |
| Started | Oct 12 02:06:29 AM UTC 24 |
| Finished | Oct 12 02:07:17 AM UTC 24 |
| Peak memory | 210072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341197788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.1341197788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/42.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_interrupt_fixed.1330666807 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 162966792866 ps |
| CPU time | 368.06 seconds |
| Started | Oct 12 02:06:39 AM UTC 24 |
| Finished | Oct 12 02:12:51 AM UTC 24 |
| Peak memory | 210128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330666807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt_fixed.1330666807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/42.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_polled.3557719169 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 170200164454 ps |
| CPU time | 472.48 seconds |
| Started | Oct 12 02:06:09 AM UTC 24 |
| Finished | Oct 12 02:14:06 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557719169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.3557719169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/42.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_polled_fixed.2123347339 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 492863852225 ps |
| CPU time | 1551.82 seconds |
| Started | Oct 12 02:06:26 AM UTC 24 |
| Finished | Oct 12 02:32:33 AM UTC 24 |
| Peak memory | 212704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123347339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixed.2123347339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/42.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_wakeup.2513642721 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 542497800692 ps |
| CPU time | 83.23 seconds |
| Started | Oct 12 02:06:41 AM UTC 24 |
| Finished | Oct 12 02:08:06 AM UTC 24 |
| Peak memory | 210068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513642721 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_wakeup.2513642721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/42.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3351101292 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 594724498019 ps |
| CPU time | 1722.64 seconds |
| Started | Oct 12 02:06:47 AM UTC 24 |
| Finished | Oct 12 02:35:47 AM UTC 24 |
| Peak memory | 212704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351101292 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_wakeup_fixed.3351101292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/42.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_fsm_reset.3452641633 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 86851769467 ps |
| CPU time | 432.12 seconds |
| Started | Oct 12 02:07:18 AM UTC 24 |
| Finished | Oct 12 02:14:34 AM UTC 24 |
| Peak memory | 210560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452641633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.3452641633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/42.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_lowpower_counter.2643847213 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 34952121653 ps |
| CPU time | 71.93 seconds |
| Started | Oct 12 02:07:16 AM UTC 24 |
| Finished | Oct 12 02:08:29 AM UTC 24 |
| Peak memory | 210184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643847213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2643847213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/42.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_poweron_counter.3780710251 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 4077079852 ps |
| CPU time | 18.08 seconds |
| Started | Oct 12 02:07:09 AM UTC 24 |
| Finished | Oct 12 02:07:29 AM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780710251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3780710251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/42.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_smoke.3414929928 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 5775999497 ps |
| CPU time | 24.63 seconds |
| Started | Oct 12 02:06:03 AM UTC 24 |
| Finished | Oct 12 02:06:28 AM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414929928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3414929928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/42.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_stress_all.2494916666 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 498355408138 ps |
| CPU time | 684.23 seconds |
| Started | Oct 12 02:07:30 AM UTC 24 |
| Finished | Oct 12 02:19:01 AM UTC 24 |
| Peak memory | 222644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494916666 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.2494916666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/42.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1893156973 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 170844695217 ps |
| CPU time | 31.72 seconds |
| Started | Oct 12 02:07:29 AM UTC 24 |
| Finished | Oct 12 02:08:02 AM UTC 24 |
| Peak memory | 220708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1893156973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 42.adc_ctrl_stress_all_with_rand_reset.1893156973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/42.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_alert_test.838595651 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 381718827 ps |
| CPU time | 2.36 seconds |
| Started | Oct 12 02:09:15 AM UTC 24 |
| Finished | Oct 12 02:09:19 AM UTC 24 |
| Peak memory | 210064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838595651 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.838595651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/43.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_clock_gating.440991883 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 496982608642 ps |
| CPU time | 90.8 seconds |
| Started | Oct 12 02:08:42 AM UTC 24 |
| Finished | Oct 12 02:10:14 AM UTC 24 |
| Peak memory | 210324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440991883 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gating.440991883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/43.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_both.82859874 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 174344310750 ps |
| CPU time | 470.06 seconds |
| Started | Oct 12 02:08:51 AM UTC 24 |
| Finished | Oct 12 02:16:47 AM UTC 24 |
| Peak memory | 210244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82859874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_ SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.82859874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/43.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_interrupt.1622044029 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 487302068145 ps |
| CPU time | 429.41 seconds |
| Started | Oct 12 02:08:08 AM UTC 24 |
| Finished | Oct 12 02:15:23 AM UTC 24 |
| Peak memory | 210348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622044029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1622044029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/43.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1453593090 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 491378749141 ps |
| CPU time | 672.04 seconds |
| Started | Oct 12 02:08:23 AM UTC 24 |
| Finished | Oct 12 02:19:42 AM UTC 24 |
| Peak memory | 210108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453593090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt_fixed.1453593090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/43.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_polled.1891434127 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 498169325132 ps |
| CPU time | 300.3 seconds |
| Started | Oct 12 02:08:03 AM UTC 24 |
| Finished | Oct 12 02:13:07 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891434127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.1891434127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/43.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_polled_fixed.1040859121 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 155599042648 ps |
| CPU time | 133.68 seconds |
| Started | Oct 12 02:08:07 AM UTC 24 |
| Finished | Oct 12 02:10:23 AM UTC 24 |
| Peak memory | 210264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040859121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixed.1040859121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/43.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_wakeup.1971037481 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 621601245072 ps |
| CPU time | 1682.91 seconds |
| Started | Oct 12 02:08:30 AM UTC 24 |
| Finished | Oct 12 02:36:51 AM UTC 24 |
| Peak memory | 212720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971037481 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_wakeup.1971037481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/43.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_wakeup_fixed.564988383 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 605415862050 ps |
| CPU time | 1447.41 seconds |
| Started | Oct 12 02:08:40 AM UTC 24 |
| Finished | Oct 12 02:33:02 AM UTC 24 |
| Peak memory | 212764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564988383 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_wakeup_fixed.564988383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/43.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_fsm_reset.7049499 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 94536820414 ps |
| CPU time | 424.22 seconds |
| Started | Oct 12 02:09:04 AM UTC 24 |
| Finished | Oct 12 02:16:13 AM UTC 24 |
| Peak memory | 210488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7049499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_S EQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.7049499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/43.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_lowpower_counter.2636521756 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 43522971215 ps |
| CPU time | 90.52 seconds |
| Started | Oct 12 02:09:01 AM UTC 24 |
| Finished | Oct 12 02:10:33 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636521756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.2636521756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/43.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_poweron_counter.4090533669 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 3376626497 ps |
| CPU time | 2.77 seconds |
| Started | Oct 12 02:08:56 AM UTC 24 |
| Finished | Oct 12 02:09:00 AM UTC 24 |
| Peak memory | 209996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090533669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.4090533669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/43.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_smoke.1739848024 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 5705064567 ps |
| CPU time | 10.76 seconds |
| Started | Oct 12 02:07:55 AM UTC 24 |
| Finished | Oct 12 02:08:07 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739848024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1739848024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/43.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_stress_all.1148851040 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 281141385738 ps |
| CPU time | 998.34 seconds |
| Started | Oct 12 02:09:05 AM UTC 24 |
| Finished | Oct 12 02:25:53 AM UTC 24 |
| Peak memory | 225352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148851040 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.1148851040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/43.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.674482326 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 25277491483 ps |
| CPU time | 24.39 seconds |
| Started | Oct 12 02:09:04 AM UTC 24 |
| Finished | Oct 12 02:09:30 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=674482326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.674482326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/43.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_alert_test.1315592709 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 432012000 ps |
| CPU time | 1.44 seconds |
| Started | Oct 12 02:11:21 AM UTC 24 |
| Finished | Oct 12 02:11:23 AM UTC 24 |
| Peak memory | 208944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315592709 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.1315592709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/44.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_clock_gating.117614314 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 168269140389 ps |
| CPU time | 288.68 seconds |
| Started | Oct 12 02:10:24 AM UTC 24 |
| Finished | Oct 12 02:15:16 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117614314 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gating.117614314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/44.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_both.107068622 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 173401091544 ps |
| CPU time | 559.98 seconds |
| Started | Oct 12 02:10:28 AM UTC 24 |
| Finished | Oct 12 02:19:54 AM UTC 24 |
| Peak memory | 210264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107068622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.107068622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/44.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_interrupt.2595798177 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 165341094400 ps |
| CPU time | 383.78 seconds |
| Started | Oct 12 02:09:30 AM UTC 24 |
| Finished | Oct 12 02:15:59 AM UTC 24 |
| Peak memory | 210424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595798177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.2595798177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/44.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_interrupt_fixed.2192650272 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 495247532818 ps |
| CPU time | 399.61 seconds |
| Started | Oct 12 02:09:49 AM UTC 24 |
| Finished | Oct 12 02:16:33 AM UTC 24 |
| Peak memory | 210060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192650272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt_fixed.2192650272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/44.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_polled.323968091 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 166173987337 ps |
| CPU time | 627.29 seconds |
| Started | Oct 12 02:09:19 AM UTC 24 |
| Finished | Oct 12 02:19:54 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323968091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.323968091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/44.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_polled_fixed.1023266457 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 497058136635 ps |
| CPU time | 1261.95 seconds |
| Started | Oct 12 02:09:27 AM UTC 24 |
| Finished | Oct 12 02:30:43 AM UTC 24 |
| Peak memory | 212712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023266457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixed.1023266457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/44.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_wakeup_fixed.2079714503 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 408497550636 ps |
| CPU time | 1235.85 seconds |
| Started | Oct 12 02:10:15 AM UTC 24 |
| Finished | Oct 12 02:31:03 AM UTC 24 |
| Peak memory | 212692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079714503 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_wakeup_fixed.2079714503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/44.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_fsm_reset.2967884085 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 125692023072 ps |
| CPU time | 881.76 seconds |
| Started | Oct 12 02:10:56 AM UTC 24 |
| Finished | Oct 12 02:25:47 AM UTC 24 |
| Peak memory | 210480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967884085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.2967884085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/44.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_lowpower_counter.4108145321 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 41799640891 ps |
| CPU time | 22.5 seconds |
| Started | Oct 12 02:10:45 AM UTC 24 |
| Finished | Oct 12 02:11:09 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108145321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.4108145321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/44.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_poweron_counter.1843333523 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 4141280763 ps |
| CPU time | 9.54 seconds |
| Started | Oct 12 02:10:34 AM UTC 24 |
| Finished | Oct 12 02:10:45 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843333523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.1843333523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/44.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_smoke.3723716858 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 5873428325 ps |
| CPU time | 7.14 seconds |
| Started | Oct 12 02:09:18 AM UTC 24 |
| Finished | Oct 12 02:09:26 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723716858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.3723716858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/44.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_stress_all.109569390 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 363892181781 ps |
| CPU time | 211.85 seconds |
| Started | Oct 12 02:11:09 AM UTC 24 |
| Finished | Oct 12 02:14:44 AM UTC 24 |
| Peak memory | 210396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109569390 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.109569390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/44.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.3601601112 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 6319659270 ps |
| CPU time | 12.02 seconds |
| Started | Oct 12 02:11:06 AM UTC 24 |
| Finished | Oct 12 02:11:20 AM UTC 24 |
| Peak memory | 210252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3601601112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 44.adc_ctrl_stress_all_with_rand_reset.3601601112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/44.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_alert_test.4135217935 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 298635958 ps |
| CPU time | 2.08 seconds |
| Started | Oct 12 02:13:04 AM UTC 24 |
| Finished | Oct 12 02:13:07 AM UTC 24 |
| Peak memory | 210124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135217935 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.4135217935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/45.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_clock_gating.110935807 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 351323806951 ps |
| CPU time | 739.55 seconds |
| Started | Oct 12 02:12:10 AM UTC 24 |
| Finished | Oct 12 02:24:38 AM UTC 24 |
| Peak memory | 210124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110935807 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gating.110935807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/45.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_both.831395378 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 502028593205 ps |
| CPU time | 1125.69 seconds |
| Started | Oct 12 02:12:13 AM UTC 24 |
| Finished | Oct 12 02:31:11 AM UTC 24 |
| Peak memory | 212972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831395378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.831395378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/45.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_interrupt.3554893550 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 331773010098 ps |
| CPU time | 930.68 seconds |
| Started | Oct 12 02:11:34 AM UTC 24 |
| Finished | Oct 12 02:27:14 AM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554893550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.3554893550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/45.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_interrupt_fixed.2555762726 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 488923405115 ps |
| CPU time | 705.46 seconds |
| Started | Oct 12 02:11:53 AM UTC 24 |
| Finished | Oct 12 02:23:46 AM UTC 24 |
| Peak memory | 210316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555762726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt_fixed.2555762726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/45.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_polled.785631418 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 494924111346 ps |
| CPU time | 680.02 seconds |
| Started | Oct 12 02:11:30 AM UTC 24 |
| Finished | Oct 12 02:22:57 AM UTC 24 |
| Peak memory | 210132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785631418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.785631418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/45.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_polled_fixed.4259738622 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 325693504663 ps |
| CPU time | 337.64 seconds |
| Started | Oct 12 02:11:32 AM UTC 24 |
| Finished | Oct 12 02:17:14 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259738622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixed.4259738622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/45.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_wakeup.1112702692 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 536276034003 ps |
| CPU time | 1311.35 seconds |
| Started | Oct 12 02:12:05 AM UTC 24 |
| Finished | Oct 12 02:34:10 AM UTC 24 |
| Peak memory | 212920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112702692 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_wakeup.1112702692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/45.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2145926955 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 193074078488 ps |
| CPU time | 553.5 seconds |
| Started | Oct 12 02:12:10 AM UTC 24 |
| Finished | Oct 12 02:21:30 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145926955 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_wakeup_fixed.2145926955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/45.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_fsm_reset.3385609516 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 131312988583 ps |
| CPU time | 669.92 seconds |
| Started | Oct 12 02:12:38 AM UTC 24 |
| Finished | Oct 12 02:23:55 AM UTC 24 |
| Peak memory | 210548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385609516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.3385609516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/45.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_lowpower_counter.2233569130 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 27155995415 ps |
| CPU time | 72.88 seconds |
| Started | Oct 12 02:12:29 AM UTC 24 |
| Finished | Oct 12 02:13:44 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233569130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2233569130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/45.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_poweron_counter.2375265999 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 4849571773 ps |
| CPU time | 20.3 seconds |
| Started | Oct 12 02:12:15 AM UTC 24 |
| Finished | Oct 12 02:12:37 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375265999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2375265999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/45.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_smoke.458618518 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 5708618014 ps |
| CPU time | 6.25 seconds |
| Started | Oct 12 02:11:24 AM UTC 24 |
| Finished | Oct 12 02:11:31 AM UTC 24 |
| Peak memory | 209984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458618518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.458618518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/45.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_stress_all.1946406478 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 324220113290 ps |
| CPU time | 869.78 seconds |
| Started | Oct 12 02:12:54 AM UTC 24 |
| Finished | Oct 12 02:27:33 AM UTC 24 |
| Peak memory | 210460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946406478 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all.1946406478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/45.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1775835923 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 3173535606 ps |
| CPU time | 10.16 seconds |
| Started | Oct 12 02:12:52 AM UTC 24 |
| Finished | Oct 12 02:13:03 AM UTC 24 |
| Peak memory | 220632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1775835923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 45.adc_ctrl_stress_all_with_rand_reset.1775835923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/45.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_alert_test.2639035378 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 555272722 ps |
| CPU time | 1.4 seconds |
| Started | Oct 12 02:14:35 AM UTC 24 |
| Finished | Oct 12 02:14:37 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639035378 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2639035378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/46.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_clock_gating.2659087823 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 177524772575 ps |
| CPU time | 81.61 seconds |
| Started | Oct 12 02:14:08 AM UTC 24 |
| Finished | Oct 12 02:15:31 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659087823 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gating.2659087823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/46.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_interrupt.3116161750 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 495282864489 ps |
| CPU time | 347.19 seconds |
| Started | Oct 12 02:13:31 AM UTC 24 |
| Finished | Oct 12 02:19:23 AM UTC 24 |
| Peak memory | 210164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116161750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.3116161750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/46.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_interrupt_fixed.2349991255 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 323708930618 ps |
| CPU time | 481.96 seconds |
| Started | Oct 12 02:13:40 AM UTC 24 |
| Finished | Oct 12 02:21:48 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349991255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt_fixed.2349991255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/46.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_polled.1756177734 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 167880303338 ps |
| CPU time | 334.22 seconds |
| Started | Oct 12 02:13:08 AM UTC 24 |
| Finished | Oct 12 02:18:46 AM UTC 24 |
| Peak memory | 210120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756177734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.1756177734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/46.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_polled_fixed.996901756 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 490963841551 ps |
| CPU time | 538.05 seconds |
| Started | Oct 12 02:13:11 AM UTC 24 |
| Finished | Oct 12 02:22:15 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996901756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fixed.996901756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/46.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_wakeup.2393484089 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 363390121410 ps |
| CPU time | 331.82 seconds |
| Started | Oct 12 02:13:45 AM UTC 24 |
| Finished | Oct 12 02:19:21 AM UTC 24 |
| Peak memory | 210064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393484089 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_wakeup.2393484089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/46.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_wakeup_fixed.552827004 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 396821724007 ps |
| CPU time | 993.46 seconds |
| Started | Oct 12 02:14:04 AM UTC 24 |
| Finished | Oct 12 02:30:48 AM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552827004 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_wakeup_fixed.552827004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/46.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_lowpower_counter.2010169078 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 26514054995 ps |
| CPU time | 16.34 seconds |
| Started | Oct 12 02:14:28 AM UTC 24 |
| Finished | Oct 12 02:14:45 AM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010169078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2010169078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/46.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_poweron_counter.2011022129 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 3138211552 ps |
| CPU time | 13.53 seconds |
| Started | Oct 12 02:14:27 AM UTC 24 |
| Finished | Oct 12 02:14:41 AM UTC 24 |
| Peak memory | 210184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011022129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2011022129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/46.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_smoke.250893034 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 5500180922 ps |
| CPU time | 21.49 seconds |
| Started | Oct 12 02:13:08 AM UTC 24 |
| Finished | Oct 12 02:13:31 AM UTC 24 |
| Peak memory | 209984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250893034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.250893034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/46.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_stress_all.3637977735 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 523032540299 ps |
| CPU time | 739.74 seconds |
| Started | Oct 12 02:14:35 AM UTC 24 |
| Finished | Oct 12 02:27:03 AM UTC 24 |
| Peak memory | 210140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637977735 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.3637977735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/46.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1323731998 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 3488976106 ps |
| CPU time | 15.83 seconds |
| Started | Oct 12 02:14:33 AM UTC 24 |
| Finished | Oct 12 02:14:50 AM UTC 24 |
| Peak memory | 220448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1323731998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 46.adc_ctrl_stress_all_with_rand_reset.1323731998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/46.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_alert_test.992399188 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 403768524 ps |
| CPU time | 1.7 seconds |
| Started | Oct 12 02:16:14 AM UTC 24 |
| Finished | Oct 12 02:16:17 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992399188 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.992399188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/47.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_clock_gating.296014802 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 516511952278 ps |
| CPU time | 301.79 seconds |
| Started | Oct 12 02:15:17 AM UTC 24 |
| Finished | Oct 12 02:20:22 AM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296014802 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gating.296014802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/47.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_both.73217127 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 498020213941 ps |
| CPU time | 1250.38 seconds |
| Started | Oct 12 02:15:24 AM UTC 24 |
| Finished | Oct 12 02:36:27 AM UTC 24 |
| Peak memory | 212980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73217127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_ SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.73217127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/47.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_interrupt.1549247785 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 163876305513 ps |
| CPU time | 127.92 seconds |
| Started | Oct 12 02:14:46 AM UTC 24 |
| Finished | Oct 12 02:16:57 AM UTC 24 |
| Peak memory | 210352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549247785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.1549247785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/47.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_interrupt_fixed.3915525517 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 166717053392 ps |
| CPU time | 106.74 seconds |
| Started | Oct 12 02:14:50 AM UTC 24 |
| Finished | Oct 12 02:16:39 AM UTC 24 |
| Peak memory | 210128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915525517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt_fixed.3915525517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/47.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_polled.2145091800 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 165478811089 ps |
| CPU time | 504.34 seconds |
| Started | Oct 12 02:14:42 AM UTC 24 |
| Finished | Oct 12 02:23:12 AM UTC 24 |
| Peak memory | 210128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145091800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2145091800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/47.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_polled_fixed.16304785 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 326655110774 ps |
| CPU time | 158.7 seconds |
| Started | Oct 12 02:14:45 AM UTC 24 |
| Finished | Oct 12 02:17:26 AM UTC 24 |
| Peak memory | 210328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16304785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas e_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixed.16304785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/47.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_wakeup.501302454 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 234113037272 ps |
| CPU time | 166.07 seconds |
| Started | Oct 12 02:14:52 AM UTC 24 |
| Finished | Oct 12 02:17:41 AM UTC 24 |
| Peak memory | 210060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501302454 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_wakeup.501302454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/47.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1681548232 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 589350691587 ps |
| CPU time | 1779.69 seconds |
| Started | Oct 12 02:15:02 AM UTC 24 |
| Finished | Oct 12 02:45:00 AM UTC 24 |
| Peak memory | 212772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681548232 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_wakeup_fixed.1681548232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/47.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_fsm_reset.1788293984 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 62722531640 ps |
| CPU time | 439.76 seconds |
| Started | Oct 12 02:16:00 AM UTC 24 |
| Finished | Oct 12 02:23:25 AM UTC 24 |
| Peak memory | 210560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788293984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.1788293984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/47.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_lowpower_counter.3117881207 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 24899203550 ps |
| CPU time | 26.51 seconds |
| Started | Oct 12 02:15:55 AM UTC 24 |
| Finished | Oct 12 02:16:23 AM UTC 24 |
| Peak memory | 209984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117881207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3117881207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/47.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_poweron_counter.2574998570 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 5492860199 ps |
| CPU time | 21.25 seconds |
| Started | Oct 12 02:15:32 AM UTC 24 |
| Finished | Oct 12 02:15:55 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574998570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.2574998570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/47.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_smoke.4257841967 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 5713089098 ps |
| CPU time | 12.16 seconds |
| Started | Oct 12 02:14:38 AM UTC 24 |
| Finished | Oct 12 02:14:51 AM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257841967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.4257841967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/47.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_stress_all.1257490993 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 188414288647 ps |
| CPU time | 163.4 seconds |
| Started | Oct 12 02:16:09 AM UTC 24 |
| Finished | Oct 12 02:18:55 AM UTC 24 |
| Peak memory | 210060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257490993 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.1257490993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/47.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2335398048 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 3747885620 ps |
| CPU time | 25.86 seconds |
| Started | Oct 12 02:16:00 AM UTC 24 |
| Finished | Oct 12 02:16:27 AM UTC 24 |
| Peak memory | 220644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2335398048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 47.adc_ctrl_stress_all_with_rand_reset.2335398048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/47.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_alert_test.1323447219 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 439587210 ps |
| CPU time | 1.7 seconds |
| Started | Oct 12 02:17:42 AM UTC 24 |
| Finished | Oct 12 02:17:45 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323447219 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1323447219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/48.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_clock_gating.2772235275 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 171095750458 ps |
| CPU time | 206.75 seconds |
| Started | Oct 12 02:16:47 AM UTC 24 |
| Finished | Oct 12 02:20:17 AM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772235275 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gating.2772235275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/48.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_both.2574435484 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 208220342669 ps |
| CPU time | 579.56 seconds |
| Started | Oct 12 02:16:57 AM UTC 24 |
| Finished | Oct 12 02:26:43 AM UTC 24 |
| Peak memory | 210376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574435484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2574435484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/48.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_interrupt.827746727 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 493010659765 ps |
| CPU time | 1156.1 seconds |
| Started | Oct 12 02:16:29 AM UTC 24 |
| Finished | Oct 12 02:35:57 AM UTC 24 |
| Peak memory | 212928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827746727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.827746727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/48.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_interrupt_fixed.21505153 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 491007927567 ps |
| CPU time | 286.9 seconds |
| Started | Oct 12 02:16:33 AM UTC 24 |
| Finished | Oct 12 02:21:23 AM UTC 24 |
| Peak memory | 210052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21505153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas e_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt_fixed.21505153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/48.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_polled.407044229 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 337201346075 ps |
| CPU time | 1040.15 seconds |
| Started | Oct 12 02:16:23 AM UTC 24 |
| Finished | Oct 12 02:33:55 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407044229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.407044229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/48.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_polled_fixed.2763118741 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 160015407240 ps |
| CPU time | 104.92 seconds |
| Started | Oct 12 02:16:27 AM UTC 24 |
| Finished | Oct 12 02:18:14 AM UTC 24 |
| Peak memory | 210400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763118741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixed.2763118741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/48.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_wakeup.3273630998 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 165177804282 ps |
| CPU time | 447.59 seconds |
| Started | Oct 12 02:16:34 AM UTC 24 |
| Finished | Oct 12 02:24:06 AM UTC 24 |
| Peak memory | 210140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273630998 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_wakeup.3273630998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/48.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3674157271 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 205468988668 ps |
| CPU time | 297.17 seconds |
| Started | Oct 12 02:16:40 AM UTC 24 |
| Finished | Oct 12 02:21:41 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674157271 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_wakeup_fixed.3674157271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/48.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_fsm_reset.3829672211 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 73264199718 ps |
| CPU time | 511.72 seconds |
| Started | Oct 12 02:17:27 AM UTC 24 |
| Finished | Oct 12 02:26:04 AM UTC 24 |
| Peak memory | 210480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829672211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3829672211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/48.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_lowpower_counter.246210574 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 47697954617 ps |
| CPU time | 191.64 seconds |
| Started | Oct 12 02:17:20 AM UTC 24 |
| Finished | Oct 12 02:20:35 AM UTC 24 |
| Peak memory | 210184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246210574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.246210574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/48.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_poweron_counter.2895231862 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 2734247926 ps |
| CPU time | 2.96 seconds |
| Started | Oct 12 02:17:15 AM UTC 24 |
| Finished | Oct 12 02:17:19 AM UTC 24 |
| Peak memory | 210060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895231862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2895231862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/48.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_smoke.1136037372 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 5587673686 ps |
| CPU time | 6.46 seconds |
| Started | Oct 12 02:16:18 AM UTC 24 |
| Finished | Oct 12 02:16:26 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136037372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1136037372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/48.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_stress_all.1878333572 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 632073030746 ps |
| CPU time | 838.73 seconds |
| Started | Oct 12 02:17:37 AM UTC 24 |
| Finished | Oct 12 02:31:46 AM UTC 24 |
| Peak memory | 210140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878333572 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.1878333572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/48.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.3542595171 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 16916917068 ps |
| CPU time | 20.28 seconds |
| Started | Oct 12 02:17:34 AM UTC 24 |
| Finished | Oct 12 02:17:56 AM UTC 24 |
| Peak memory | 220716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3542595171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 48.adc_ctrl_stress_all_with_rand_reset.3542595171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/48.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_alert_test.451523199 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 450299484 ps |
| CPU time | 2.7 seconds |
| Started | Oct 12 02:19:54 AM UTC 24 |
| Finished | Oct 12 02:19:58 AM UTC 24 |
| Peak memory | 210272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451523199 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.451523199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/49.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_clock_gating.3162323217 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 182735000388 ps |
| CPU time | 135.78 seconds |
| Started | Oct 12 02:18:56 AM UTC 24 |
| Finished | Oct 12 02:21:14 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162323217 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gating.3162323217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/49.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1319206503 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 163384273587 ps |
| CPU time | 479.06 seconds |
| Started | Oct 12 02:18:13 AM UTC 24 |
| Finished | Oct 12 02:26:18 AM UTC 24 |
| Peak memory | 210372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319206503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt_fixed.1319206503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/49.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_polled.1521569032 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 495018804173 ps |
| CPU time | 1107.6 seconds |
| Started | Oct 12 02:17:57 AM UTC 24 |
| Finished | Oct 12 02:36:36 AM UTC 24 |
| Peak memory | 212716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521569032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1521569032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/49.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_polled_fixed.666170652 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 163351211444 ps |
| CPU time | 509.76 seconds |
| Started | Oct 12 02:18:05 AM UTC 24 |
| Finished | Oct 12 02:26:41 AM UTC 24 |
| Peak memory | 210040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666170652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixed.666170652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/49.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1075296102 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 203088919147 ps |
| CPU time | 70.79 seconds |
| Started | Oct 12 02:18:47 AM UTC 24 |
| Finished | Oct 12 02:20:00 AM UTC 24 |
| Peak memory | 210120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075296102 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_wakeup_fixed.1075296102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/49.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_fsm_reset.1163604144 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 97428391688 ps |
| CPU time | 684.9 seconds |
| Started | Oct 12 02:19:29 AM UTC 24 |
| Finished | Oct 12 02:31:02 AM UTC 24 |
| Peak memory | 210740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163604144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.1163604144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/49.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_lowpower_counter.691128182 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 41762961985 ps |
| CPU time | 37.73 seconds |
| Started | Oct 12 02:19:23 AM UTC 24 |
| Finished | Oct 12 02:20:03 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691128182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.691128182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/49.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_poweron_counter.2324750621 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 3708055489 ps |
| CPU time | 15.88 seconds |
| Started | Oct 12 02:19:22 AM UTC 24 |
| Finished | Oct 12 02:19:40 AM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324750621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2324750621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/49.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_smoke.281550777 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 5715814886 ps |
| CPU time | 24.42 seconds |
| Started | Oct 12 02:17:47 AM UTC 24 |
| Finished | Oct 12 02:18:12 AM UTC 24 |
| Peak memory | 209984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281550777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.281550777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/49.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_stress_all.3330896537 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 167946294617 ps |
| CPU time | 293.06 seconds |
| Started | Oct 12 02:19:43 AM UTC 24 |
| Finished | Oct 12 02:24:40 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330896537 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.3330896537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/49.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.1624346608 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 5364418531 ps |
| CPU time | 11.59 seconds |
| Started | Oct 12 02:19:41 AM UTC 24 |
| Finished | Oct 12 02:19:53 AM UTC 24 |
| Peak memory | 220516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1624346608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 49.adc_ctrl_stress_all_with_rand_reset.1624346608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/49.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_alert_test.405010165 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 358481894 ps |
| CPU time | 1.25 seconds |
| Started | Oct 12 01:15:56 AM UTC 24 |
| Finished | Oct 12 01:15:58 AM UTC 24 |
| Peak memory | 208944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405010165 -assert nopostproc +UVM_TESTNAME=ad c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.405010165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/5.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_clock_gating.2812896835 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 393210779013 ps |
| CPU time | 361.6 seconds |
| Started | Oct 12 01:15:27 AM UTC 24 |
| Finished | Oct 12 01:21:33 AM UTC 24 |
| Peak memory | 210336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812896835 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gating.2812896835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/5.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_both.4190987306 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 434840024921 ps |
| CPU time | 1231.02 seconds |
| Started | Oct 12 01:15:28 AM UTC 24 |
| Finished | Oct 12 01:36:11 AM UTC 24 |
| Peak memory | 212872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190987306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.4190987306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/5.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt.4101661851 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 331031921963 ps |
| CPU time | 719.61 seconds |
| Started | Oct 12 01:15:18 AM UTC 24 |
| Finished | Oct 12 01:27:25 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101661851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.4101661851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/5.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt_fixed.66297871 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 494738280064 ps |
| CPU time | 368.8 seconds |
| Started | Oct 12 01:15:20 AM UTC 24 |
| Finished | Oct 12 01:21:33 AM UTC 24 |
| Peak memory | 210124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66297871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_bas e_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt_fixed.66297871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/5.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled.2388386453 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 326774589399 ps |
| CPU time | 181.52 seconds |
| Started | Oct 12 01:15:16 AM UTC 24 |
| Finished | Oct 12 01:18:21 AM UTC 24 |
| Peak memory | 210340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388386453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.2388386453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/5.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled_fixed.3206500323 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 328049916026 ps |
| CPU time | 844.96 seconds |
| Started | Oct 12 01:15:16 AM UTC 24 |
| Finished | Oct 12 01:29:30 AM UTC 24 |
| Peak memory | 210116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206500323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed.3206500323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/5.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup.1618361649 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 395948360742 ps |
| CPU time | 146.92 seconds |
| Started | Oct 12 01:15:23 AM UTC 24 |
| Finished | Oct 12 01:17:52 AM UTC 24 |
| Peak memory | 210264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618361649 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_wakeup.1618361649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/5.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup_fixed.169476370 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 200560455307 ps |
| CPU time | 220.6 seconds |
| Started | Oct 12 01:15:25 AM UTC 24 |
| Finished | Oct 12 01:19:08 AM UTC 24 |
| Peak memory | 210320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169476370 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_wakeup_fixed.169476370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/5.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_lowpower_counter.3913535957 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 36330465676 ps |
| CPU time | 72.11 seconds |
| Started | Oct 12 01:15:34 AM UTC 24 |
| Finished | Oct 12 01:16:48 AM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913535957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.3913535957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/5.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_poweron_counter.47748453 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 4738943894 ps |
| CPU time | 5.65 seconds |
| Started | Oct 12 01:15:30 AM UTC 24 |
| Finished | Oct 12 01:15:37 AM UTC 24 |
| Peak memory | 209976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47748453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_ SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.47748453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/5.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_smoke.814054302 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 5848689949 ps |
| CPU time | 12.47 seconds |
| Started | Oct 12 01:15:13 AM UTC 24 |
| Finished | Oct 12 01:15:27 AM UTC 24 |
| Peak memory | 210064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814054302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.814054302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/5.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_alert_test.3087239011 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 518978933 ps |
| CPU time | 1.22 seconds |
| Started | Oct 12 01:17:47 AM UTC 24 |
| Finished | Oct 12 01:17:50 AM UTC 24 |
| Peak memory | 208944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087239011 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.3087239011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/6.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_clock_gating.1406088001 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 180912592264 ps |
| CPU time | 145.7 seconds |
| Started | Oct 12 01:16:49 AM UTC 24 |
| Finished | Oct 12 01:19:17 AM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406088001 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gating.1406088001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/6.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt_fixed.2940970126 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 326874352815 ps |
| CPU time | 763.26 seconds |
| Started | Oct 12 01:16:28 AM UTC 24 |
| Finished | Oct 12 01:29:19 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940970126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt_fixed.2940970126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/6.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled.210155488 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 323567891494 ps |
| CPU time | 737.68 seconds |
| Started | Oct 12 01:15:59 AM UTC 24 |
| Finished | Oct 12 01:28:24 AM UTC 24 |
| Peak memory | 210140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210155488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.210155488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/6.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled_fixed.1202464651 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 165265677008 ps |
| CPU time | 394.03 seconds |
| Started | Oct 12 01:16:06 AM UTC 24 |
| Finished | Oct 12 01:22:45 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202464651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixed.1202464651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/6.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup.2896690027 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 186892704483 ps |
| CPU time | 588.89 seconds |
| Started | Oct 12 01:16:38 AM UTC 24 |
| Finished | Oct 12 01:26:34 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896690027 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_wakeup.2896690027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/6.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup_fixed.3476543805 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 195742039509 ps |
| CPU time | 123.14 seconds |
| Started | Oct 12 01:16:44 AM UTC 24 |
| Finished | Oct 12 01:18:49 AM UTC 24 |
| Peak memory | 210132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476543805 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_wakeup_fixed.3476543805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/6.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_fsm_reset.2196012494 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 111518420375 ps |
| CPU time | 1014.17 seconds |
| Started | Oct 12 01:17:27 AM UTC 24 |
| Finished | Oct 12 01:34:32 AM UTC 24 |
| Peak memory | 213060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196012494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.2196012494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/6.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_lowpower_counter.571677723 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 31157378871 ps |
| CPU time | 23.88 seconds |
| Started | Oct 12 01:17:19 AM UTC 24 |
| Finished | Oct 12 01:17:44 AM UTC 24 |
| Peak memory | 209996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571677723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.571677723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/6.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_poweron_counter.3321362239 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 4934020347 ps |
| CPU time | 2.17 seconds |
| Started | Oct 12 01:17:15 AM UTC 24 |
| Finished | Oct 12 01:17:18 AM UTC 24 |
| Peak memory | 209984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321362239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.3321362239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/6.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_smoke.537526762 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 5999780127 ps |
| CPU time | 7.71 seconds |
| Started | Oct 12 01:15:59 AM UTC 24 |
| Finished | Oct 12 01:16:08 AM UTC 24 |
| Peak memory | 210068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537526762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.537526762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/6.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all.1853352305 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 146482185384 ps |
| CPU time | 732.8 seconds |
| Started | Oct 12 01:17:45 AM UTC 24 |
| Finished | Oct 12 01:30:05 AM UTC 24 |
| Peak memory | 210632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853352305 -assert nopostproc +UVM_TESTNAM E=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.1853352305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/6.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3973115615 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 2861356732 ps |
| CPU time | 26.7 seconds |
| Started | Oct 12 01:17:37 AM UTC 24 |
| Finished | Oct 12 01:18:05 AM UTC 24 |
| Peak memory | 220308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3973115615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 6.adc_ctrl_stress_all_with_rand_reset.3973115615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/6.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_alert_test.1950931650 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 527044173 ps |
| CPU time | 1.39 seconds |
| Started | Oct 12 01:18:49 AM UTC 24 |
| Finished | Oct 12 01:18:52 AM UTC 24 |
| Peak memory | 208944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950931650 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.1950931650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/7.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_clock_gating.3317324467 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 158993049583 ps |
| CPU time | 361.15 seconds |
| Started | Oct 12 01:18:06 AM UTC 24 |
| Finished | Oct 12 01:24:11 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317324467 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gating.3317324467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/7.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_both.65489634 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 342433065810 ps |
| CPU time | 508.29 seconds |
| Started | Oct 12 01:18:09 AM UTC 24 |
| Finished | Oct 12 01:26:43 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65489634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_ SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.65489634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/7.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3181386611 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 494166891935 ps |
| CPU time | 395.95 seconds |
| Started | Oct 12 01:17:57 AM UTC 24 |
| Finished | Oct 12 01:24:37 AM UTC 24 |
| Peak memory | 210116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181386611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt_fixed.3181386611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/7.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled.85976762 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 495720250599 ps |
| CPU time | 1669.99 seconds |
| Started | Oct 12 01:17:50 AM UTC 24 |
| Finished | Oct 12 01:45:56 AM UTC 24 |
| Peak memory | 212704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85976762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_ SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.85976762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/7.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled_fixed.2477900913 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 488566073106 ps |
| CPU time | 1536.85 seconds |
| Started | Oct 12 01:17:51 AM UTC 24 |
| Finished | Oct 12 01:43:43 AM UTC 24 |
| Peak memory | 212792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477900913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed.2477900913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/7.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup.1302542119 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 347354621961 ps |
| CPU time | 537.7 seconds |
| Started | Oct 12 01:18:00 AM UTC 24 |
| Finished | Oct 12 01:27:03 AM UTC 24 |
| Peak memory | 210128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302542119 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_wakeup.1302542119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/7.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup_fixed.4079097676 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 599766622133 ps |
| CPU time | 642.39 seconds |
| Started | Oct 12 01:18:01 AM UTC 24 |
| Finished | Oct 12 01:28:50 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079097676 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_wakeup_fixed.4079097676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/7.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_fsm_reset.2695875592 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 99735399986 ps |
| CPU time | 522.03 seconds |
| Started | Oct 12 01:18:21 AM UTC 24 |
| Finished | Oct 12 01:27:09 AM UTC 24 |
| Peak memory | 210472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695875592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.2695875592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/7.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_lowpower_counter.1716956142 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 36487603270 ps |
| CPU time | 37.81 seconds |
| Started | Oct 12 01:18:17 AM UTC 24 |
| Finished | Oct 12 01:18:56 AM UTC 24 |
| Peak memory | 209992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716956142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.1716956142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/7.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_poweron_counter.827851086 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 4503916182 ps |
| CPU time | 4.87 seconds |
| Started | Oct 12 01:18:10 AM UTC 24 |
| Finished | Oct 12 01:18:16 AM UTC 24 |
| Peak memory | 209984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827851086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.827851086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/7.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_smoke.2804920397 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 5638186120 ps |
| CPU time | 7.88 seconds |
| Started | Oct 12 01:17:50 AM UTC 24 |
| Finished | Oct 12 01:17:59 AM UTC 24 |
| Peak memory | 210176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804920397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.2804920397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/7.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.4109610440 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 32737858715 ps |
| CPU time | 26.4 seconds |
| Started | Oct 12 01:18:27 AM UTC 24 |
| Finished | Oct 12 01:18:55 AM UTC 24 |
| Peak memory | 220432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4109610440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 7.adc_ctrl_stress_all_with_rand_reset.4109610440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_alert_test.4281960804 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 502804152 ps |
| CPU time | 1.82 seconds |
| Started | Oct 12 01:21:05 AM UTC 24 |
| Finished | Oct 12 01:21:08 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281960804 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.4281960804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/8.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt.1191159381 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 328392034524 ps |
| CPU time | 923.62 seconds |
| Started | Oct 12 01:18:57 AM UTC 24 |
| Finished | Oct 12 01:34:30 AM UTC 24 |
| Peak memory | 212800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191159381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1191159381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/8.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt_fixed.424782979 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 491057605385 ps |
| CPU time | 862.11 seconds |
| Started | Oct 12 01:19:01 AM UTC 24 |
| Finished | Oct 12 01:33:31 AM UTC 24 |
| Peak memory | 210120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424782979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_ba se_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt_fixed.424782979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/8.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled.2622037028 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 163413345296 ps |
| CPU time | 327.7 seconds |
| Started | Oct 12 01:18:56 AM UTC 24 |
| Finished | Oct 12 01:24:28 AM UTC 24 |
| Peak memory | 210060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622037028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2622037028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/8.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled_fixed.3521377567 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 493400186295 ps |
| CPU time | 394.44 seconds |
| Started | Oct 12 01:18:56 AM UTC 24 |
| Finished | Oct 12 01:25:34 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521377567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed.3521377567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/8.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup.1204931655 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 361701355352 ps |
| CPU time | 227.88 seconds |
| Started | Oct 12 01:19:09 AM UTC 24 |
| Finished | Oct 12 01:23:00 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204931655 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_wakeup.1204931655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/8.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup_fixed.2280962295 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 412827121663 ps |
| CPU time | 345.28 seconds |
| Started | Oct 12 01:19:18 AM UTC 24 |
| Finished | Oct 12 01:25:08 AM UTC 24 |
| Peak memory | 210064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280962295 -assert nopostp roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_wakeup_fixed.2280962295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/8.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_fsm_reset.3102152596 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 120104551057 ps |
| CPU time | 648.78 seconds |
| Started | Oct 12 01:20:29 AM UTC 24 |
| Finished | Oct 12 01:31:24 AM UTC 24 |
| Peak memory | 210692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102152596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.3102152596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/8.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_lowpower_counter.693559083 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 28532708974 ps |
| CPU time | 65.16 seconds |
| Started | Oct 12 01:20:29 AM UTC 24 |
| Finished | Oct 12 01:21:36 AM UTC 24 |
| Peak memory | 210260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693559083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.693559083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/8.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_poweron_counter.4078867978 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 2809226810 ps |
| CPU time | 2.98 seconds |
| Started | Oct 12 01:20:24 AM UTC 24 |
| Finished | Oct 12 01:20:28 AM UTC 24 |
| Peak memory | 210064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078867978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.4078867978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/8.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_smoke.1550811286 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 5750361320 ps |
| CPU time | 6.73 seconds |
| Started | Oct 12 01:18:52 AM UTC 24 |
| Finished | Oct 12 01:19:00 AM UTC 24 |
| Peak memory | 209984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550811286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1550811286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/8.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all.372169891 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 201595157684 ps |
| CPU time | 462.34 seconds |
| Started | Oct 12 01:21:03 AM UTC 24 |
| Finished | Oct 12 01:28:52 AM UTC 24 |
| Peak memory | 210128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372169891 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.372169891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/8.adc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.605844828 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1694544904 ps |
| CPU time | 8.29 seconds |
| Started | Oct 12 01:20:55 AM UTC 24 |
| Finished | Oct 12 01:21:05 AM UTC 24 |
| Peak memory | 210028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=605844828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.605844828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/8.adc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_alert_test.1981999912 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 314064147 ps |
| CPU time | 1.66 seconds |
| Started | Oct 12 01:22:53 AM UTC 24 |
| Finished | Oct 12 01:22:55 AM UTC 24 |
| Peak memory | 208764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981999912 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1981999912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/9.adc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_clock_gating.741181204 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 332444506086 ps |
| CPU time | 437.47 seconds |
| Started | Oct 12 01:22:28 AM UTC 24 |
| Finished | Oct 12 01:29:51 AM UTC 24 |
| Peak memory | 210452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741181204 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gating.741181204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/9.adc_ctrl_clock_gating/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_both.727610609 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 334022523030 ps |
| CPU time | 460.19 seconds |
| Started | Oct 12 01:22:31 AM UTC 24 |
| Finished | Oct 12 01:30:16 AM UTC 24 |
| Peak memory | 210328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727610609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST _SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.727610609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/9.adc_ctrl_filters_both/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt.1608674596 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 166274065884 ps |
| CPU time | 425.7 seconds |
| Started | Oct 12 01:21:34 AM UTC 24 |
| Finished | Oct 12 01:28:44 AM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608674596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.1608674596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/9.adc_ctrl_filters_interrupt/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt_fixed.1208243113 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 165722658562 ps |
| CPU time | 445.33 seconds |
| Started | Oct 12 01:21:34 AM UTC 24 |
| Finished | Oct 12 01:29:04 AM UTC 24 |
| Peak memory | 210064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208243113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt_fixed.1208243113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/9.adc_ctrl_filters_interrupt_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled.2156145978 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 493079341995 ps |
| CPU time | 794.31 seconds |
| Started | Oct 12 01:21:15 AM UTC 24 |
| Finished | Oct 12 01:34:37 AM UTC 24 |
| Peak memory | 212788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156145978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2156145978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/9.adc_ctrl_filters_polled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled_fixed.1998643098 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 166096377210 ps |
| CPU time | 521.88 seconds |
| Started | Oct 12 01:21:23 AM UTC 24 |
| Finished | Oct 12 01:30:10 AM UTC 24 |
| Peak memory | 210064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998643098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_b ase_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed.1998643098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/9.adc_ctrl_filters_polled_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup.1061764079 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 176512401046 ps |
| CPU time | 59.43 seconds |
| Started | Oct 12 01:21:37 AM UTC 24 |
| Finished | Oct 12 01:22:38 AM UTC 24 |
| Peak memory | 210060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061764079 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_wakeup.1061764079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/9.adc_ctrl_filters_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup_fixed.999229754 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 208087893930 ps |
| CPU time | 90.55 seconds |
| Started | Oct 12 01:22:03 AM UTC 24 |
| Finished | Oct 12 01:23:35 AM UTC 24 |
| Peak memory | 210340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999229754 -assert nopostpr oc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_wakeup_fixed.999229754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/9.adc_ctrl_filters_wakeup_fixed/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.4279190096 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 129493155637 ps |
| CPU time | 467.98 seconds |
| Started | Oct 12 01:22:46 AM UTC 24 |
| Finished | Oct 12 01:30:39 AM UTC 24 |
| Peak memory | 210544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279190096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.4279190096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/9.adc_ctrl_fsm_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_lowpower_counter.1098009390 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 42845706605 ps |
| CPU time | 20.78 seconds |
| Started | Oct 12 01:22:38 AM UTC 24 |
| Finished | Oct 12 01:23:00 AM UTC 24 |
| Peak memory | 209988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098009390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.1098009390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/9.adc_ctrl_lowpower_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_poweron_counter.3742056455 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 3377759810 ps |
| CPU time | 14.16 seconds |
| Started | Oct 12 01:22:33 AM UTC 24 |
| Finished | Oct 12 01:22:49 AM UTC 24 |
| Peak memory | 209992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742056455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.3742056455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/9.adc_ctrl_poweron_counter/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_smoke.2176041084 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 5939956343 ps |
| CPU time | 3.24 seconds |
| Started | Oct 12 01:21:09 AM UTC 24 |
| Finished | Oct 12 01:21:14 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176041084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TES T_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.2176041084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/9.adc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.4252586873 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 15266320093 ps |
| CPU time | 37.65 seconds |
| Started | Oct 12 01:22:47 AM UTC 24 |
| Finished | Oct 12 01:23:26 AM UTC 24 |
| Peak memory | 220768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4252586873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 9.adc_ctrl_stress_all_with_rand_reset.4252586873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all_with_rand_reset/latest |
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