Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1189906	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1165252

1

T1

8

T2

66

T3

56

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2078139	1			T1	1		T2	81		T3	81
values[0x0]	138183	1			T1	8		T2	40		T3	30
values[0x1]	138836	1			T1	13		T2	23		T3	33

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	953391	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1401767

1

T1

11

T2

77

T3

70

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7185	1			T2	1		T3	1		T6	3
valid_sources[0x01]	11591	1			T2	1		T9	2		T13	2
valid_sources[0x02]	7168	1			T4	50		T8	1		T10	3
valid_sources[0x03]	7517	1			T10	2		T16	2		T17	3
valid_sources[0x04]	8252	1			T3	1		T8	1		T16	7
valid_sources[0x05]	7627	1			T10	2		T13	3		T16	3
valid_sources[0x06]	7287	1			T2	2		T10	17		T11	1
valid_sources[0x07]	7409	1			T3	1		T7	1		T9	1
valid_sources[0x08]	9993	1			T2	1		T12	1		T25	1
valid_sources[0x09]	7357	1			T3	1		T10	4		T15	3
valid_sources[0x0a]	7249	1			T2	1		T3	1		T7	1
valid_sources[0x0b]	10046	1			T2	1		T8	1		T10	1
valid_sources[0x0c]	15235	1			T3	2		T13	2		T17	3
valid_sources[0x0d]	11307	1			T2	1		T7	3		T10	2
valid_sources[0x0e]	7093	1			T3	1		T10	1		T25	1
valid_sources[0x0f]	7174	1			T3	2		T10	1		T13	1
valid_sources[0x10]	12602	1			T3	1		T10	3		T26	1
valid_sources[0x11]	7302	1			T9	3		T10	6		T25	1
valid_sources[0x12]	7089	1			T2	1		T9	2		T10	3
valid_sources[0x13]	7613	1			T10	1		T25	3		T26	12
valid_sources[0x14]	7494	1			T2	1		T3	3		T9	2
valid_sources[0x15]	7658	1			T2	1		T3	1		T6	1
valid_sources[0x16]	9996	1			T2	1		T9	1		T10	1
valid_sources[0x17]	7911	1			T10	8		T26	2		T16	1
valid_sources[0x18]	7567	1			T2	1		T3	1		T4	12
valid_sources[0x19]	7821	1			T2	2		T9	1		T10	1
valid_sources[0x1a]	8730	1			T3	1		T9	1		T10	3
valid_sources[0x1b]	7563	1			T2	1		T3	1		T8	1
valid_sources[0x1c]	9672	1			T2	1		T3	1		T5	11
valid_sources[0x1d]	9903	1			T2	1		T3	1		T10	2
valid_sources[0x1e]	12443	1			T9	2		T10	1		T23	1
valid_sources[0x1f]	15061	1			T2	1		T3	1		T9	2
valid_sources[0x20]	7585	1			T3	1		T9	3		T11	4
valid_sources[0x21]	7281	1			T2	1		T3	1		T10	1
valid_sources[0x22]	7130	1			T2	1		T3	1		T21	1
valid_sources[0x23]	11789	1			T2	1		T10	1		T13	2
valid_sources[0x24]	7483	1			T8	2		T10	1		T13	2
valid_sources[0x25]	11687	1			T10	1		T25	1		T13	1
valid_sources[0x26]	8936	1			T2	1		T10	1		T13	2
valid_sources[0x27]	11307	1			T2	1		T9	1		T10	1
valid_sources[0x28]	7585	1			T2	1		T10	3		T13	3
valid_sources[0x29]	7151	1			T2	1		T10	1		T13	2
valid_sources[0x2a]	7402	1			T3	2		T41	1		T16	5
valid_sources[0x2b]	12598	1			T10	2		T13	1		T16	4
valid_sources[0x2c]	9238	1			T10	1		T13	1		T16	3
valid_sources[0x2d]	8453	1			T16	3		T119	1		T17	4
valid_sources[0x2e]	15883	1			T3	1		T21	2		T10	2
valid_sources[0x2f]	9359	1			T2	1		T9	2		T10	1
valid_sources[0x30]	11061	1			T8	1		T9	3		T10	3
valid_sources[0x31]	7208	1			T2	1		T9	2		T10	1
valid_sources[0x32]	11507	1			T10	2		T11	1		T13	1
valid_sources[0x33]	7251	1			T6	2		T9	1		T10	3
valid_sources[0x34]	12895	1			T1	13		T2	1		T9	1
valid_sources[0x35]	7573	1			T3	1		T8	1		T9	1
valid_sources[0x36]	7411	1			T10	2		T25	2		T13	1
valid_sources[0x37]	7425	1			T2	1		T10	5		T16	5
valid_sources[0x38]	6859	1			T9	2		T10	5		T25	1
valid_sources[0x39]	7388	1			T2	1		T3	1		T9	1
valid_sources[0x3a]	9835	1			T2	1		T10	3		T12	3
valid_sources[0x3b]	8194	1			T2	1		T10	2		T25	1
valid_sources[0x3c]	12936	1			T2	1		T10	2		T13	2
valid_sources[0x3d]	7034	1			T2	2		T3	1		T9	1
valid_sources[0x3e]	11688	1			T2	1		T3	1		T9	1
valid_sources[0x3f]	8601	1			T2	2		T3	1		T10	3
valid_sources[0x40]	7640	1			T21	1		T10	3		T25	1
valid_sources[0x41]	11489	1			T2	2		T10	2		T25	1
valid_sources[0x42]	7690	1			T3	1		T10	1		T11	1
valid_sources[0x43]	7494	1			T10	1		T25	1		T13	2
valid_sources[0x44]	9908	1			T2	1		T3	1		T9	1
valid_sources[0x45]	7570	1			T2	1		T3	1		T13	4
valid_sources[0x46]	7516	1			T2	1		T3	1		T10	4
valid_sources[0x47]	7104	1			T3	2		T5	2		T10	1
valid_sources[0x48]	12079	1			T3	2		T26	3		T16	1
valid_sources[0x49]	11461	1			T2	2		T3	1		T10	19
valid_sources[0x4a]	7360	1			T2	4		T3	1		T10	1
valid_sources[0x4b]	7392	1			T2	1		T9	2		T13	1
valid_sources[0x4c]	7621	1			T3	1		T9	1		T10	1
valid_sources[0x4d]	7251	1			T2	1		T10	2		T13	1
valid_sources[0x4e]	11088	1			T2	1		T3	1		T10	1
valid_sources[0x4f]	8334	1			T2	1		T9	1		T10	3
valid_sources[0x50]	23353	1			T10	2		T25	1		T13	2
valid_sources[0x51]	12699	1			T9	1		T10	3		T13	1
valid_sources[0x52]	7502	1			T3	1		T9	1		T10	2
valid_sources[0x53]	11950	1			T7	1		T10	2		T13	1
valid_sources[0x54]	9259	1			T10	1		T16	2		T99	1
valid_sources[0x55]	8443	1			T1	1		T2	1		T4	1
valid_sources[0x56]	7664	1			T9	1		T10	3		T25	1
valid_sources[0x57]	14603	1			T2	1		T9	3		T10	5
valid_sources[0x58]	6771	1			T13	4		T16	1		T119	1
valid_sources[0x59]	10244	1			T10	7		T16	6		T18	31
valid_sources[0x5a]	10181	1			T2	1		T3	1		T10	2
valid_sources[0x5b]	9329	1			T3	2		T7	1		T13	3
valid_sources[0x5c]	7808	1			T10	2		T13	2		T16	2
valid_sources[0x5d]	7542	1			T9	1		T10	2		T13	1
valid_sources[0x5e]	8227	1			T2	1		T3	1		T9	1
valid_sources[0x5f]	10004	1			T2	1		T9	1		T10	2
valid_sources[0x60]	7430	1			T13	2		T41	1		T16	1
valid_sources[0x61]	7367	1			T3	1		T9	3		T10	2
valid_sources[0x62]	7045	1			T10	2		T13	2		T40	2
valid_sources[0x63]	7203	1			T3	1		T5	9		T7	2
valid_sources[0x64]	8000	1			T26	9		T13	2		T16	8
valid_sources[0x65]	12659	1			T2	1		T10	2		T26	12
valid_sources[0x66]	11550	1			T2	2		T10	1		T11	1
valid_sources[0x67]	7446	1			T2	1		T10	1		T16	3
valid_sources[0x68]	11291	1			T2	2		T10	3		T11	1
valid_sources[0x69]	6795	1			T3	1		T4	13		T7	1
valid_sources[0x6a]	8931	1			T3	1		T6	3		T11	1
valid_sources[0x6b]	7740	1			T2	1		T25	1		T13	2
valid_sources[0x6c]	7543	1			T10	3		T11	1		T13	2
valid_sources[0x6d]	10337	1			T9	2		T16	3		T119	2
valid_sources[0x6e]	7340	1			T2	2		T3	3		T16	4
valid_sources[0x6f]	11241	1			T3	1		T9	1		T10	17
valid_sources[0x70]	7811	1			T9	1		T10	10		T16	2
valid_sources[0x71]	8136	1			T2	1		T7	3		T10	5
valid_sources[0x72]	8306	1			T2	1		T3	1		T10	3
valid_sources[0x73]	11325	1			T3	2		T10	1		T25	1
valid_sources[0x74]	7239	1			T2	1		T8	2		T9	1
valid_sources[0x75]	7455	1			T1	7		T2	2		T3	1
valid_sources[0x76]	10106	1			T8	2		T11	1		T26	1
valid_sources[0x77]	7242	1			T6	1		T9	1		T26	19
valid_sources[0x78]	11767	1			T3	3		T10	1		T13	1
valid_sources[0x79]	8690	1			T3	1		T6	7		T7	1
valid_sources[0x7a]	7491	1			T2	1		T8	1		T10	1
valid_sources[0x7b]	7394	1			T10	1		T13	4		T16	5
valid_sources[0x7c]	16149	1			T3	2		T10	3		T13	4
valid_sources[0x7d]	6928	1			T2	1		T21	1		T9	2
valid_sources[0x7e]	7264	1			T1	1		T2	1		T3	1
valid_sources[0x7f]	8269	1			T7	1		T10	5		T26	6
valid_sources[0x80]	7426	1			T8	1		T9	1		T10	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1035491

1

T1

1

T2

43

T3

42

values[0x0]

all_enables

biggest_size

75300

1

T1

3

T2

18

T3

9

values[0x1]

all_enables

biggest_size

54461

1

T1

4

T2

5

T3

5