Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1165711	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1141358

1

T1

4

T2

72

T3

59

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2020437	1			T1	1		T2	81		T3	81
values[0x0]	143333	1			T1	11		T2	37		T3	32
values[0x1]	143299	1			T1	6		T2	26		T3	31

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	933969	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1373100

1

T1

5

T2

82

T3

67

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9127	1			T9	15		T12	23		T14	10
valid_sources[0x01]	16756	1			T5	2		T9	26		T12	28
valid_sources[0x02]	11980	1			T9	2		T12	12		T13	6
valid_sources[0x03]	7346	1			T9	19		T12	20		T58	1
valid_sources[0x04]	9356	1			T9	12		T12	18		T14	14
valid_sources[0x05]	8074	1			T2	1		T9	23		T12	19
valid_sources[0x06]	6777	1			T9	14		T12	23		T28	1
valid_sources[0x07]	7097	1			T8	7		T9	3		T12	16
valid_sources[0x08]	13819	1			T2	1		T21	1		T9	3
valid_sources[0x09]	8771	1			T2	2		T5	2		T6	1
valid_sources[0x0a]	7335	1			T4	4		T9	16		T12	18
valid_sources[0x0b]	7080	1			T9	23		T12	17		T13	29
valid_sources[0x0c]	7038	1			T2	2		T9	15		T12	21
valid_sources[0x0d]	7228	1			T9	8		T12	18		T14	12
valid_sources[0x0e]	7247	1			T9	13		T12	26		T13	1
valid_sources[0x0f]	9294	1			T2	3		T5	1		T9	91
valid_sources[0x10]	6732	1			T9	13		T12	21		T14	21
valid_sources[0x11]	7651	1			T12	16		T58	1		T14	9
valid_sources[0x12]	11399	1			T9	19		T11	16		T12	24
valid_sources[0x13]	6807	1			T9	14		T12	28		T13	4
valid_sources[0x14]	7029	1			T2	1		T9	3		T12	13
valid_sources[0x15]	15434	1			T2	1		T9	2		T12	24
valid_sources[0x16]	6679	1			T2	1		T9	11		T12	23
valid_sources[0x17]	8153	1			T54	1		T9	23		T12	20
valid_sources[0x18]	9794	1			T3	144		T5	1		T9	3
valid_sources[0x19]	8231	1			T2	1		T24	1		T12	15
valid_sources[0x1a]	7766	1			T12	24		T28	2		T14	18
valid_sources[0x1b]	7090	1			T9	11		T12	24		T14	18
valid_sources[0x1c]	6761	1			T2	3		T9	25		T12	25
valid_sources[0x1d]	11781	1			T9	22		T12	20		T28	1
valid_sources[0x1e]	15117	1			T9	39		T12	37		T28	1
valid_sources[0x1f]	6851	1			T2	2		T54	1		T12	28
valid_sources[0x20]	7047	1			T9	11		T12	18		T28	1
valid_sources[0x21]	8681	1			T2	1		T9	8		T12	28
valid_sources[0x22]	8726	1			T2	2		T6	6		T21	1
valid_sources[0x23]	13056	1			T5	1		T9	2		T24	1
valid_sources[0x24]	10486	1			T2	3		T5	1		T9	20
valid_sources[0x25]	6727	1			T9	8		T12	24		T14	15
valid_sources[0x26]	6835	1			T2	1		T9	22		T11	4
valid_sources[0x27]	12913	1			T4	1		T9	7		T12	18
valid_sources[0x28]	6646	1			T21	1		T9	25		T12	27
valid_sources[0x29]	11210	1			T2	2		T9	16		T12	22
valid_sources[0x2a]	7603	1			T24	1		T12	20		T28	2
valid_sources[0x2b]	6592	1			T9	18		T12	33		T14	18
valid_sources[0x2c]	16576	1			T9	44		T12	28		T14	10
valid_sources[0x2d]	17170	1			T54	4		T9	23		T12	22
valid_sources[0x2e]	13980	1			T9	22		T12	20		T13	2
valid_sources[0x2f]	6642	1			T2	2		T9	19		T12	27
valid_sources[0x30]	7908	1			T2	1		T9	27		T12	25
valid_sources[0x31]	6728	1			T9	6		T12	20		T28	2
valid_sources[0x32]	6684	1			T9	11		T12	16		T28	1
valid_sources[0x33]	10900	1			T9	8		T10	1		T12	24
valid_sources[0x34]	7006	1			T4	2		T9	14		T12	26
valid_sources[0x35]	7009	1			T9	19		T12	17		T14	23
valid_sources[0x36]	6651	1			T2	1		T12	28		T14	15
valid_sources[0x37]	6631	1			T4	4		T8	9		T9	16
valid_sources[0x38]	8998	1			T9	16		T12	22		T14	25
valid_sources[0x39]	8697	1			T9	11		T12	23		T13	6
valid_sources[0x3a]	6928	1			T9	23		T24	1		T12	22
valid_sources[0x3b]	6848	1			T9	20		T12	19		T14	16
valid_sources[0x3c]	6654	1			T8	4		T9	4		T24	1
valid_sources[0x3d]	7125	1			T2	1		T12	15		T14	17
valid_sources[0x3e]	11806	1			T2	1		T9	19		T11	2
valid_sources[0x3f]	11206	1			T2	1		T4	4		T9	36
valid_sources[0x40]	6688	1			T9	9		T12	10		T28	3
valid_sources[0x41]	10537	1			T4	1		T9	29		T12	19
valid_sources[0x42]	11067	1			T9	6		T12	18		T58	1
valid_sources[0x43]	19650	1			T2	4		T9	33		T12	25
valid_sources[0x44]	12111	1			T2	1		T9	11		T12	23
valid_sources[0x45]	13143	1			T4	1		T9	39		T12	25
valid_sources[0x46]	11955	1			T5	2		T9	11		T24	3
valid_sources[0x47]	12173	1			T6	1		T24	3		T12	14
valid_sources[0x48]	24767	1			T9	39		T12	19		T14	19
valid_sources[0x49]	6599	1			T6	9		T12	17		T14	12
valid_sources[0x4a]	6628	1			T2	2		T9	9		T12	24
valid_sources[0x4b]	15008	1			T4	3		T9	8		T11	10
valid_sources[0x4c]	6514	1			T4	3		T9	34		T12	21
valid_sources[0x4d]	8485	1			T2	3		T9	19		T12	14
valid_sources[0x4e]	7701	1			T12	25		T13	12		T14	17
valid_sources[0x4f]	6805	1			T12	22		T27	3		T14	10
valid_sources[0x50]	11644	1			T9	3		T12	22		T28	3
valid_sources[0x51]	6790	1			T8	5		T12	27		T14	11
valid_sources[0x52]	9354	1			T9	21		T24	3		T12	18
valid_sources[0x53]	8027	1			T6	3		T21	1		T9	29
valid_sources[0x54]	7499	1			T9	23		T12	19		T28	1
valid_sources[0x55]	11092	1			T21	1		T9	6		T12	25
valid_sources[0x56]	10701	1			T2	1		T21	2		T9	39
valid_sources[0x57]	15093	1			T2	2		T4	1		T9	10
valid_sources[0x58]	6998	1			T2	2		T8	1		T9	32
valid_sources[0x59]	14041	1			T2	1		T4	1		T9	24
valid_sources[0x5a]	6850	1			T9	18		T10	11		T12	20
valid_sources[0x5b]	12833	1			T2	5		T9	18		T12	19
valid_sources[0x5c]	9535	1			T2	2		T21	1		T23	3
valid_sources[0x5d]	6680	1			T2	1		T9	11		T12	18
valid_sources[0x5e]	7016	1			T2	4		T5	1		T22	1
valid_sources[0x5f]	12300	1			T2	1		T9	9		T12	24
valid_sources[0x60]	10732	1			T4	3		T9	30		T12	20
valid_sources[0x61]	6564	1			T2	1		T9	48		T12	19
valid_sources[0x62]	11115	1			T9	1		T12	17		T13	5
valid_sources[0x63]	9549	1			T2	1		T9	7		T12	14
valid_sources[0x64]	6769	1			T2	1		T12	20		T14	14
valid_sources[0x65]	15681	1			T2	2		T9	30		T12	26
valid_sources[0x66]	6700	1			T9	29		T12	25		T14	22
valid_sources[0x67]	7540	1			T2	4		T9	8		T12	22
valid_sources[0x68]	7303	1			T12	21		T14	20		T15	8
valid_sources[0x69]	10937	1			T4	1		T9	1		T12	30
valid_sources[0x6a]	10597	1			T9	27		T12	22		T13	4
valid_sources[0x6b]	11574	1			T21	1		T9	52		T12	23
valid_sources[0x6c]	10955	1			T12	23		T14	21		T15	31
valid_sources[0x6d]	12120	1			T9	40		T12	13		T14	27
valid_sources[0x6e]	20546	1			T9	11		T12	20		T13	11
valid_sources[0x6f]	15692	1			T9	27		T12	23		T28	1
valid_sources[0x70]	7587	1			T7	8		T12	17		T13	1
valid_sources[0x71]	6414	1			T10	2		T12	24		T13	19
valid_sources[0x72]	8308	1			T5	1		T7	31		T54	2
valid_sources[0x73]	7863	1			T9	2		T12	20		T58	2
valid_sources[0x74]	11537	1			T9	16		T12	20		T28	1
valid_sources[0x75]	7039	1			T9	23		T12	26		T28	2
valid_sources[0x76]	6786	1			T9	23		T12	24		T14	16
valid_sources[0x77]	6792	1			T9	30		T12	29		T28	2
valid_sources[0x78]	7341	1			T9	1		T10	12		T12	30
valid_sources[0x79]	9488	1			T2	1		T9	10		T11	4
valid_sources[0x7a]	7935	1			T2	1		T9	14		T24	4
valid_sources[0x7b]	15199	1			T2	1		T21	1		T12	15
valid_sources[0x7c]	6855	1			T54	1		T9	1		T12	19
valid_sources[0x7d]	10483	1			T9	8		T12	24		T13	2
valid_sources[0x7e]	7804	1			T12	18		T14	18		T15	21
valid_sources[0x7f]	6800	1			T7	5		T9	11		T12	32
valid_sources[0x80]	6906	1			T2	2		T5	1		T12	23

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1007320

1

T2

51

T3

41

T21

1

values[0x0]

all_enables

biggest_size

77925

1

T1

4

T2

18

T3

10

values[0x1]

all_enables

biggest_size

56113

1

T2

3

T3

8

T4

13