Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
84.44	84.44	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	84.44	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	7	38	84.44

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	6	10	62.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	26780	1			T11	9		T14	6		T16	7
auto[PWRUP]	95	1			T52	1		T50	1		T47	1
auto[ONEST_0]	65	1			T52	1		T47	2		T51	2
auto[ONEST_021]	17	1			T51	1		T200	2		T49	1
auto[ONEST_1]	68	1			T52	2		T50	2		T47	1
auto[ONEST_DONE]	5	1			T219	1		T220	1		T221	1
auto[LP_0]	127	1			T52	4		T50	1		T47	4
auto[LP_021]	34	1			T51	1		T222	1		T54	2
auto[LP_1]	113	1			T52	1		T50	2		T47	1
auto[LP_EVAL]	50	1			T47	1		T53	1		T200	1
auto[LP_SLP]	416	1			T52	5		T50	2		T47	7
auto[LP_PWRUP]	17	1			T53	1		T223	1		T222	1
auto[NP_0]	140	1			T52	3		T51	1		T53	2
auto[NP_021]	29	1			T52	1		T50	1		T79	1
auto[NP_1]	133	1			T52	1		T50	3		T47	3
auto[NP_EVAL]	26	1			T54	1		T224	2		T225	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

4

1

T53

1

T221

1

T226

1

min

26345

1

T11

9

T14

6

T16

7

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	26349	1			T11	9		T14	6		T16	7
pow[0x1]	6	1			T227	1		T225	1		T228	1
pow[0x2]	18	1			T49	1		T227	2		T225	1
pow[0x3]	33	1			T47	2		T79	1		T51	1
pow[0x4]	53	1			T50	1		T47	1		T79	1
pow[0x5]	105	1			T52	1		T50	1		T47	1
pow[0x6]	217	1			T52	1		T50	1		T47	4
pow[0x7]	454	1			T52	8		T50	5		T47	6

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

144

1

T52

2

T50

2

T79

2

min

25957

1

T11

9

T14

6

T16

7

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	6	10	62.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	25957	1			T11	9		T14	6		T16	7
pow[0x7]	1	1			T221	1		-	-		-	-
pow[0x8]	2	1			T54	1		T229	1		-	-
pow[0x9]	6	1			T230	1		T231	1		T229	1
pow[0xa]	13	1			T51	1		T232	1		T224	1
pow[0xb]	34	1			T48	2		T54	1		T233	1
pow[0xc]	79	1			T52	2		T50	1		T53	1
pow[0xd]	102	1			T52	1		T50	1		T47	2
pow[0xe]	254	1			T52	1		T50	1		T47	4
pow[0xf]	513	1			T52	4		T50	5		T47	9