Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
91.11 91.11 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
adc_ctrl_fsm_reset_cg_inst 91.11 1 100 1 64 64



Group Instance : adc_ctrl_fsm_reset_cg_inst
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
91.11 1 100 1 64 64



Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 45 4 41 91.11


Variables for Group Instance adc_ctrl_fsm_reset_cg_inst
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
fsm_state_cp 17 1 16 94.12 100 1 1 0
lp_sample_cnt_min_max_cp 2 0 2 100.00 100 1 1 0
lp_sample_cnt_pow_cp 8 0 8 100.00 100 1 1 0
np_sample_cnt_min_max_cp 2 0 2 100.00 100 1 1 0
np_sample_cnt_pow_cp 16 3 13 81.25 100 1 1 0


Summary for Variable fsm_state_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 17 1 16 94.12


Automatically Generated Bins for fsm_state_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[NP_DONE] 0 1 1


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[PWRDN] 28170 1 T9 5 T12 24 T13 10
auto[PWRUP] 98 1 T62 3 T59 1 T60 2
auto[ONEST_0] 64 1 T62 1 T59 2 T61 3
auto[ONEST_021] 16 1 T59 2 T161 1 T205 1
auto[ONEST_1] 70 1 T59 1 T60 1 T102 1
auto[ONEST_DONE] 2 1 T59 1 T206 1 - -
auto[LP_0] 106 1 T62 3 T59 2 T60 1
auto[LP_021] 24 1 T61 1 T207 1 T185 3
auto[LP_1] 110 1 T59 1 T60 1 T102 1
auto[LP_EVAL] 70 1 T59 1 T60 1 T102 1
auto[LP_SLP] 465 1 T62 4 T59 4 T60 6
auto[LP_PWRUP] 27 1 T62 1 T60 2 T63 1
auto[NP_0] 138 1 T62 2 T59 1 T60 1
auto[NP_021] 39 1 T30 1 T206 1 T61 1
auto[NP_1] 130 1 T30 1 T62 1 T59 1
auto[NP_EVAL] 27 1 T62 1 T206 1 T61 1


Summary for Variable lp_sample_cnt_min_max_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for lp_sample_cnt_min_max_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
max 8 1 T161 1 T205 1 T208 1
min 27624 1 T9 5 T12 24 T13 10


Summary for Variable lp_sample_cnt_pow_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for lp_sample_cnt_pow_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
pow[0x0] 27630 1 T9 5 T12 24 T13 10
pow[0x1] 9 1 T206 1 T175 1 T209 1
pow[0x2] 14 1 T210 1 T206 1 T61 1
pow[0x3] 32 1 T59 1 T60 1 T210 1
pow[0x4] 58 1 T59 1 T60 1 T63 1
pow[0x5] 129 1 T62 2 T59 1 T60 2
pow[0x6] 269 1 T59 4 T60 2 T102 2
pow[0x7] 451 1 T30 1 T62 10 T59 4


Summary for Variable np_sample_cnt_min_max_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for np_sample_cnt_min_max_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
max 195 1 T30 2 T62 4 T59 2
min 27168 1 T9 5 T12 24 T13 10


Summary for Variable np_sample_cnt_pow_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 16 3 13 81.25


User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins
NAME   COUNT   AT LEAST   NUMBER   STATUS   
pow[0x1] 0 1 1
pow[0x3] 0 1 1
pow[0x6] 0 1 1


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
pow[0x0] 27168 1 T9 5 T12 24 T13 10
pow[0x2] 1 1 T102 1 - - - -
pow[0x4] 1 1 T211 1 - - - -
pow[0x5] 2 1 T212 1 T213 1 - -
pow[0x7] 2 1 T214 1 T204 1 - -
pow[0x8] 4 1 T210 1 T215 1 T216 1
pow[0x9] 7 1 T205 1 T217 1 T218 1
pow[0xa] 23 1 T60 1 T63 1 T210 1
pow[0xb] 36 1 T60 2 T102 1 T206 1
pow[0xc] 63 1 T102 1 T63 1 T61 1
pow[0xd] 141 1 T62 1 T59 4 T60 2
pow[0xe] 278 1 T18 1 T62 5 T59 4
pow[0xf] 512 1 T30 1 T62 3 T59 3