Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2031	1			T4	6		T10	13		T22	20
auto[PWRUP]	119	1			T47	3		T53	1		T48	4
auto[ONEST_0]	73	1			T52	1		T50	4		T47	1
auto[ONEST_021]	20	1			T45	1		T53	1		T48	2
auto[ONEST_1]	83	1			T52	2		T50	1		T44	1
auto[ONEST_DONE]	2	1			T170	1		T366	1		-	-
auto[LP_0]	125	1			T15	1		T52	3		T50	2
auto[LP_021]	29	1			T50	1		T45	1		T223	1
auto[LP_1]	129	1			T52	2		T50	1		T47	1
auto[LP_EVAL]	38	1			T52	1		T50	1		T223	1
auto[LP_SLP]	480	1			T42	1		T52	4		T50	6
auto[LP_PWRUP]	31	1			T43	1		T47	1		T223	1
auto[NP_0]	164	1			T13	2		T15	2		T42	1
auto[NP_021]	37	1			T43	1		T52	1		T50	1
auto[NP_1]	195	1			T10	4		T13	1		T15	1
auto[NP_EVAL]	28	1			T15	1		T42	1		T43	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T200

1

T220

1

T273

1

min

1741

1

T4

5

T10

17

T22

20

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1761	1			T4	5		T10	17		T22	20
pow[0x1]	13	1			T50	2		T223	1		T319	1
pow[0x2]	27	1			T50	1		T79	1		T200	1
pow[0x3]	25	1			T48	1		T222	2		T54	1
pow[0x4]	57	1			T52	3		T51	1		T200	1
pow[0x5]	123	1			T4	1		T52	1		T50	2
pow[0x6]	216	1			T42	3		T52	2		T50	4
pow[0x7]	465	1			T42	1		T52	5		T50	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

171

1

T52

2

T50

3

T47

1

min

1257

1

T4

5

T10

14

T22

20

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1265	1			T4	5		T10	14		T22	20
pow[0x1]	16	1			T43	2		T255	1		T31	1
pow[0x2]	22	1			T42	4		T43	1		T45	1
pow[0x3]	13	1			T13	1		T15	4		T170	1
pow[0x4]	20	1			T10	3		T43	1		T44	1
pow[0x5]	2	1			T221	1		T367	1		-	-
pow[0x7]	4	1			T222	1		T368	1		T369	1
pow[0x8]	3	1			T303	1		T370	1		T368	1
pow[0x9]	9	1			T54	1		T225	1		T371	1
pow[0xa]	16	1			T50	1		T47	1		T79	1
pow[0xb]	31	1			T51	1		T200	2		T223	2
pow[0xc]	64	1			T42	1		T52	1		T50	1
pow[0xd]	136	1			T50	2		T47	1		T51	1
pow[0xe]	255	1			T42	2		T52	2		T50	3
pow[0xf]	545	1			T4	1		T42	1		T52	11