Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg
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Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
97.78 97.78 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
adc_ctrl_hw_reset_cg_inst 97.78 1 100 1 64 64



Group Instance : adc_ctrl_hw_reset_cg_inst
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
97.78 1 100 1 64 64



Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 45 1 44 97.78


Variables for Group Instance adc_ctrl_hw_reset_cg_inst
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
fsm_state_cp 17 1 16 94.12 100 1 1 0
lp_sample_cnt_min_max_cp 2 0 2 100.00 100 1 1 0
lp_sample_cnt_pow_cp 8 0 8 100.00 100 1 1 0
np_sample_cnt_min_max_cp 2 0 2 100.00 100 1 1 0
np_sample_cnt_pow_cp 16 0 16 100.00 100 1 1 0


Summary for Variable fsm_state_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 17 1 16 94.12


Automatically Generated Bins for fsm_state_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[NP_DONE] 0 1 1


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[PWRDN] 2252 1 T22 20 T23 20 T55 10
auto[PWRUP] 145 1 T18 1 T62 2 T59 1
auto[ONEST_0] 72 1 T18 2 T49 2 T62 2
auto[ONEST_021] 23 1 T63 1 T206 1 T191 2
auto[ONEST_1] 81 1 T49 1 T29 1 T59 1
auto[ONEST_DONE] 3 1 T357 1 T358 1 T359 1
auto[LP_0] 117 1 T41 1 T62 1 T59 2
auto[LP_021] 31 1 T30 1 T62 1 T60 1
auto[LP_1] 135 1 T18 1 T62 2 T59 1
auto[LP_EVAL] 66 1 T18 1 T59 1 T60 1
auto[LP_SLP] 476 1 T50 1 T30 1 T62 2
auto[LP_PWRUP] 30 1 T62 1 T63 1 T210 1
auto[NP_0] 225 1 T18 1 T41 2 T49 1
auto[NP_021] 43 1 T18 1 T41 1 T62 1
auto[NP_1] 212 1 T18 2 T41 3 T49 1
auto[NP_EVAL] 28 1 T50 1 T63 1 T191 2


Summary for Variable lp_sample_cnt_min_max_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for lp_sample_cnt_min_max_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
max 5 1 T217 1 T64 1 T327 1
min 1923 1 T22 20 T23 20 T55 10


Summary for Variable lp_sample_cnt_pow_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for lp_sample_cnt_pow_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
pow[0x0] 1937 1 T22 20 T23 20 T55 10
pow[0x1] 12 1 T161 1 T175 1 T360 1
pow[0x2] 17 1 T18 1 T63 1 T205 1
pow[0x3] 29 1 T62 1 T102 1 T63 1
pow[0x4] 66 1 T210 1 T206 3 T207 1
pow[0x5] 125 1 T30 1 T62 1 T59 2
pow[0x6] 235 1 T62 8 T59 1 T60 4
pow[0x7] 521 1 T18 2 T62 2 T59 6


Summary for Variable np_sample_cnt_min_max_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for np_sample_cnt_min_max_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
max 182 1 T62 1 T60 7 T102 2
min 1367 1 T22 20 T23 20 T55 10


Summary for Variable np_sample_cnt_pow_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 16 0 16 100.00


User Defined Bins for np_sample_cnt_pow_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
pow[0x0] 1371 1 T22 20 T23 20 T55 10
pow[0x1] 7 1 T259 1 T304 1 T65 1
pow[0x2] 27 1 T52 3 T31 1 T131 5
pow[0x3] 41 1 T18 2 T41 6 T29 1
pow[0x4] 80 1 T18 2 T49 1 T29 1
pow[0x5] 2 1 T33 1 T65 1 - -
pow[0x6] 1 1 T315 1 - - - -
pow[0x7] 1 1 T361 1 - - - -
pow[0x8] 3 1 T362 1 T204 1 T363 1
pow[0x9] 11 1 T191 1 T208 1 T47 1
pow[0xa] 12 1 T62 1 T61 1 T185 1
pow[0xb] 53 1 T62 1 T59 1 T60 2
pow[0xc] 54 1 T62 2 T60 2 T207 2
pow[0xd] 132 1 T60 3 T102 1 T63 1
pow[0xe] 291 1 T62 2 T59 6 T60 6
pow[0xf] 547 1 T18 1 T30 2 T62 8