Assert Coverage for Module :
adc_ctrl_fsm_sva
Assertion Details
FsmDebugOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
32107818 |
32023902 |
0 |
0 |
T1 |
100 |
1 |
0 |
0 |
T2 |
1129 |
1058 |
0 |
0 |
T3 |
1098 |
1041 |
0 |
0 |
T4 |
1048 |
979 |
0 |
0 |
T5 |
642 |
557 |
0 |
0 |
T6 |
5792 |
5734 |
0 |
0 |
T7 |
1208 |
1109 |
0 |
0 |
T21 |
86 |
1 |
0 |
0 |
T22 |
80 |
1 |
0 |
0 |
T23 |
63 |
1 |
0 |
0 |
FsmStateHwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1219 |
1219 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
FsmStateSwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
32107818 |
6502 |
0 |
0 |
T9 |
33999 |
5 |
0 |
0 |
T10 |
1145 |
0 |
0 |
0 |
T11 |
7867 |
0 |
0 |
0 |
T12 |
101303 |
24 |
0 |
0 |
T13 |
31858 |
10 |
0 |
0 |
T14 |
0 |
10 |
0 |
0 |
T15 |
0 |
14 |
0 |
0 |
T16 |
0 |
6 |
0 |
0 |
T17 |
0 |
19 |
0 |
0 |
T19 |
0 |
8 |
0 |
0 |
T20 |
0 |
9 |
0 |
0 |
T24 |
818 |
0 |
0 |
0 |
T25 |
6471 |
0 |
0 |
0 |
T26 |
87 |
0 |
0 |
0 |
T27 |
85 |
0 |
0 |
0 |
T28 |
1188 |
0 |
0 |
0 |
T43 |
0 |
5 |
0 |
0 |
LpSampleCntHwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1219 |
1219 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
LpSampleCntSwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
32107818 |
6502 |
0 |
0 |
T9 |
33999 |
5 |
0 |
0 |
T10 |
1145 |
0 |
0 |
0 |
T11 |
7867 |
0 |
0 |
0 |
T12 |
101303 |
24 |
0 |
0 |
T13 |
31858 |
10 |
0 |
0 |
T14 |
0 |
10 |
0 |
0 |
T15 |
0 |
14 |
0 |
0 |
T16 |
0 |
6 |
0 |
0 |
T17 |
0 |
19 |
0 |
0 |
T19 |
0 |
8 |
0 |
0 |
T20 |
0 |
9 |
0 |
0 |
T24 |
818 |
0 |
0 |
0 |
T25 |
6471 |
0 |
0 |
0 |
T26 |
87 |
0 |
0 |
0 |
T27 |
85 |
0 |
0 |
0 |
T28 |
1188 |
0 |
0 |
0 |
T43 |
0 |
5 |
0 |
0 |
NpSampleCntHwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1219 |
1219 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
NpSampleCntSwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
32107818 |
6502 |
0 |
0 |
T9 |
33999 |
5 |
0 |
0 |
T10 |
1145 |
0 |
0 |
0 |
T11 |
7867 |
0 |
0 |
0 |
T12 |
101303 |
24 |
0 |
0 |
T13 |
31858 |
10 |
0 |
0 |
T14 |
0 |
10 |
0 |
0 |
T15 |
0 |
14 |
0 |
0 |
T16 |
0 |
6 |
0 |
0 |
T17 |
0 |
19 |
0 |
0 |
T19 |
0 |
8 |
0 |
0 |
T20 |
0 |
9 |
0 |
0 |
T24 |
818 |
0 |
0 |
0 |
T25 |
6471 |
0 |
0 |
0 |
T26 |
87 |
0 |
0 |
0 |
T27 |
85 |
0 |
0 |
0 |
T28 |
1188 |
0 |
0 |
0 |
T43 |
0 |
5 |
0 |
0 |
PwrupTimerCntHwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1219 |
1219 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
PwrupTimerCntSwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
32107818 |
6502 |
0 |
0 |
T9 |
33999 |
5 |
0 |
0 |
T10 |
1145 |
0 |
0 |
0 |
T11 |
7867 |
0 |
0 |
0 |
T12 |
101303 |
24 |
0 |
0 |
T13 |
31858 |
10 |
0 |
0 |
T14 |
0 |
10 |
0 |
0 |
T15 |
0 |
14 |
0 |
0 |
T16 |
0 |
6 |
0 |
0 |
T17 |
0 |
19 |
0 |
0 |
T19 |
0 |
8 |
0 |
0 |
T20 |
0 |
9 |
0 |
0 |
T24 |
818 |
0 |
0 |
0 |
T25 |
6471 |
0 |
0 |
0 |
T26 |
87 |
0 |
0 |
0 |
T27 |
85 |
0 |
0 |
0 |
T28 |
1188 |
0 |
0 |
0 |
T43 |
0 |
5 |
0 |
0 |
WakeupTimerCntHwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1219 |
1219 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
WakeupTimerCntSwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
32107818 |
6502 |
0 |
0 |
T9 |
33999 |
5 |
0 |
0 |
T10 |
1145 |
0 |
0 |
0 |
T11 |
7867 |
0 |
0 |
0 |
T12 |
101303 |
24 |
0 |
0 |
T13 |
31858 |
10 |
0 |
0 |
T14 |
0 |
10 |
0 |
0 |
T15 |
0 |
14 |
0 |
0 |
T16 |
0 |
6 |
0 |
0 |
T17 |
0 |
19 |
0 |
0 |
T19 |
0 |
8 |
0 |
0 |
T20 |
0 |
9 |
0 |
0 |
T24 |
818 |
0 |
0 |
0 |
T25 |
6471 |
0 |
0 |
0 |
T26 |
87 |
0 |
0 |
0 |
T27 |
85 |
0 |
0 |
0 |
T28 |
1188 |
0 |
0 |
0 |
T43 |
0 |
5 |
0 |
0 |