Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : adc_ctrl_core
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_adc_ctrl_core 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_adc_ctrl_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.83 100.00 99.76 100.00 99.37 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_adc_ctrl_fsm 99.75 100.00 100.00 100.00 98.73 100.00
u_adc_ctrl_intr 99.00 100.00 96.00 100.00 100.00
u_oneshot_done_sync 100.00 100.00 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : adc_ctrl_core
Line No.TotalCoveredPercent
TOTAL6363100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5611100.00
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CONT_ASSIGN6311100.00
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CONT_ASSIGN6311100.00
CONT_ASSIGN6311100.00
CONT_ASSIGN6311100.00
CONT_ASSIGN6311100.00
CONT_ASSIGN6311100.00
CONT_ASSIGN6311100.00
CONT_ASSIGN7211100.00
CONT_ASSIGN7311100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN11711100.00
CONT_ASSIGN11711100.00
CONT_ASSIGN11711100.00
CONT_ASSIGN11711100.00
CONT_ASSIGN11711100.00
CONT_ASSIGN11711100.00
CONT_ASSIGN11711100.00
CONT_ASSIGN11711100.00
CONT_ASSIGN12111100.00
CONT_ASSIGN12111100.00
CONT_ASSIGN12111100.00
CONT_ASSIGN12111100.00
CONT_ASSIGN12111100.00
CONT_ASSIGN12111100.00
CONT_ASSIGN12111100.00
CONT_ASSIGN12111100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN21311100.00

55 56 8/8 assign aon_filter_ctl[0][k] = '{ Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  57 min_v: reg2hw_i.adc_chn0_filter_ctl[k].min_v.q, 58 max_v: reg2hw_i.adc_chn0_filter_ctl[k].max_v.q, 59 cond: reg2hw_i.adc_chn0_filter_ctl[k].cond.q, 60 en: reg2hw_i.adc_chn0_filter_ctl[k].en.q 61 }; 62 63 8/8 assign aon_filter_ctl[1][k] = '{ Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  64 min_v: reg2hw_i.adc_chn1_filter_ctl[k].min_v.q, 65 max_v: reg2hw_i.adc_chn1_filter_ctl[k].max_v.q, 66 cond: reg2hw_i.adc_chn1_filter_ctl[k].cond.q, 67 en: reg2hw_i.adc_chn1_filter_ctl[k].en.q 68 }; 69 end // block: gen_filter_ctl_sync 70 71 // Recent adc channel values 72 1/1 assign adc_chn_val_o[0].adc_chn_value.de = chn0_val_we; Tests: T1 T2 T3  73 1/1 assign adc_chn_val_o[0].adc_chn_value.d = chn0_val; Tests: T1 T2 T3  74 1/1 assign adc_chn_val_o[1].adc_chn_value.de = chn1_val_we; Tests: T1 T2 T3  75 1/1 assign adc_chn_val_o[1].adc_chn_value.d = chn1_val; Tests: T1 T2 T3  76 77 // Interrupt based adc channel values 78 // The value of the adc is captured whenever an interrupt triggers. 79 // There are two cases: 80 // completion of one shot mode 81 // match detection from the filters 82 logic chn_val_intr_we; 83 1/1 assign chn_val_intr_we = reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : Tests: T1 T2 T3  84 reg2hw_i.adc_en_ctl.adc_enable.q ? |match_pulse : '0; 85 86 1/1 assign adc_chn_val_o[0].adc_chn_value_intr.de = chn_val_intr_we; Tests: T1 T2 T3  87 1/1 assign adc_chn_val_o[0].adc_chn_value_intr.d = chn0_val; Tests: T1 T2 T3  88 1/1 assign adc_chn_val_o[1].adc_chn_value_intr.de = chn_val_intr_we; Tests: T1 T2 T3  89 1/1 assign adc_chn_val_o[1].adc_chn_value_intr.d = chn1_val; Tests: T1 T2 T3  90 91 //Connect the ports for future extension 92 assign adc_chn_val_o[0].adc_chn_value_ext.de = 1'b0; 93 assign adc_chn_val_o[0].adc_chn_value_ext.d = 2'b0; 94 assign adc_chn_val_o[1].adc_chn_value_ext.de = 1'b0; 95 assign adc_chn_val_o[1].adc_chn_value_ext.d = 2'b0; 96 97 assign adc_chn_val_o[0].adc_chn_value_intr_ext.de = 1'b0; 98 assign adc_chn_val_o[0].adc_chn_value_intr_ext.d = 2'b0; 99 assign adc_chn_val_o[1].adc_chn_value_intr_ext.de = 1'b0; 100 assign adc_chn_val_o[1].adc_chn_value_intr_ext.d = 2'b0; 101 102 // Evaluate if there is a match from chn0 and chn1 samples 103 for (genvar k = 0 ; k < NumAdcFilter ; k++) begin : gen_filter_match 104 8/8 assign chn0_match[k] = (!aon_filter_ctl[0][k].cond) ? Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  105 (aon_filter_ctl[0][k].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][k].max_v) : 106 (aon_filter_ctl[0][k].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][k].max_v); 107 8/8 assign chn1_match[k] = (!aon_filter_ctl[1][k].cond) ? Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  108 (aon_filter_ctl[1][k].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][k].max_v) : 109 (aon_filter_ctl[1][k].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][k].max_v); 110 111 // If the filter on a particular channel is NOT enabled, it does not participate in the final 112 // match decision. This means the match value should have no impact on the final result. 113 // For example, if channel 0's filter is enabled, but channel 1's is not, the match result 114 // is determined solely based on whether channel 0's filter shows a match. 115 // On the other hand, if all channel's filters are enabled, then a match is seen only when 116 // both filters match. 117 8/8 assign match[k] = |{aon_filter_ctl[0][k].en, aon_filter_ctl[1][k].en} & Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  118 (!aon_filter_ctl[0][k].en | (chn0_match[k] & aon_filter_ctl[0][k].en)) & 119 (!aon_filter_ctl[1][k].en | (chn1_match[k] & aon_filter_ctl[1][k].en)) ; 120 121 8/8 assign match_pulse[k] = adc_ctrl_done && match[k]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  122 123 // Explicitly create assertions for all the matching conditions. 124 // These assertions are unwieldy and not suitable for expansion to more channels. 125 // They should be adjusted eventually. 126 `ASSERT(MatchCheck00_A, !aon_filter_ctl[0][k].en & !aon_filter_ctl[1][k].en |-> 127 !match[k], clk_aon_i, !rst_aon_ni) 128 `ASSERT(MatchCheck01_A, !aon_filter_ctl[0][k].en & aon_filter_ctl[1][k].en |-> 129 match[k] == chn1_match[k], clk_aon_i, !rst_aon_ni) 130 `ASSERT(MatchCheck10_A, aon_filter_ctl[0][k].en & !aon_filter_ctl[1][k].en |-> 131 match[k] == chn0_match[k], clk_aon_i, !rst_aon_ni) 132 `ASSERT(MatchCheck11_A, aon_filter_ctl[0][k].en & aon_filter_ctl[1][k].en |-> 133 match[k] == (chn0_match[k] & chn1_match[k]), clk_aon_i, !rst_aon_ni) 134 end 135 136 // adc filter status 137 1/1 assign aon_filter_status_o.match.d = match_pulse | reg2hw_i.filter_status.match.q; Tests: T1 T2 T3  138 1/1 assign aon_filter_status_o.match.de = |match_pulse; Tests: T1 T2 T3  139 // transition status 140 1/1 assign aon_filter_status_o.trans.d = aon_fsm_trans | reg2hw_i.filter_status.trans.q; Tests: T1 T2 T3  141 1/1 assign aon_filter_status_o.trans.de = aon_fsm_trans; Tests: T1 T2 T3  142 143 // generate wakeup to external power manager if filter status 144 // and wakeup enable are set. 145 1/1 assign wkup_req_o = |(reg2hw_i.filter_status.match.q & Tests: T1 T2 T3  146 reg2hw_i.adc_wakeup_ctl.match_en.q) || 147 (reg2hw_i.filter_status.trans.q & 148 reg2hw_i.adc_wakeup_ctl.trans_en.q); 149 150 //instantiate the main state machine 151 adc_ctrl_fsm u_adc_ctrl_fsm ( 152 .clk_aon_i, 153 .rst_aon_ni, 154 // configuration and settings from reg interface 155 .cfg_fsm_rst_i(reg2hw_i.adc_fsm_rst.q), 156 .cfg_adc_enable_i(reg2hw_i.adc_en_ctl.adc_enable.q), 157 .cfg_oneshot_mode_i(reg2hw_i.adc_en_ctl.oneshot_mode.q), 158 .cfg_lp_mode_i(reg2hw_i.adc_pd_ctl.lp_mode.q), 159 .cfg_pwrup_time_i(reg2hw_i.adc_pd_ctl.pwrup_time.q), 160 .cfg_wakeup_time_i(reg2hw_i.adc_pd_ctl.wakeup_time.q), 161 .cfg_lp_sample_cnt_i(reg2hw_i.adc_lp_sample_ctl.q), 162 .cfg_np_sample_cnt_i(reg2hw_i.adc_sample_ctl.q), 163 // 164 .adc_ctrl_match_i(match), 165 .adc_d_i(adc_i.data), 166 .adc_d_val_i(adc_i.data_valid), 167 .adc_pd_o(adc_o.pd), 168 .adc_chn_sel_o(adc_o.channel_sel), 169 .chn0_val_we_o(chn0_val_we), 170 .chn1_val_we_o(chn1_val_we), 171 .chn0_val_o(chn0_val), 172 .chn1_val_o(chn1_val), 173 .adc_ctrl_done_o(adc_ctrl_done), 174 .oneshot_done_o(oneshot_done), 175 .aon_fsm_state_o, 176 .aon_fsm_trans_o(aon_fsm_trans) 177 ); 178 179 // synchronzie from clk_aon into cfg domain 180 logic cfg_oneshot_done; 181 prim_pulse_sync u_oneshot_done_sync ( 182 .clk_src_i(clk_aon_i), 183 .rst_src_ni(rst_aon_ni), 184 .src_pulse_i(oneshot_done), 185 .clk_dst_i(clk_i), 186 .rst_dst_ni(rst_ni), 187 .dst_pulse_o(cfg_oneshot_done) 188 ); 189 190 //Instantiate the interrupt module 191 adc_ctrl_intr u_adc_ctrl_intr ( 192 .clk_i, 193 .rst_ni, 194 .clk_aon_i, 195 .rst_aon_ni, 196 .aon_filter_match_i(match_pulse), 197 .aon_fsm_trans_i(aon_fsm_trans), 198 .cfg_oneshot_done_i(cfg_oneshot_done), 199 .cfg_intr_en_i(reg2hw_i.adc_intr_ctl.match_en.q), 200 .cfg_intr_trans_en_i(reg2hw_i.adc_intr_ctl.trans_en.q), 201 .cfg_oneshot_done_en_i(reg2hw_i.adc_intr_ctl.oneshot_en.q), 202 .intr_state_i(reg2hw_i.intr_state), 203 .intr_enable_i(reg2hw_i.intr_enable), 204 .intr_test_i(reg2hw_i.intr_test), 205 .intr_state_o, 206 .adc_intr_status_i(reg2hw_i.adc_intr_status), 207 .adc_intr_status_o, 208 .intr_o 209 ); 210 211 // unused register inputs 212 logic unused_cfgs; 213 1/1 assign unused_cfgs = ^reg2hw_i; Tests: T1 T2 T3 

Cond Coverage for Module : adc_ctrl_core
TotalCoveredPercent
Conditions293293100.00
Logical293293100.00
Non-Logical00
Event00

 LINE       83
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       83
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))
-1-StatusTests
0CoveredT12,T14,T15
1CoveredT1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------
-1--2-StatusTests
01CoveredT9,T12,T13
10CoveredT2,T3,T4
11CoveredT1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------
-1--2-StatusTests
00CoveredT12,T14,T15
01CoveredT12,T14,T15
10CoveredT12,T14,T15

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))
-1-StatusTests
0CoveredT12,T14,T18
1CoveredT1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------
-1--2-StatusTests
01CoveredT9,T12,T13
10CoveredT2,T3,T4
11CoveredT1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------
-1--2-StatusTests
00CoveredT12,T14,T20
01CoveredT12,T14,T20
10CoveredT12,T14,T18

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))
-1-StatusTests
0CoveredT12,T14,T15
1CoveredT1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------
-1--2-StatusTests
01CoveredT9,T12,T13
10CoveredT2,T3,T4
11CoveredT1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------
-1--2-StatusTests
00CoveredT12,T14,T15
01CoveredT12,T14,T15
10CoveredT12,T14,T15

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))
-1-StatusTests
0CoveredT12,T15,T18
1CoveredT1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------
-1--2-StatusTests
01CoveredT9,T13,T14
10CoveredT2,T3,T4
11CoveredT1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------
-1--2-StatusTests
00CoveredT12,T15,T18
01CoveredT12,T15,T18
10CoveredT12,T15,T18

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))
-1-StatusTests
0CoveredT9,T12,T14
1CoveredT1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------
-1--2-StatusTests
01CoveredT13,T15,T16
10CoveredT2,T3,T4
11CoveredT1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------
-1--2-StatusTests
00CoveredT9,T12,T14
01CoveredT9,T12,T14
10CoveredT9,T12,T14

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))
-1-StatusTests
0CoveredT9,T12,T15
1CoveredT1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------
-1--2-StatusTests
01CoveredT12,T13,T14
10CoveredT2,T3,T4
11CoveredT1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------
-1--2-StatusTests
00CoveredT9,T12,T15
01CoveredT9,T12,T15
10CoveredT12,T15,T19

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))
-1-StatusTests
0CoveredT9,T12,T15
1CoveredT1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------
-1--2-StatusTests
01CoveredT12,T13,T14
10CoveredT2,T3,T4
11CoveredT1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------
-1--2-StatusTests
00CoveredT9,T12,T15
01CoveredT9,T12,T15
10CoveredT9,T12,T15

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))
-1-StatusTests
0CoveredT12,T13,T14
1CoveredT1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------
-1--2-StatusTests
01CoveredT9,T12,T15
10CoveredT2,T3,T4
11CoveredT1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------
-1--2-StatusTests
00CoveredT12,T13,T14
01CoveredT12,T13,T14
10CoveredT12,T13,T14

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))
-1-StatusTests
0CoveredT12,T14,T15
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------
-1--2-StatusTests
01CoveredT9,T12,T13
10CoveredT2,T3,T4
11CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------
-1--2-StatusTests
00CoveredT12,T14,T15
01CoveredT12,T14,T15
10CoveredT12,T14,T15

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))
-1-StatusTests
0CoveredT12,T14,T18
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------
-1--2-StatusTests
01CoveredT9,T12,T13
10CoveredT2,T3,T4
11CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------
-1--2-StatusTests
00CoveredT12,T14,T41
01CoveredT12,T14,T41
10CoveredT12,T14,T18

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))
-1-StatusTests
0CoveredT12,T15,T20
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------
-1--2-StatusTests
01CoveredT9,T12,T13
10CoveredT2,T3,T4
11CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------
-1--2-StatusTests
00CoveredT12,T15,T20
01CoveredT12,T15,T41
10CoveredT12,T15,T20

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))
-1-StatusTests
0CoveredT12,T15,T18
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------
-1--2-StatusTests
01CoveredT9,T13,T14
10CoveredT2,T3,T4
11CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------
-1--2-StatusTests
00CoveredT12,T15,T18
01CoveredT12,T15,T18
10CoveredT12,T15,T18

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))
-1-StatusTests
0CoveredT9,T12,T14
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------
-1--2-StatusTests
01CoveredT13,T15,T16
10CoveredT2,T3,T4
11CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------
-1--2-StatusTests
00CoveredT9,T12,T14
01CoveredT9,T12,T14
10CoveredT9,T12,T14

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))
-1-StatusTests
0CoveredT9,T12,T15
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------
-1--2-StatusTests
01CoveredT12,T13,T14
10CoveredT2,T3,T4
11CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------
-1--2-StatusTests
00CoveredT9,T12,T15
01CoveredT9,T12,T15
10CoveredT9,T12,T15

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))
-1-StatusTests
0CoveredT9,T12,T15
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------
-1--2-StatusTests
01CoveredT12,T13,T14
10CoveredT2,T3,T4
11CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------
-1--2-StatusTests
00CoveredT9,T12,T15
01CoveredT9,T12,T15
10CoveredT9,T12,T15

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))
-1-StatusTests
0CoveredT12,T13,T14
1CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------
-1--2-StatusTests
01CoveredT9,T12,T15
10CoveredT2,T3,T4
11CoveredT1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------
-1--2-StatusTests
00CoveredT12,T13,T14
01CoveredT12,T13,T14
10CoveredT12,T13,T14

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT9,T12,T13
110CoveredT9,T12,T13
111CoveredT9,T12,T13

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------
-1--2-StatusTests
00CoveredT9,T12,T13
01CoveredT9,T12,T13
10CoveredT1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT9,T12,T13
10CoveredT1,T2,T3
11CoveredT9,T12,T13

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------
-1--2-StatusTests
00CoveredT9,T12,T13
01CoveredT9,T12,T13
10CoveredT1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT9,T12,T13
10CoveredT1,T2,T3
11CoveredT9,T12,T13

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT9,T12,T13
110CoveredT9,T12,T13
111CoveredT9,T12,T13

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------
-1--2-StatusTests
00CoveredT9,T12,T13
01CoveredT9,T12,T13
10CoveredT1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT9,T12,T13
10CoveredT1,T2,T3
11CoveredT9,T12,T13

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------
-1--2-StatusTests
00CoveredT9,T12,T13
01CoveredT9,T12,T13
10CoveredT1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT9,T12,T13
10CoveredT1,T2,T3
11CoveredT9,T12,T13

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT12,T13,T14
110CoveredT9,T12,T13
111CoveredT9,T12,T13

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------
-1--2-StatusTests
00CoveredT12,T13,T14
01CoveredT12,T13,T14
10CoveredT1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT12,T13,T14
10CoveredT1,T2,T3
11CoveredT12,T13,T14

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------
-1--2-StatusTests
00CoveredT9,T12,T13
01CoveredT9,T12,T13
10CoveredT1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT9,T12,T13
10CoveredT1,T2,T3
11CoveredT9,T12,T13

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT9,T12,T13
110CoveredT9,T12,T13
111CoveredT9,T12,T13

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------
-1--2-StatusTests
00CoveredT9,T12,T13
01CoveredT9,T12,T13
10CoveredT1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT9,T12,T13
10CoveredT1,T2,T3
11CoveredT9,T12,T13

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------
-1--2-StatusTests
00CoveredT9,T12,T13
01CoveredT9,T12,T13
10CoveredT1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT9,T12,T13
10CoveredT1,T2,T3
11CoveredT9,T12,T13

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT12,T13,T14
110CoveredT12,T13,T15
111CoveredT12,T13,T14

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------
-1--2-StatusTests
00CoveredT12,T13,T14
01CoveredT12,T13,T14
10CoveredT1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT12,T13,T14
10CoveredT1,T2,T3
11CoveredT12,T13,T14

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------
-1--2-StatusTests
00CoveredT12,T13,T14
01CoveredT12,T13,T14
10CoveredT1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT12,T13,T14
10CoveredT1,T2,T3
11CoveredT12,T13,T14

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT9,T12,T13
110CoveredT9,T12,T13
111CoveredT9,T12,T13

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------
-1--2-StatusTests
00CoveredT9,T12,T13
01CoveredT9,T12,T13
10CoveredT1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT9,T12,T13
10CoveredT1,T2,T3
11CoveredT9,T12,T13

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------
-1--2-StatusTests
00CoveredT9,T12,T13
01CoveredT9,T12,T13
10CoveredT1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT9,T12,T13
10CoveredT1,T2,T3
11CoveredT9,T12,T13

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT9,T12,T13
110CoveredT9,T12,T13
111CoveredT9,T12,T13

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------
-1--2-StatusTests
00CoveredT9,T12,T13
01CoveredT9,T12,T13
10CoveredT1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT9,T12,T13
10CoveredT1,T2,T3
11CoveredT9,T12,T13

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------
-1--2-StatusTests
00CoveredT9,T12,T13
01CoveredT9,T12,T13
10CoveredT1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT9,T12,T13
10CoveredT1,T2,T3
11CoveredT9,T12,T13

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT12,T13,T15
110CoveredT12,T13,T15
111CoveredT12,T13,T15

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------
-1--2-StatusTests
00CoveredT12,T13,T15
01CoveredT12,T13,T15
10CoveredT1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT12,T13,T15
10CoveredT1,T2,T3
11CoveredT12,T13,T15

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------
-1--2-StatusTests
00CoveredT12,T13,T15
01CoveredT12,T13,T15
10CoveredT1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT12,T13,T15
10CoveredT1,T2,T3
11CoveredT12,T13,T15

 LINE       121
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---
-1--2-StatusTests
01CoveredT9,T12,T13
10CoveredT9,T12,T13
11CoveredT9,T12,T13

 LINE       121
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---
-1--2-StatusTests
01CoveredT9,T12,T13
10CoveredT9,T12,T13
11CoveredT9,T12,T13

 LINE       121
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---
-1--2-StatusTests
01CoveredT9,T12,T13
10CoveredT9,T12,T13
11CoveredT9,T12,T13

 LINE       121
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---
-1--2-StatusTests
01CoveredT9,T12,T13
10CoveredT9,T12,T13
11CoveredT9,T12,T13

 LINE       121
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---
-1--2-StatusTests
01CoveredT12,T13,T14
10CoveredT9,T12,T13
11CoveredT12,T13,T14

 LINE       121
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---
-1--2-StatusTests
01CoveredT9,T12,T13
10CoveredT9,T12,T13
11CoveredT9,T12,T13

 LINE       121
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---
-1--2-StatusTests
01CoveredT9,T12,T13
10CoveredT9,T12,T13
11CoveredT9,T12,T13

 LINE       121
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---
-1--2-StatusTests
01CoveredT12,T13,T15
10CoveredT9,T12,T13
11CoveredT12,T13,T15

 LINE       140
 EXPRESSION (aon_fsm_trans | reg2hw_i.filter_status.trans.q)
             ------1------   ---------------2--------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT12,T15,T16
10CoveredT12,T15,T16

 LINE       145
 EXPRESSION (((|(reg2hw_i.filter_status.match.q & reg2hw_i.adc_wakeup_ctl.match_en.q))) || (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q))
             -------------------------------------1------------------------------------    ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT12,T15,T16
10CoveredT12,T15,T16

 LINE       145
 SUB-EXPRESSION (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q)
                 ---------------1--------------   -----------------2----------------
-1--2-StatusTests
01CoveredT12,T15,T16
10CoveredT12,T18,T19
11CoveredT12,T15,T16

Branch Coverage for Module : adc_ctrl_core
Line No.TotalCoveredPercent
Branches 35 35 100.00
TERNARY 83 3 3 100.00
TERNARY 104 2 2 100.00
TERNARY 107 2 2 100.00
TERNARY 104 2 2 100.00
TERNARY 107 2 2 100.00
TERNARY 104 2 2 100.00
TERNARY 107 2 2 100.00
TERNARY 104 2 2 100.00
TERNARY 107 2 2 100.00
TERNARY 104 2 2 100.00
TERNARY 107 2 2 100.00
TERNARY 104 2 2 100.00
TERNARY 107 2 2 100.00
TERNARY 104 2 2 100.00
TERNARY 107 2 2 100.00
TERNARY 104 2 2 100.00
TERNARY 107 2 2 100.00


83 assign chn_val_intr_we = reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : -1- ==> 84 reg2hw_i.adc_en_ctl.adc_enable.q ? |match_pulse : '0; -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T2,T3,T4
0 1 Covered T4,T5,T6
0 0 Covered T1,T2,T3


104 assign chn0_match[k] = (!aon_filter_ctl[0][k].cond) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T12,T14,T15


107 assign chn1_match[k] = (!aon_filter_ctl[1][k].cond) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T12,T14,T15


104 assign chn0_match[k] = (!aon_filter_ctl[0][k].cond) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T12,T14,T18


107 assign chn1_match[k] = (!aon_filter_ctl[1][k].cond) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T12,T14,T18


104 assign chn0_match[k] = (!aon_filter_ctl[0][k].cond) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T12,T14,T15


107 assign chn1_match[k] = (!aon_filter_ctl[1][k].cond) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T12,T15,T20


104 assign chn0_match[k] = (!aon_filter_ctl[0][k].cond) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T12,T15,T18


107 assign chn1_match[k] = (!aon_filter_ctl[1][k].cond) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T12,T15,T18


104 assign chn0_match[k] = (!aon_filter_ctl[0][k].cond) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T9,T12,T14


107 assign chn1_match[k] = (!aon_filter_ctl[1][k].cond) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T9,T12,T14


104 assign chn0_match[k] = (!aon_filter_ctl[0][k].cond) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T9,T12,T15


107 assign chn1_match[k] = (!aon_filter_ctl[1][k].cond) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T9,T12,T15


104 assign chn0_match[k] = (!aon_filter_ctl[0][k].cond) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T9,T12,T15


107 assign chn1_match[k] = (!aon_filter_ctl[1][k].cond) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T9,T12,T15


104 assign chn0_match[k] = (!aon_filter_ctl[0][k].cond) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T12,T13,T14


107 assign chn1_match[k] = (!aon_filter_ctl[1][k].cond) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T12,T13,T14


Assert Coverage for Module : adc_ctrl_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 33 33 100.00 33 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 33 33 100.00 33 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
MaxFilters_A 35023136 34720866 0 0
gen_filter_match[0].MatchCheck00_A 35023136 10454005 0 0
gen_filter_match[0].MatchCheck01_A 35023136 3163903 0 0
gen_filter_match[0].MatchCheck10_A 35023136 2346869 0 0
gen_filter_match[0].MatchCheck11_A 35023136 18756089 0 0
gen_filter_match[1].MatchCheck00_A 35023136 12808169 0 0
gen_filter_match[1].MatchCheck01_A 35023136 1471060 0 0
gen_filter_match[1].MatchCheck10_A 35023136 1577928 0 0
gen_filter_match[1].MatchCheck11_A 35023136 18863709 0 0
gen_filter_match[2].MatchCheck00_A 35023136 13491242 0 0
gen_filter_match[2].MatchCheck01_A 35023136 540056 0 0
gen_filter_match[2].MatchCheck10_A 35023136 859638 0 0
gen_filter_match[2].MatchCheck11_A 35023136 19829930 0 0
gen_filter_match[3].MatchCheck00_A 35023136 12637875 0 0
gen_filter_match[3].MatchCheck01_A 35023136 387879 0 0
gen_filter_match[3].MatchCheck10_A 35023136 203476 0 0
gen_filter_match[3].MatchCheck11_A 35023136 21491636 0 0
gen_filter_match[4].MatchCheck00_A 35023136 13273479 0 0
gen_filter_match[4].MatchCheck01_A 35023136 128772 0 0
gen_filter_match[4].MatchCheck10_A 35023136 89 0 0
gen_filter_match[4].MatchCheck11_A 35023136 21318526 0 0
gen_filter_match[5].MatchCheck00_A 35023136 14371889 0 0
gen_filter_match[5].MatchCheck01_A 35023136 67064 0 0
gen_filter_match[5].MatchCheck10_A 35023136 33635 0 0
gen_filter_match[5].MatchCheck11_A 35023136 20248278 0 0
gen_filter_match[6].MatchCheck00_A 35023136 13776792 0 0
gen_filter_match[6].MatchCheck01_A 35023136 65715 0 0
gen_filter_match[6].MatchCheck10_A 35023136 110 0 0
gen_filter_match[6].MatchCheck11_A 35023136 20878249 0 0
gen_filter_match[7].MatchCheck00_A 35023136 14345814 0 0
gen_filter_match[7].MatchCheck01_A 35023136 179655 0 0
gen_filter_match[7].MatchCheck10_A 35023136 73922 0 0
gen_filter_match[7].MatchCheck11_A 35023136 20121475 0 0


MaxFilters_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35023136 34720866 0 0
T1 103 4 0 0
T2 1129 1058 0 0
T3 1098 1041 0 0
T4 1048 979 0 0
T5 642 557 0 0
T6 5792 5734 0 0
T7 1208 1109 0 0
T21 91 6 0 0
T22 1639 5 0 0
T23 1605 6 0 0

gen_filter_match[0].MatchCheck00_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35023136 10454005 0 0
T1 103 4 0 0
T2 1129 1058 0 0
T3 1098 1041 0 0
T4 1048 979 0 0
T5 642 557 0 0
T6 5792 5734 0 0
T7 1208 1109 0 0
T21 91 6 0 0
T22 1639 5 0 0
T23 1605 6 0 0

gen_filter_match[0].MatchCheck01_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35023136 3163903 0 0
T12 101303 32540 0 0
T13 31858 0 0 0
T14 33725 0 0 0
T15 68835 0 0 0
T16 40863 0 0 0
T18 0 62903 0 0
T25 6471 0 0 0
T26 91 0 0 0
T27 1637 0 0 0
T28 1188 0 0 0
T30 0 1111 0 0
T31 0 4884 0 0
T52 0 21952 0 0
T58 8440 0 0 0
T132 0 33519 0 0
T133 0 32885 0 0
T134 0 66688 0 0
T135 0 39301 0 0
T136 0 71303 0 0

gen_filter_match[0].MatchCheck10_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35023136 2346869 0 0
T9 33999 1 0 0
T10 1145 0 0 0
T11 7867 0 0 0
T12 101303 2 0 0
T13 31858 0 0 0
T18 0 2 0 0
T19 0 35555 0 0
T24 818 0 0 0
T25 6471 0 0 0
T26 91 0 0 0
T27 1637 0 0 0
T28 1188 0 0 0
T29 0 38304 0 0
T41 0 74522 0 0
T49 0 57392 0 0
T137 0 32884 0 0
T138 0 1 0 0
T139 0 35348 0 0

gen_filter_match[0].MatchCheck11_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35023136 18756089 0 0
T9 33999 33902 0 0
T10 1145 0 0 0
T11 7867 0 0 0
T12 101303 34849 0 0
T13 31858 31791 0 0
T15 0 36208 0 0
T16 0 40808 0 0
T17 0 66456 0 0
T18 0 12702 0 0
T24 818 0 0 0
T25 6471 0 0 0
T26 91 0 0 0
T27 1637 0 0 0
T28 1188 0 0 0
T43 0 31508 0 0
T56 0 69646 0 0
T140 0 31914 0 0

gen_filter_match[1].MatchCheck00_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35023136 12808169 0 0
T1 103 4 0 0
T2 1129 1058 0 0
T3 1098 1041 0 0
T4 1048 979 0 0
T5 642 557 0 0
T6 5792 5734 0 0
T7 1208 1109 0 0
T21 91 6 0 0
T22 1639 5 0 0
T23 1605 6 0 0

gen_filter_match[1].MatchCheck01_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35023136 1471060 0 0
T29 0 35360 0 0
T49 64733 0 0 0
T57 34103 0 0 0
T107 0 33567 0 0
T132 66142 0 0 0
T134 0 32405 0 0
T141 33027 32949 0 0
T142 0 32866 0 0
T143 0 32510 0 0
T144 0 32197 0 0
T145 0 32024 0 0
T146 0 1 0 0
T147 0 34556 0 0
T148 69 0 0 0
T149 1151 0 0 0
T150 8865 0 0 0
T151 33099 0 0 0
T152 98933 0 0 0
T153 32792 0 0 0

gen_filter_match[1].MatchCheck10_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35023136 1577928 0 0
T9 33999 1 0 0
T10 1145 0 0 0
T11 7867 0 0 0
T12 101303 68697 0 0
T13 31858 0 0 0
T19 0 3 0 0
T24 818 0 0 0
T25 6471 0 0 0
T26 91 0 0 0
T27 1637 0 0 0
T28 1188 0 0 0
T56 0 34532 0 0
T138 0 1 0 0
T154 0 32325 0 0
T155 0 32971 0 0
T156 0 32746 0 0
T157 0 33981 0 0
T158 0 32777 0 0

gen_filter_match[1].MatchCheck11_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35023136 18863709 0 0
T9 33999 33902 0 0
T10 1145 0 0 0
T11 7867 0 0 0
T12 101303 32538 0 0
T13 31858 31791 0 0
T15 0 32545 0 0
T16 0 40808 0 0
T17 0 66456 0 0
T19 0 35552 0 0
T20 0 35684 0 0
T24 818 0 0 0
T25 6471 0 0 0
T26 91 0 0 0
T27 1637 0 0 0
T28 1188 0 0 0
T43 0 31508 0 0
T140 0 63172 0 0

gen_filter_match[2].MatchCheck00_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35023136 13491242 0 0
T1 103 4 0 0
T2 1129 1058 0 0
T3 1098 1041 0 0
T4 1048 979 0 0
T5 642 557 0 0
T6 5792 5734 0 0
T7 1208 1109 0 0
T21 91 6 0 0
T22 1639 5 0 0
T23 1605 6 0 0

gen_filter_match[2].MatchCheck01_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35023136 540056 0 0
T9 33999 33902 0 0
T10 1145 0 0 0
T11 7867 0 0 0
T12 101303 3 0 0
T13 31858 0 0 0
T24 818 0 0 0
T25 6471 0 0 0
T26 91 0 0 0
T27 1637 0 0 0
T28 1188 0 0 0
T32 0 2406 0 0
T146 0 1 0 0
T159 0 36290 0 0
T160 0 32697 0 0
T161 0 6767 0 0
T162 0 32330 0 0
T163 0 38629 0 0
T164 0 38105 0 0

gen_filter_match[2].MatchCheck10_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35023136 859638 0 0
T12 101303 5 0 0
T13 31858 0 0 0
T14 33725 0 0 0
T15 68835 0 0 0
T16 40863 0 0 0
T18 0 3 0 0
T25 6471 0 0 0
T26 91 0 0 0
T27 1637 0 0 0
T28 1188 0 0 0
T29 0 2 0 0
T51 0 85082 0 0
T57 0 34017 0 0
T58 8440 0 0 0
T107 0 1 0 0
T138 0 1 0 0
T142 0 33793 0 0
T153 0 1 0 0
T165 0 1 0 0

gen_filter_match[2].MatchCheck11_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35023136 19829930 0 0
T12 101303 67386 0 0
T13 31858 31791 0 0
T14 33725 33627 0 0
T15 68835 0 0 0
T16 40863 40808 0 0
T17 0 66456 0 0
T18 0 62902 0 0
T25 6471 0 0 0
T26 91 0 0 0
T27 1637 0 0 0
T28 1188 0 0 0
T41 0 74522 0 0
T43 0 31508 0 0
T58 8440 0 0 0
T132 0 32544 0 0
T140 0 31914 0 0

gen_filter_match[3].MatchCheck00_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35023136 12637875 0 0
T1 103 4 0 0
T2 1129 1058 0 0
T3 1098 1041 0 0
T4 1048 979 0 0
T5 642 557 0 0
T6 5792 5734 0 0
T7 1208 1109 0 0
T21 91 6 0 0
T22 1639 5 0 0
T23 1605 6 0 0

gen_filter_match[3].MatchCheck01_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35023136 387879 0 0
T12 101303 2 0 0
T13 31858 0 0 0
T14 33725 0 0 0
T15 68835 0 0 0
T16 40863 0 0 0
T25 6471 0 0 0
T26 91 0 0 0
T27 1637 0 0 0
T28 1188 0 0 0
T58 8440 0 0 0
T152 0 65122 0 0
T165 0 2 0 0
T166 0 2 0 0
T167 0 41497 0 0
T168 0 35051 0 0
T169 0 38761 0 0
T170 0 34601 0 0
T171 0 39544 0 0
T172 0 33489 0 0

gen_filter_match[3].MatchCheck10_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35023136 203476 0 0
T9 33999 1 0 0
T10 1145 0 0 0
T11 7867 0 0 0
T12 101303 2 0 0
T13 31858 0 0 0
T14 0 1 0 0
T18 0 2 0 0
T24 818 0 0 0
T25 6471 0 0 0
T26 91 0 0 0
T27 1637 0 0 0
T28 1188 0 0 0
T138 0 1 0 0
T142 0 1 0 0
T152 0 33754 0 0
T166 0 3 0 0
T173 0 36786 0 0
T174 0 1 0 0

gen_filter_match[3].MatchCheck11_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35023136 21491636 0 0
T9 33999 33902 0 0
T10 1145 0 0 0
T11 7867 0 0 0
T12 101303 68693 0 0
T13 31858 31791 0 0
T14 0 33626 0 0
T15 0 36208 0 0
T16 0 40808 0 0
T17 0 66456 0 0
T18 0 12368 0 0
T20 0 35684 0 0
T24 818 0 0 0
T25 6471 0 0 0
T26 91 0 0 0
T27 1637 0 0 0
T28 1188 0 0 0
T41 0 74522 0 0

gen_filter_match[4].MatchCheck00_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35023136 13273479 0 0
T1 103 4 0 0
T2 1129 1058 0 0
T3 1098 1041 0 0
T4 1048 979 0 0
T5 642 557 0 0
T6 5792 5734 0 0
T7 1208 1109 0 0
T21 91 6 0 0
T22 1639 5 0 0
T23 1605 6 0 0

gen_filter_match[4].MatchCheck01_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35023136 128772 0 0
T12 101303 2 0 0
T13 31858 0 0 0
T14 33725 0 0 0
T15 68835 0 0 0
T16 40863 0 0 0
T25 6471 0 0 0
T26 91 0 0 0
T27 1637 0 0 0
T28 1188 0 0 0
T58 8440 0 0 0
T157 0 1 0 0
T165 0 2 0 0
T166 0 3 0 0
T175 0 24701 0 0
T176 0 33648 0 0
T177 0 1 0 0
T178 0 1 0 0
T179 0 1 0 0
T180 0 32594 0 0

gen_filter_match[4].MatchCheck10_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35023136 89 0 0
T12 101303 2 0 0
T13 31858 0 0 0
T14 33725 1 0 0
T15 68835 0 0 0
T16 40863 0 0 0
T18 0 2 0 0
T25 6471 0 0 0
T26 91 0 0 0
T27 1637 0 0 0
T28 1188 0 0 0
T29 0 2 0 0
T58 8440 0 0 0
T138 0 1 0 0
T142 0 1 0 0
T153 0 2 0 0
T160 0 1 0 0
T166 0 3 0 0
T174 0 1 0 0

gen_filter_match[4].MatchCheck11_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35023136 21318526 0 0
T12 101303 34849 0 0
T13 31858 31791 0 0
T14 33725 33626 0 0
T15 68835 32545 0 0
T16 40863 40808 0 0
T17 0 66456 0 0
T18 0 12368 0 0
T20 0 35684 0 0
T25 6471 0 0 0
T26 91 0 0 0
T27 1637 0 0 0
T28 1188 0 0 0
T43 0 31508 0 0
T58 8440 0 0 0
T140 0 31258 0 0

gen_filter_match[5].MatchCheck00_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35023136 14371889 0 0
T1 103 4 0 0
T2 1129 1058 0 0
T3 1098 1041 0 0
T4 1048 979 0 0
T5 642 557 0 0
T6 5792 5734 0 0
T7 1208 1109 0 0
T21 91 6 0 0
T22 1639 5 0 0
T23 1605 6 0 0

gen_filter_match[5].MatchCheck01_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35023136 67064 0 0
T145 96332 0 0 0
T165 99368 2 0 0
T168 105415 0 0 0
T177 0 1 0 0
T178 0 1 0 0
T181 0 34277 0 0
T182 0 32777 0 0
T183 0 2 0 0
T184 0 4 0 0
T185 21329 0 0 0
T186 1200 0 0 0
T187 66414 0 0 0
T188 80202 0 0 0
T189 3609 0 0 0
T190 67701 0 0 0
T191 21827 0 0 0

gen_filter_match[5].MatchCheck10_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35023136 33635 0 0
T9 33999 2 0 0
T10 1145 0 0 0
T11 7867 0 0 0
T12 101303 2 0 0
T13 31858 0 0 0
T19 0 2 0 0
T24 818 0 0 0
T25 6471 0 0 0
T26 91 0 0 0
T27 1637 0 0 0
T28 1188 0 0 0
T29 0 3 0 0
T107 0 1 0 0
T138 0 1 0 0
T142 0 1 0 0
T160 0 1 0 0
T166 0 3 0 0
T192 0 1 0 0

gen_filter_match[5].MatchCheck11_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35023136 20248278 0 0
T9 33999 33901 0 0
T10 1145 0 0 0
T11 7867 0 0 0
T12 101303 101232 0 0
T13 31858 31791 0 0
T15 0 68753 0 0
T16 0 40808 0 0
T17 0 66456 0 0
T19 0 35551 0 0
T20 0 35684 0 0
T24 818 0 0 0
T25 6471 0 0 0
T26 91 0 0 0
T27 1637 0 0 0
T28 1188 0 0 0
T43 0 31508 0 0
T132 0 66063 0 0

gen_filter_match[6].MatchCheck00_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35023136 13776792 0 0
T1 103 4 0 0
T2 1129 1058 0 0
T3 1098 1041 0 0
T4 1048 979 0 0
T5 642 557 0 0
T6 5792 5734 0 0
T7 1208 1109 0 0
T21 91 6 0 0
T22 1639 5 0 0
T23 1605 6 0 0

gen_filter_match[6].MatchCheck01_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35023136 65715 0 0
T12 101303 2 0 0
T13 31858 0 0 0
T14 33725 0 0 0
T15 68835 0 0 0
T16 40863 0 0 0
T25 6471 0 0 0
T26 91 0 0 0
T27 1637 0 0 0
T28 1188 0 0 0
T58 8440 0 0 0
T166 0 2 0 0
T177 0 1 0 0
T182 0 1 0 0
T183 0 1 0 0
T184 0 3 0 0
T193 0 33225 0 0
T194 0 32478 0 0
T195 0 1 0 0
T196 0 1 0 0

gen_filter_match[6].MatchCheck10_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35023136 110 0 0
T9 33999 1 0 0
T10 1145 0 0 0
T11 7867 0 0 0
T12 101303 3 0 0
T13 31858 0 0 0
T18 0 4 0 0
T24 818 0 0 0
T25 6471 0 0 0
T26 91 0 0 0
T27 1637 0 0 0
T28 1188 0 0 0
T29 0 1 0 0
T107 0 1 0 0
T132 0 1 0 0
T142 0 1 0 0
T153 0 1 0 0
T166 0 3 0 0
T192 0 1 0 0

gen_filter_match[6].MatchCheck11_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35023136 20878249 0 0
T9 33999 33901 0 0
T10 1145 0 0 0
T11 7867 0 0 0
T12 101303 68693 0 0
T13 31858 31791 0 0
T15 0 36208 0 0
T16 0 40808 0 0
T17 0 66456 0 0
T18 0 62900 0 0
T20 0 35684 0 0
T24 818 0 0 0
T25 6471 0 0 0
T26 91 0 0 0
T27 1637 0 0 0
T28 1188 0 0 0
T43 0 31508 0 0
T140 0 63172 0 0

gen_filter_match[7].MatchCheck00_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35023136 14345814 0 0
T1 103 4 0 0
T2 1129 1058 0 0
T3 1098 1041 0 0
T4 1048 979 0 0
T5 642 557 0 0
T6 5792 5734 0 0
T7 1208 1109 0 0
T21 91 6 0 0
T22 1639 5 0 0
T23 1605 6 0 0

gen_filter_match[7].MatchCheck01_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35023136 179655 0 0
T29 77545 0 0 0
T49 64733 0 0 0
T132 66142 1 0 0
T149 1151 0 0 0
T150 8865 0 0 0
T151 33099 0 0 0
T152 98933 0 0 0
T153 32792 32722 0 0
T154 32419 0 0 0
T165 0 1 0 0
T166 0 2 0 0
T179 0 1 0 0
T180 0 1 0 0
T197 0 1 0 0
T198 0 1 0 0
T199 0 33420 0 0
T200 0 1 0 0
T201 719 0 0 0

gen_filter_match[7].MatchCheck10_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35023136 73922 0 0
T12 101303 2 0 0
T13 31858 0 0 0
T14 33725 0 0 0
T15 68835 0 0 0
T16 40863 0 0 0
T18 0 6 0 0
T25 6471 0 0 0
T26 91 0 0 0
T27 1637 0 0 0
T28 1188 0 0 0
T29 0 2 0 0
T58 8440 0 0 0
T157 0 1 0 0
T158 0 1 0 0
T160 0 1 0 0
T166 0 2 0 0
T174 0 1 0 0
T202 0 1 0 0
T203 0 1 0 0

gen_filter_match[7].MatchCheck11_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 35023136 20121475 0 0
T12 101303 32536 0 0
T13 31858 31791 0 0
T14 33725 0 0 0
T15 68835 36208 0 0
T16 40863 40808 0 0
T17 0 66456 0 0
T18 0 75265 0 0
T20 0 35684 0 0
T25 6471 0 0 0
T26 91 0 0 0
T27 1637 0 0 0
T28 1188 0 0 0
T43 0 31508 0 0
T58 8440 0 0 0
T132 0 33519 0 0
T140 0 63172 0 0