Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2031	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1908	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1993	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2066	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1956	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2085	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2045	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1974	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1959	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2041	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1943	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2095	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2138	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2040	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2157	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2203	0	0
adc_en_ctl_rd_A	2147483647	1837	0	0
adc_fsm_rst_rd_A	2147483647	1445	0	0
adc_intr_ctl_rd_A	2147483647	2002	0	0
adc_lp_sample_ctl_rd_A	2147483647	1490	0	0
adc_pd_ctl_rd_A	2147483647	1790	0	0
adc_sample_ctl_rd_A	2147483647	1317	0	0
adc_wakeup_ctl_rd_A	2147483647	1603	0	0
intr_enable_rd_A	2147483647	1896	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2031	0	0
T4	112168	19	0	0
T5	257089	0	0	0
T6	587346	0	0	0
T7	504135	0	0	0
T8	451663	0	0	0
T9	135446	0	0	0
T10	396183	0	0	0
T11	55375	0	0	0
T15	0	31	0	0
T21	10688	0	0	0
T22	701701	0	0	0
T28	0	18	0	0
T29	0	42	0	0
T30	0	18	0	0
T31	0	7	0	0
T32	0	31	0	0
T33	0	52	0	0
T34	0	19	0	0
T35	0	12	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1908	0	0
T4	112168	16	0	0
T5	257089	0	0	0
T6	587346	0	0	0
T7	504135	0	0	0
T8	451663	0	0	0
T9	135446	0	0	0
T10	396183	0	0	0
T11	55375	0	0	0
T15	0	23	0	0
T21	10688	0	0	0
T22	701701	0	0	0
T28	0	10	0	0
T29	0	46	0	0
T30	0	24	0	0
T31	0	6	0	0
T32	0	25	0	0
T33	0	30	0	0
T34	0	17	0	0
T35	0	11	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1993	0	0
T4	112168	24	0	0
T5	257089	0	0	0
T6	587346	0	0	0
T7	504135	0	0	0
T8	451663	0	0	0
T9	135446	0	0	0
T10	396183	0	0	0
T11	55375	0	0	0
T15	0	10	0	0
T21	10688	0	0	0
T22	701701	0	0	0
T28	0	14	0	0
T29	0	28	0	0
T30	0	20	0	0
T31	0	30	0	0
T32	0	31	0	0
T33	0	36	0	0
T34	0	15	0	0
T35	0	17	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2066	0	0
T4	112168	15	0	0
T5	257089	0	0	0
T6	587346	0	0	0
T7	504135	0	0	0
T8	451663	0	0	0
T9	135446	0	0	0
T10	396183	0	0	0
T11	55375	0	0	0
T15	0	9	0	0
T21	10688	0	0	0
T22	701701	0	0	0
T28	0	11	0	0
T29	0	34	0	0
T30	0	16	0	0
T31	0	16	0	0
T32	0	28	0	0
T33	0	56	0	0
T34	0	15	0	0
T35	0	12	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1956	0	0
T4	112168	10	0	0
T5	257089	0	0	0
T6	587346	0	0	0
T7	504135	0	0	0
T8	451663	0	0	0
T9	135446	0	0	0
T10	396183	0	0	0
T11	55375	0	0	0
T15	0	13	0	0
T21	10688	0	0	0
T22	701701	0	0	0
T28	0	18	0	0
T29	0	51	0	0
T30	0	32	0	0
T31	0	27	0	0
T32	0	22	0	0
T33	0	29	0	0
T34	0	15	0	0
T35	0	24	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2085	0	0
T4	112168	26	0	0
T5	257089	0	0	0
T6	587346	0	0	0
T7	504135	0	0	0
T8	451663	0	0	0
T9	135446	0	0	0
T10	396183	0	0	0
T11	55375	0	0	0
T15	0	30	0	0
T21	10688	0	0	0
T22	701701	0	0	0
T28	0	11	0	0
T29	0	35	0	0
T30	0	9	0	0
T31	0	31	0	0
T32	0	31	0	0
T33	0	38	0	0
T34	0	18	0	0
T35	0	10	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2045	0	0
T4	112168	26	0	0
T5	257089	0	0	0
T6	587346	0	0	0
T7	504135	0	0	0
T8	451663	0	0	0
T9	135446	0	0	0
T10	396183	0	0	0
T11	55375	0	0	0
T15	0	32	0	0
T21	10688	0	0	0
T22	701701	0	0	0
T28	0	7	0	0
T29	0	36	0	0
T30	0	9	0	0
T31	0	14	0	0
T32	0	27	0	0
T33	0	22	0	0
T34	0	23	0	0
T35	0	18	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1974	0	0
T4	112168	19	0	0
T5	257089	0	0	0
T6	587346	0	0	0
T7	504135	0	0	0
T8	451663	0	0	0
T9	135446	0	0	0
T10	396183	0	0	0
T11	55375	0	0	0
T15	0	15	0	0
T21	10688	0	0	0
T22	701701	0	0	0
T28	0	10	0	0
T29	0	28	0	0
T30	0	18	0	0
T31	0	10	0	0
T32	0	26	0	0
T33	0	36	0	0
T34	0	26	0	0
T35	0	20	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1959	0	0
T4	112168	25	0	0
T5	257089	0	0	0
T6	587346	0	0	0
T7	504135	0	0	0
T8	451663	0	0	0
T9	135446	0	0	0
T10	396183	0	0	0
T11	55375	0	0	0
T15	0	26	0	0
T21	10688	0	0	0
T22	701701	0	0	0
T28	0	21	0	0
T29	0	31	0	0
T30	0	17	0	0
T31	0	10	0	0
T32	0	33	0	0
T33	0	33	0	0
T34	0	14	0	0
T35	0	21	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2041	0	0
T4	112168	19	0	0
T5	257089	0	0	0
T6	587346	0	0	0
T7	504135	0	0	0
T8	451663	0	0	0
T9	135446	0	0	0
T10	396183	0	0	0
T11	55375	0	0	0
T15	0	11	0	0
T21	10688	0	0	0
T22	701701	0	0	0
T28	0	20	0	0
T29	0	33	0	0
T30	0	19	0	0
T31	0	12	0	0
T32	0	49	0	0
T33	0	45	0	0
T34	0	15	0	0
T35	0	14	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1943	0	0
T4	112168	18	0	0
T5	257089	0	0	0
T6	587346	0	0	0
T7	504135	0	0	0
T8	451663	0	0	0
T9	135446	0	0	0
T10	396183	0	0	0
T11	55375	0	0	0
T15	0	15	0	0
T21	10688	0	0	0
T22	701701	0	0	0
T28	0	6	0	0
T29	0	36	0	0
T30	0	17	0	0
T31	0	20	0	0
T32	0	28	0	0
T33	0	20	0	0
T34	0	22	0	0
T35	0	22	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2095	0	0
T4	112168	11	0	0
T5	257089	0	0	0
T6	587346	0	0	0
T7	504135	0	0	0
T8	451663	0	0	0
T9	135446	0	0	0
T10	396183	0	0	0
T11	55375	0	0	0
T15	0	18	0	0
T21	10688	0	0	0
T22	701701	0	0	0
T28	0	6	0	0
T29	0	55	0	0
T30	0	26	0	0
T31	0	38	0	0
T32	0	35	0	0
T33	0	38	0	0
T34	0	20	0	0
T35	0	14	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2138	0	0
T4	112168	22	0	0
T5	257089	0	0	0
T6	587346	0	0	0
T7	504135	0	0	0
T8	451663	0	0	0
T9	135446	0	0	0
T10	396183	0	0	0
T11	55375	0	0	0
T15	0	14	0	0
T21	10688	0	0	0
T22	701701	0	0	0
T28	0	18	0	0
T29	0	31	0	0
T30	0	19	0	0
T31	0	26	0	0
T32	0	35	0	0
T33	0	43	0	0
T34	0	17	0	0
T35	0	14	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2040	0	0
T4	112168	14	0	0
T5	257089	0	0	0
T6	587346	0	0	0
T7	504135	0	0	0
T8	451663	0	0	0
T9	135446	0	0	0
T10	396183	0	0	0
T11	55375	0	0	0
T15	0	17	0	0
T21	10688	0	0	0
T22	701701	0	0	0
T28	0	13	0	0
T29	0	31	0	0
T30	0	15	0	0
T31	0	28	0	0
T32	0	52	0	0
T33	0	51	0	0
T34	0	25	0	0
T35	0	15	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2157	0	0
T4	112168	15	0	0
T5	257089	0	0	0
T6	587346	0	0	0
T7	504135	0	0	0
T8	451663	0	0	0
T9	135446	0	0	0
T10	396183	0	0	0
T11	55375	0	0	0
T15	0	8	0	0
T21	10688	0	0	0
T22	701701	0	0	0
T28	0	14	0	0
T29	0	44	0	0
T30	0	19	0	0
T31	0	31	0	0
T32	0	43	0	0
T33	0	31	0	0
T34	0	22	0	0
T35	0	19	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2203	0	0
T4	112168	26	0	0
T5	257089	0	0	0
T6	587346	0	0	0
T7	504135	0	0	0
T8	451663	0	0	0
T9	135446	0	0	0
T10	396183	0	0	0
T11	55375	0	0	0
T15	0	17	0	0
T21	10688	0	0	0
T22	701701	0	0	0
T28	0	22	0	0
T29	0	31	0	0
T30	0	27	0	0
T31	0	55	0	0
T32	0	24	0	0
T33	0	32	0	0
T34	0	16	0	0
T35	0	22	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1837	0	0
T4	112168	16	0	0
T5	257089	0	0	0
T6	587346	0	0	0
T7	504135	0	0	0
T8	451663	0	0	0
T9	135446	0	0	0
T10	396183	0	0	0
T11	55375	0	0	0
T15	0	10	0	0
T21	10688	0	0	0
T22	701701	0	0	0
T28	0	15	0	0
T29	0	32	0	0
T30	0	17	0	0
T31	0	24	0	0
T32	0	45	0	0
T33	0	28	0	0
T34	0	22	0	0
T35	0	23	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1445	0	0
T4	112168	26	0	0
T5	257089	0	0	0
T6	587346	0	0	0
T7	504135	0	0	0
T8	451663	0	0	0
T9	135446	0	0	0
T10	396183	0	0	0
T11	55375	0	0	0
T15	0	13	0	0
T21	10688	0	0	0
T22	701701	0	0	0
T28	0	2	0	0
T29	0	42	0	0
T30	0	18	0	0
T31	0	14	0	0
T32	0	31	0	0
T33	0	27	0	0
T34	0	23	0	0
T35	0	20	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2002	0	0
T4	112168	24	0	0
T5	257089	0	0	0
T6	587346	0	0	0
T7	504135	0	0	0
T8	451663	0	0	0
T9	135446	0	0	0
T10	396183	0	0	0
T11	55375	0	0	0
T15	0	12	0	0
T21	10688	0	0	0
T22	701701	0	0	0
T28	0	13	0	0
T29	0	40	0	0
T30	0	11	0	0
T31	0	18	0	0
T32	0	44	0	0
T33	0	37	0	0
T34	0	30	0	0
T35	0	8	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1490	0	0
T4	112168	15	0	0
T5	257089	0	0	0
T6	587346	0	0	0
T7	504135	0	0	0
T8	451663	0	0	0
T9	135446	0	0	0
T10	396183	0	0	0
T11	55375	0	0	0
T15	0	22	0	0
T21	10688	0	0	0
T22	701701	0	0	0
T28	0	8	0	0
T29	0	32	0	0
T30	0	26	0	0
T31	0	24	0	0
T32	0	33	0	0
T33	0	49	0	0
T34	0	18	0	0
T35	0	25	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1790	0	0
T4	112168	24	0	0
T5	257089	0	0	0
T6	587346	0	0	0
T7	504135	0	0	0
T8	451663	0	0	0
T9	135446	0	0	0
T10	396183	0	0	0
T11	55375	0	0	0
T15	0	12	0	0
T21	10688	0	0	0
T22	701701	0	0	0
T28	0	13	0	0
T29	0	37	0	0
T30	0	22	0	0
T31	0	33	0	0
T32	0	24	0	0
T33	0	34	0	0
T34	0	27	0	0
T35	0	8	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1317	0	0
T4	112168	12	0	0
T5	257089	0	0	0
T6	587346	0	0	0
T7	504135	0	0	0
T8	451663	0	0	0
T9	135446	0	0	0
T10	396183	0	0	0
T11	55375	0	0	0
T15	0	10	0	0
T21	10688	0	0	0
T22	701701	0	0	0
T28	0	10	0	0
T29	0	29	0	0
T30	0	18	0	0
T31	0	24	0	0
T32	0	39	0	0
T33	0	38	0	0
T34	0	12	0	0
T35	0	24	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1603	0	0
T4	112168	29	0	0
T5	257089	0	0	0
T6	587346	0	0	0
T7	504135	0	0	0
T8	451663	0	0	0
T9	135446	0	0	0
T10	396183	0	0	0
T11	55375	0	0	0
T15	0	24	0	0
T21	10688	0	0	0
T22	701701	0	0	0
T28	0	13	0	0
T29	0	37	0	0
T30	0	11	0	0
T31	0	19	0	0
T32	0	35	0	0
T33	0	29	0	0
T34	0	14	0	0
T35	0	24	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1896	0	0
T4	112168	35	0	0
T5	257089	0	0	0
T6	587346	0	0	0
T7	504135	0	0	0
T8	451663	0	0	0
T9	135446	0	0	0
T10	396183	0	0	0
T11	55375	0	0	0
T15	0	25	0	0
T21	10688	0	0	0
T22	701701	0	0	0
T25	0	21	0	0
T28	0	30	0	0
T29	0	41	0	0
T30	0	20	0	0
T31	0	14	0	0
T32	0	62	0	0
T33	0	35	0	0
T36	0	11	0	0