AES/MASKED Simulation Results

Friday May 19 2023 07:05:15 UTC

GitHub Revision: `30db5a999`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 2235272161

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	63.989us	1	1	100.00
V1	smoke	aes_smoke	8.000s	599.888us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	194.143us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	134.424us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	1.009ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	74.305us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	61.019us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	134.424us	20	20	100.00
		aes_csr_aliasing	5.000s	74.305us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	8.000s	599.888us	50	50	100.00
		aes_config_error	17.000s	1.830ms	50	50	100.00
		aes_stress	2.500m	3.655ms	50	50	100.00
V2	key_length	aes_smoke	8.000s	599.888us	50	50	100.00
		aes_config_error	17.000s	1.830ms	50	50	100.00
		aes_stress	2.500m	3.655ms	50	50	100.00
V2	back2back	aes_stress	2.500m	3.655ms	50	50	100.00
		aes_b2b	37.000s	413.763us	50	50	100.00
V2	backpressure	aes_stress	2.500m	3.655ms	50	50	100.00
V2	multi_message	aes_smoke	8.000s	599.888us	50	50	100.00
		aes_config_error	17.000s	1.830ms	50	50	100.00
		aes_stress	2.500m	3.655ms	50	50	100.00
		aes_alert_reset	17.000s	2.655ms	50	50	100.00
V2	failure_test	aes_config_error	17.000s	1.830ms	50	50	100.00
		aes_alert_reset	17.000s	2.655ms	50	50	100.00
		aes_man_cfg_err	5.000s	194.761us	50	50	100.00
V2	trigger_clear_test	aes_clear	31.000s	1.843ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	175.470us	1	1	100.00
V2	reset_recovery	aes_alert_reset	17.000s	2.655ms	50	50	100.00
V2	stress	aes_stress	2.500m	3.655ms	50	50	100.00
V2	sideload	aes_stress	2.500m	3.655ms	50	50	100.00
		aes_sideload	13.000s	322.549us	50	50	100.00
V2	deinitialization	aes_deinit	16.000s	767.225us	50	50	100.00
V2	alert_test	aes_alert_test	5.000s	59.531us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	82.966us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	82.966us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	194.143us	5	5	100.00
		aes_csr_rw	4.000s	134.424us	20	20	100.00
		aes_csr_aliasing	5.000s	74.305us	5	5	100.00
		aes_same_csr_outstanding	4.000s	332.034us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	194.143us	5	5	100.00
		aes_csr_rw	4.000s	134.424us	20	20	100.00
		aes_csr_aliasing	5.000s	74.305us	5	5	100.00
		aes_same_csr_outstanding	4.000s	332.034us	20	20	100.00
V2		TOTAL			491	491	100.00
V2S	reseeding	aes_reseed	2.283m	1.758ms	50	50	100.00
V2S	fault_inject	aes_fi	22.000s	899.197us	50	50	100.00
		aes_control_fi	53.000s	10.024ms	283	300	94.33
		aes_cipher_fi	45.000s	10.007ms	337	350	96.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	77.094us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	77.094us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	77.094us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	77.094us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	588.526us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	1.302ms	5	5	100.00
		aes_tl_intg_err	6.000s	539.923us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	539.923us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	17.000s	2.655ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	77.094us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	8.000s	599.888us	50	50	100.00
		aes_stress	2.500m	3.655ms	50	50	100.00
		aes_alert_reset	17.000s	2.655ms	50	50	100.00
		aes_core_fi	1.450m	10.087ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	77.094us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_stress	2.500m	3.655ms	50	50	100.00
		aes_readability	5.000s	54.764us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	2.500m	3.655ms	50	50	100.00
		aes_sideload	13.000s	322.549us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	54.764us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	54.764us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	54.764us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	54.764us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	54.764us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	2.500m	3.655ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	2.500m	3.655ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	22.000s	899.197us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	22.000s	899.197us	50	50	100.00
		aes_control_fi	53.000s	10.024ms	283	300	94.33
		aes_cipher_fi	45.000s	10.007ms	337	350	96.29
		aes_ctr_fi	5.000s	167.031us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	22.000s	899.197us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	22.000s	899.197us	50	50	100.00
		aes_control_fi	53.000s	10.024ms	283	300	94.33
		aes_cipher_fi	45.000s	10.007ms	337	350	96.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	45.000s	10.007ms	337	350	96.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	22.000s	899.197us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	22.000s	899.197us	50	50	100.00
		aes_control_fi	53.000s	10.024ms	283	300	94.33
		aes_ctr_fi	5.000s	167.031us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	22.000s	899.197us	50	50	100.00
		aes_control_fi	53.000s	10.024ms	283	300	94.33
		aes_cipher_fi	45.000s	10.007ms	337	350	96.29
		aes_ctr_fi	5.000s	167.031us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	17.000s	2.655ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	22.000s	899.197us	50	50	100.00
		aes_control_fi	53.000s	10.024ms	283	300	94.33
		aes_cipher_fi	45.000s	10.007ms	337	350	96.29
		aes_ctr_fi	5.000s	167.031us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	22.000s	899.197us	50	50	100.00
		aes_control_fi	53.000s	10.024ms	283	300	94.33
		aes_cipher_fi	45.000s	10.007ms	337	350	96.29
		aes_ctr_fi	5.000s	167.031us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	22.000s	899.197us	50	50	100.00
		aes_control_fi	53.000s	10.024ms	283	300	94.33
		aes_ctr_fi	5.000s	167.031us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	22.000s	899.197us	50	50	100.00
		aes_control_fi	53.000s	10.024ms	283	300	94.33
		aes_cipher_fi	45.000s	10.007ms	337	350	96.29
V2S		TOTAL			953	985	96.75
V3		TOTAL			0	0	--
		TOTAL			1550	1582	97.98

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	12	12	12	100.00
V2S	11	11	8	72.73

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.44	98.99	97.49	99.37	95.89	95.60	97.78	98.67	92.70

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 21 failures:
- Test aes_control_fi has 14 failures.
  - 3.aes_control_fi.58946386
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_control_fi/latest/run.log
```
  Job ID: smart:bb0f96c8-65ff-4cca-aa5b-c6abc63fd68a
```
  - 10.aes_control_fi.1489821421
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/10.aes_control_fi/latest/run.log
```
  Job ID: smart:a69eac44-ca45-40a7-9c90-4f9cc6e99f49
```
  - ... and 12 more failures.
- Test aes_cipher_fi has 7 failures.
  - 46.aes_cipher_fi.361497012
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/46.aes_cipher_fi/latest/run.log
```
  Job ID: smart:827d12a0-4c48-4a43-a7f4-494d25051be5
```
  - 67.aes_cipher_fi.125899206
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/67.aes_cipher_fi/latest/run.log
```
  Job ID: smart:379a30a0-3725-4fc2-b527-5fafe752efb8
```
  - ... and 5 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 6 failures:

Test aes_cipher_fi has 6 failures.

69.aes_cipher_fi.3770814621
Line 278, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/69.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10010429103 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010429103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

153.aes_cipher_fi.1011233280
Line 278, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/153.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10015888078 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015888078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 3 failures:

Test aes_control_fi has 3 failures.

193.aes_control_fi.1679918788
Line 280, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/193.aes_control_fi/latest/run.log

  UVM_FATAL @ 10024181555 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10024181555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

197.aes_control_fi.1955054288
Line 291, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/197.aes_control_fi/latest/run.log

  UVM_FATAL @ 10017433660 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017433660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:

Test aes_core_fi has 2 failures.

52.aes_core_fi.2866069948
Line 273, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/52.aes_core_fi/latest/run.log

  UVM_FATAL @ 10086795575 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10086795575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

62.aes_core_fi.2215796805
Line 287, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/62.aes_core_fi/latest/run.log

  UVM_FATAL @ 10011171763 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011171763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---