AES/MASKED Simulation Results

Wednesday October 04 2023 19:02:35 UTC

GitHub Revision: `1522c8119`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 1107990535

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	86.234us	1	1	100.00
V1	smoke	aes_smoke	15.000s	125.549us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	86.257us	5	5	100.00
V1	csr_rw	aes_csr_rw	9.000s	80.468us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	12.000s	854.638us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	9.000s	134.593us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	7.000s	68.402us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	9.000s	80.468us	20	20	100.00
		aes_csr_aliasing	9.000s	134.593us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	15.000s	125.549us	50	50	100.00
		aes_config_error	24.000s	735.352us	50	50	100.00
		aes_stress	24.000s	2.678ms	50	50	100.00
V2	key_length	aes_smoke	15.000s	125.549us	50	50	100.00
		aes_config_error	24.000s	735.352us	50	50	100.00
		aes_stress	24.000s	2.678ms	50	50	100.00
V2	back2back	aes_stress	24.000s	2.678ms	50	50	100.00
		aes_b2b	33.000s	609.499us	50	50	100.00
V2	backpressure	aes_stress	24.000s	2.678ms	50	50	100.00
V2	multi_message	aes_smoke	15.000s	125.549us	50	50	100.00
		aes_config_error	24.000s	735.352us	50	50	100.00
		aes_stress	24.000s	2.678ms	50	50	100.00
		aes_alert_reset	51.000s	2.837ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	17.000s	132.355us	50	50	100.00
		aes_config_error	24.000s	735.352us	50	50	100.00
		aes_alert_reset	51.000s	2.837ms	50	50	100.00
V2	trigger_clear_test	aes_clear	19.000s	290.642us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	292.749us	1	1	100.00
V2	reset_recovery	aes_alert_reset	51.000s	2.837ms	50	50	100.00
V2	stress	aes_stress	24.000s	2.678ms	50	50	100.00
V2	sideload	aes_stress	24.000s	2.678ms	50	50	100.00
		aes_sideload	19.000s	1.061ms	50	50	100.00
V2	deinitialization	aes_deinit	12.000s	176.342us	50	50	100.00
V2	stress_all	aes_stress_all	1.217m	5.599ms	10	10	100.00
V2	alert_test	aes_alert_test	13.000s	62.416us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	16.000s	351.672us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	16.000s	351.672us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	86.257us	5	5	100.00
		aes_csr_rw	9.000s	80.468us	20	20	100.00
		aes_csr_aliasing	9.000s	134.593us	5	5	100.00
		aes_same_csr_outstanding	6.000s	110.289us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	86.257us	5	5	100.00
		aes_csr_rw	9.000s	80.468us	20	20	100.00
		aes_csr_aliasing	9.000s	134.593us	5	5	100.00
		aes_same_csr_outstanding	6.000s	110.289us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	37.000s	4.643ms	50	50	100.00
V2S	fault_inject	aes_fi	23.000s	3.846ms	50	50	100.00
		aes_control_fi	55.000s	10.007ms	277	300	92.33
		aes_cipher_fi	52.000s	10.009ms	341	350	97.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	14.000s	90.708us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	14.000s	90.708us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	14.000s	90.708us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	14.000s	90.708us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	185.545us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	11.000s	978.647us	5	5	100.00
		aes_tl_intg_err	9.000s	587.143us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	587.143us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	51.000s	2.837ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	14.000s	90.708us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	15.000s	125.549us	50	50	100.00
		aes_stress	24.000s	2.678ms	50	50	100.00
		aes_alert_reset	51.000s	2.837ms	50	50	100.00
		aes_core_fi	13.000s	10.047ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	14.000s	90.708us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	14.000s	77.308us	50	50	100.00
		aes_stress	24.000s	2.678ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	24.000s	2.678ms	50	50	100.00
		aes_sideload	19.000s	1.061ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	14.000s	77.308us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	14.000s	77.308us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	14.000s	77.308us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	14.000s	77.308us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	14.000s	77.308us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	24.000s	2.678ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	24.000s	2.678ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	23.000s	3.846ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	23.000s	3.846ms	50	50	100.00
		aes_control_fi	55.000s	10.007ms	277	300	92.33
		aes_cipher_fi	52.000s	10.009ms	341	350	97.43
		aes_ctr_fi	12.000s	54.651us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	23.000s	3.846ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	23.000s	3.846ms	50	50	100.00
		aes_control_fi	55.000s	10.007ms	277	300	92.33
		aes_cipher_fi	52.000s	10.009ms	341	350	97.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	52.000s	10.009ms	341	350	97.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	23.000s	3.846ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	23.000s	3.846ms	50	50	100.00
		aes_control_fi	55.000s	10.007ms	277	300	92.33
		aes_ctr_fi	12.000s	54.651us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	23.000s	3.846ms	50	50	100.00
		aes_control_fi	55.000s	10.007ms	277	300	92.33
		aes_cipher_fi	52.000s	10.009ms	341	350	97.43
		aes_ctr_fi	12.000s	54.651us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	51.000s	2.837ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	23.000s	3.846ms	50	50	100.00
		aes_control_fi	55.000s	10.007ms	277	300	92.33
		aes_cipher_fi	52.000s	10.009ms	341	350	97.43
		aes_ctr_fi	12.000s	54.651us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	23.000s	3.846ms	50	50	100.00
		aes_control_fi	55.000s	10.007ms	277	300	92.33
		aes_cipher_fi	52.000s	10.009ms	341	350	97.43
		aes_ctr_fi	12.000s	54.651us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	23.000s	3.846ms	50	50	100.00
		aes_control_fi	55.000s	10.007ms	277	300	92.33
		aes_ctr_fi	12.000s	54.651us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	23.000s	3.846ms	50	50	100.00
		aes_control_fi	55.000s	10.007ms	277	300	92.33
		aes_cipher_fi	52.000s	10.009ms	341	350	97.43
V2S		TOTAL			952	985	96.65
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.033m	3.026ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1559	1602	97.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.48	98.96	97.38	99.41	95.72	95.60	100.00	98.97	97.77

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 23 failures:
- Test aes_control_fi has 19 failures.
  - 8.aes_control_fi.3923735562
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_control_fi/latest/run.log
```
  Job ID: smart:c5830542-d3e7-4e94-805e-49489797a1a6
```
  - 38.aes_control_fi.3390361110
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/38.aes_control_fi/latest/run.log
```
  Job ID: smart:e6dce92c-e943-44f8-bb17-7f2296fb6729
```
  - ... and 17 more failures.
- Test aes_cipher_fi has 4 failures.
  - 34.aes_cipher_fi.2009655672
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/34.aes_cipher_fi/latest/run.log
```
  Job ID: smart:e008e5eb-144f-4b98-856d-d027055951b0
```
  - 108.aes_cipher_fi.1471230853
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/108.aes_cipher_fi/latest/run.log
```
  Job ID: smart:c13f5549-a998-4d7a-8034-93d5723d18f6
```
  - ... and 2 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.2739244198
Line 805, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 512729120 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 512729120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.634009191
Line 692, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1617484779 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1617484779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 5 failures:

Test aes_cipher_fi has 5 failures.

42.aes_cipher_fi.3470868497
Line 270, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/42.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10018594234 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018594234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

46.aes_cipher_fi.162272462
Line 282, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/46.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10015061950 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015061950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 4 failures:

Test aes_control_fi has 4 failures.

88.aes_control_fi.4162425136
Line 275, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/88.aes_control_fi/latest/run.log

  UVM_FATAL @ 10007410264 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007410264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

153.aes_control_fi.3202899993
Line 284, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/153.aes_control_fi/latest/run.log

  UVM_FATAL @ 10138938657 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10138938657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_all_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.757913083
    Line 246, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  16158248 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_all_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  16158248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.2140745675
    Line 440, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 909859405 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 909859405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 8.aes_stress_all_with_rand_reset.1080283343
    Line 1577, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1953353918 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1953353918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 49.aes_core_fi.2898288061
    Line 282, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/49.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10047127691 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10047127691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```