AES/MASKED Simulation Results

Wednesday December 27 2023 20:02:24 UTC

GitHub Revision: `0c759b93ab`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 85416116840666724748485424200434981761468351851988553961117902923833034512693

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	59.811us	1	1	100.00
V1	smoke	aes_smoke	12.000s	627.970us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	63.593us	5	5	100.00
V1	csr_rw	aes_csr_rw	11.000s	102.668us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	16.000s	2.299ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	574.018us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	10.000s	77.643us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	11.000s	102.668us	20	20	100.00
		aes_csr_aliasing	6.000s	574.018us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	12.000s	627.970us	50	50	100.00
		aes_config_error	31.000s	1.177ms	50	50	100.00
		aes_stress	15.000s	366.004us	50	50	100.00
V2	key_length	aes_smoke	12.000s	627.970us	50	50	100.00
		aes_config_error	31.000s	1.177ms	50	50	100.00
		aes_stress	15.000s	366.004us	50	50	100.00
V2	back2back	aes_stress	15.000s	366.004us	50	50	100.00
		aes_b2b	37.000s	440.306us	50	50	100.00
V2	backpressure	aes_stress	15.000s	366.004us	50	50	100.00
V2	multi_message	aes_smoke	12.000s	627.970us	50	50	100.00
		aes_config_error	31.000s	1.177ms	50	50	100.00
		aes_stress	15.000s	366.004us	50	50	100.00
		aes_alert_reset	14.000s	906.788us	50	50	100.00
V2	failure_test	aes_man_cfg_err	4.000s	80.321us	50	50	100.00
		aes_config_error	31.000s	1.177ms	50	50	100.00
		aes_alert_reset	14.000s	906.788us	50	50	100.00
V2	trigger_clear_test	aes_clear	1.117m	2.270ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	308.204us	1	1	100.00
V2	reset_recovery	aes_alert_reset	14.000s	906.788us	50	50	100.00
V2	stress	aes_stress	15.000s	366.004us	50	50	100.00
V2	sideload	aes_stress	15.000s	366.004us	50	50	100.00
		aes_sideload	11.000s	302.136us	50	50	100.00
V2	deinitialization	aes_deinit	12.000s	355.876us	50	50	100.00
V2	stress_all	aes_stress_all	2.217m	8.547ms	10	10	100.00
V2	alert_test	aes_alert_test	5.000s	198.575us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	210.925us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	210.925us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	63.593us	5	5	100.00
		aes_csr_rw	11.000s	102.668us	20	20	100.00
		aes_csr_aliasing	6.000s	574.018us	5	5	100.00
		aes_same_csr_outstanding	13.000s	139.704us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	63.593us	5	5	100.00
		aes_csr_rw	11.000s	102.668us	20	20	100.00
		aes_csr_aliasing	6.000s	574.018us	5	5	100.00
		aes_same_csr_outstanding	13.000s	139.704us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	16.000s	210.807us	50	50	100.00
V2S	fault_inject	aes_fi	31.000s	1.089ms	50	50	100.00
		aes_control_fi	44.000s	10.009ms	278	300	92.67
		aes_cipher_fi	30.000s	10.013ms	342	350	97.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	10.000s	85.337us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	10.000s	85.337us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	10.000s	85.337us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	10.000s	85.337us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	15.000s	543.483us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	13.000s	1.037ms	5	5	100.00
		aes_tl_intg_err	10.000s	301.006us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	10.000s	301.006us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	14.000s	906.788us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	10.000s	85.337us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	12.000s	627.970us	50	50	100.00
		aes_stress	15.000s	366.004us	50	50	100.00
		aes_alert_reset	14.000s	906.788us	50	50	100.00
		aes_core_fi	49.000s	10.006ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	10.000s	85.337us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	331.710us	50	50	100.00
		aes_stress	15.000s	366.004us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	15.000s	366.004us	50	50	100.00
		aes_sideload	11.000s	302.136us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	331.710us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	331.710us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	331.710us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	331.710us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	331.710us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	15.000s	366.004us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	15.000s	366.004us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	31.000s	1.089ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	31.000s	1.089ms	50	50	100.00
		aes_control_fi	44.000s	10.009ms	278	300	92.67
		aes_cipher_fi	30.000s	10.013ms	342	350	97.71
		aes_ctr_fi	4.000s	100.867us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	31.000s	1.089ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	31.000s	1.089ms	50	50	100.00
		aes_control_fi	44.000s	10.009ms	278	300	92.67
		aes_cipher_fi	30.000s	10.013ms	342	350	97.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	30.000s	10.013ms	342	350	97.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	31.000s	1.089ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	31.000s	1.089ms	50	50	100.00
		aes_control_fi	44.000s	10.009ms	278	300	92.67
		aes_ctr_fi	4.000s	100.867us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	31.000s	1.089ms	50	50	100.00
		aes_control_fi	44.000s	10.009ms	278	300	92.67
		aes_cipher_fi	30.000s	10.013ms	342	350	97.71
		aes_ctr_fi	4.000s	100.867us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	14.000s	906.788us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	31.000s	1.089ms	50	50	100.00
		aes_control_fi	44.000s	10.009ms	278	300	92.67
		aes_cipher_fi	30.000s	10.013ms	342	350	97.71
		aes_ctr_fi	4.000s	100.867us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	31.000s	1.089ms	50	50	100.00
		aes_control_fi	44.000s	10.009ms	278	300	92.67
		aes_cipher_fi	30.000s	10.013ms	342	350	97.71
		aes_ctr_fi	4.000s	100.867us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	31.000s	1.089ms	50	50	100.00
		aes_control_fi	44.000s	10.009ms	278	300	92.67
		aes_ctr_fi	4.000s	100.867us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	31.000s	1.089ms	50	50	100.00
		aes_control_fi	44.000s	10.009ms	278	300	92.67
		aes_cipher_fi	30.000s	10.013ms	342	350	97.71
V2S		TOTAL			953	985	96.75
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	7.017m	13.309ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1560	1602	97.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.54	99.00	97.49	99.45	95.76	95.66	100.00	98.97	98.38

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 23 failures:
- Test aes_control_fi has 18 failures.
  - 18.aes_control_fi.106852679950991740246721117749909311221114210394788086270253522637388571682688
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/18.aes_control_fi/latest/run.log
```
  Job ID: smart:f2ef2553-6ec6-4c75-8bf5-39b57dba1f5c
```
  - 48.aes_control_fi.74346157488127414510881790957151693537048469991490490130584316536370390415488
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/48.aes_control_fi/latest/run.log
```
  Job ID: smart:8b5f42f0-daf4-4777-9f75-5c6480e6c47b
```
  - ... and 16 more failures.
- Test aes_cipher_fi has 5 failures.
  - 159.aes_cipher_fi.109855152351316812810804619545586128870719888119379764283069109082103645025592
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/159.aes_cipher_fi/latest/run.log
```
  Job ID: smart:df3773a1-e8a0-4758-b3a7-dfd266475271
```
  - 222.aes_cipher_fi.37249162590670755870637519231066701930961587775699844531250527649999790792763
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/222.aes_cipher_fi/latest/run.log
```
  Job ID: smart:bfe9e63c-3971-432e-946b-73418a3f557f
```
  - ... and 3 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

1.aes_stress_all_with_rand_reset.108647948215605395675853569339587000640805241227793876462411404131437066172176
Line 1027, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7833335740 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 7833335740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.67876129758213718491593105180373679123326946185718271269052026446413299362130
Line 1043, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2848774746 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2848774746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_control_fi has 4 failures.
  - 55.aes_control_fi.93925956936812520509645163527189849765040169934558168212911428992066628400209
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/55.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011872460 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011872460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 88.aes_control_fi.27414084016175200031252847817774546293153749923085412923980399250417913194176
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/88.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10032527435 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10032527435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_cipher_fi has 3 failures.
  - 132.aes_cipher_fi.10587680454999487139388591042323377208340596040097600227082864505545769384846
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/132.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10134296652 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10134296652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 178.aes_cipher_fi.102687119207987163646229803492634045923957836864914673971376500966252166024765
    Line 330, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/178.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10076221907 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10076221907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 0.aes_stress_all_with_rand_reset.25796694868046711319637839714198924043079443667321824753169078155267781905822
    Line 1565, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2782109992 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2782109992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:520) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.31600467230322816652703752304031017372855264699814582076113657068017152243829
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 201770559 ps: (cip_base_vseq.sv:520) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @ 201770559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 22.aes_core_fi.43428963043165294235818996808026715010845734995363974046531769952549123176048
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/22.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10005892678 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005892678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_cipher_core.sv,825): Assertion AesSecCmKeyMaskingInitialPrngUpdateSubBytes has failed (* cycles, starting * PS) has 1 failures:

Test aes_core_fi has 1 failures.

64.aes_core_fi.13652925953199328537097493574662319841791416542212973522785319088583308290690
Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/64.aes_core_fi/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_core.sv,825): (time 8774079 PS) Assertion tb.dut.u_aes_core.u_aes_cipher_core.gen_sec_cm_key_masking_svas.AesSecCmKeyMaskingInitialPrngUpdateSubBytes has failed (2 cycles, starting 8754079 PS)
  UVM_ERROR @   8774079 ps: (aes_cipher_core.sv:825) [ASSERT FAILED] AesSecCmKeyMaskingInitialPrngUpdateSubBytes
  UVM_INFO @   8774079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---