AES/UNMASKED Simulation Results

Friday May 19 2023 07:05:15 UTC

GitHub Revision: `30db5a999`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 2235272161

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	85.917us	1	1	100.00
V1	smoke	aes_smoke	6.000s	131.266us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	61.698us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	122.200us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	12.000s	3.142ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	334.086us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	373.746us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	122.200us	20	20	100.00
		aes_csr_aliasing	5.000s	334.086us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	6.000s	131.266us	50	50	100.00
		aes_config_error	6.000s	575.465us	50	50	100.00
		aes_stress	40.000s	4.335ms	50	50	100.00
V2	key_length	aes_smoke	6.000s	131.266us	50	50	100.00
		aes_config_error	6.000s	575.465us	50	50	100.00
		aes_stress	40.000s	4.335ms	50	50	100.00
V2	back2back	aes_stress	40.000s	4.335ms	50	50	100.00
		aes_b2b	13.000s	148.445us	50	50	100.00
V2	backpressure	aes_stress	40.000s	4.335ms	50	50	100.00
V2	multi_message	aes_smoke	6.000s	131.266us	50	50	100.00
		aes_config_error	6.000s	575.465us	50	50	100.00
		aes_stress	40.000s	4.335ms	50	50	100.00
		aes_alert_reset	6.000s	97.434us	50	50	100.00
V2	failure_test	aes_config_error	6.000s	575.465us	50	50	100.00
		aes_alert_reset	6.000s	97.434us	50	50	100.00
		aes_man_cfg_err	4.000s	55.451us	50	50	100.00
V2	trigger_clear_test	aes_clear	7.000s	451.291us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	306.173us	1	1	100.00
V2	reset_recovery	aes_alert_reset	6.000s	97.434us	50	50	100.00
V2	stress	aes_stress	40.000s	4.335ms	50	50	100.00
V2	sideload	aes_stress	40.000s	4.335ms	50	50	100.00
		aes_sideload	6.000s	123.088us	50	50	100.00
V2	deinitialization	aes_deinit	6.000s	64.649us	50	50	100.00
V2	alert_test	aes_alert_test	5.000s	124.325us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	217.586us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	217.586us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	61.698us	5	5	100.00
		aes_csr_rw	3.000s	122.200us	20	20	100.00
		aes_csr_aliasing	5.000s	334.086us	5	5	100.00
		aes_same_csr_outstanding	4.000s	144.141us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	61.698us	5	5	100.00
		aes_csr_rw	3.000s	122.200us	20	20	100.00
		aes_csr_aliasing	5.000s	334.086us	5	5	100.00
		aes_same_csr_outstanding	4.000s	144.141us	20	20	100.00
V2		TOTAL			491	491	100.00
V2S	reseeding	aes_reseed	42.000s	5.105ms	49	50	98.00
V2S	fault_inject	aes_fi	8.000s	490.743us	49	50	98.00
		aes_control_fi	55.000s	32.847ms	273	300	91.00
		aes_cipher_fi	45.000s	10.002ms	317	350	90.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	117.541us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	117.541us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	117.541us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	117.541us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	450.583us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	1.223ms	5	5	100.00
		aes_tl_intg_err	5.000s	1.333ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	1.333ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	6.000s	97.434us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	117.541us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	6.000s	131.266us	50	50	100.00
		aes_stress	40.000s	4.335ms	50	50	100.00
		aes_alert_reset	6.000s	97.434us	50	50	100.00
		aes_core_fi	6.267m	10.008ms	62	70	88.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	117.541us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_stress	40.000s	4.335ms	50	50	100.00
		aes_readability	4.000s	124.418us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	40.000s	4.335ms	50	50	100.00
		aes_sideload	6.000s	123.088us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	124.418us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	124.418us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	124.418us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	124.418us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	124.418us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	40.000s	4.335ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	40.000s	4.335ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	8.000s	490.743us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	8.000s	490.743us	49	50	98.00
		aes_control_fi	55.000s	32.847ms	273	300	91.00
		aes_cipher_fi	45.000s	10.002ms	317	350	90.57
		aes_ctr_fi	5.000s	60.937us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	8.000s	490.743us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	8.000s	490.743us	49	50	98.00
		aes_control_fi	55.000s	32.847ms	273	300	91.00
		aes_cipher_fi	45.000s	10.002ms	317	350	90.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	45.000s	10.002ms	317	350	90.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	8.000s	490.743us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	8.000s	490.743us	49	50	98.00
		aes_control_fi	55.000s	32.847ms	273	300	91.00
		aes_ctr_fi	5.000s	60.937us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	8.000s	490.743us	49	50	98.00
		aes_control_fi	55.000s	32.847ms	273	300	91.00
		aes_cipher_fi	45.000s	10.002ms	317	350	90.57
		aes_ctr_fi	5.000s	60.937us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	6.000s	97.434us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	8.000s	490.743us	49	50	98.00
		aes_control_fi	55.000s	32.847ms	273	300	91.00
		aes_cipher_fi	45.000s	10.002ms	317	350	90.57
		aes_ctr_fi	5.000s	60.937us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	8.000s	490.743us	49	50	98.00
		aes_control_fi	55.000s	32.847ms	273	300	91.00
		aes_cipher_fi	45.000s	10.002ms	317	350	90.57
		aes_ctr_fi	5.000s	60.937us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	8.000s	490.743us	49	50	98.00
		aes_control_fi	55.000s	32.847ms	273	300	91.00
		aes_ctr_fi	5.000s	60.937us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	8.000s	490.743us	49	50	98.00
		aes_control_fi	55.000s	32.847ms	273	300	91.00
		aes_cipher_fi	45.000s	10.002ms	317	350	90.57
V2S		TOTAL			915	985	92.89
V3		TOTAL			0	0	--
		TOTAL			1512	1582	95.58

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	12	12	12	100.00
V2S	11	11	6	54.55

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.17	97.61	94.60	98.83	93.65	97.72	91.11	98.07	92.49

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 32 failures:
- Test aes_control_fi has 12 failures.
  - 25.aes_control_fi.1613312518
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/25.aes_control_fi/latest/run.log
```
  Job ID: smart:28f4546b-5304-4bae-b418-fe45d3dacb1d
```
  - 32.aes_control_fi.4091342730
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/32.aes_control_fi/latest/run.log
```
  Job ID: smart:a4b54541-1243-4edf-9037-c2ba88580f46
```
  - ... and 10 more failures.
- Test aes_cipher_fi has 20 failures.
  - 38.aes_cipher_fi.1406403461
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/38.aes_cipher_fi/latest/run.log
```
  Job ID: smart:0505ea45-61b6-4f20-8325-e63ddf4af657
```
  - 66.aes_cipher_fi.1837795838
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/66.aes_cipher_fi/latest/run.log
```
  Job ID: smart:66028db5-e511-45bb-969b-bdde7b192684
```
  - ... and 18 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 14 failures:

Test aes_control_fi has 14 failures.

15.aes_control_fi.897282907
Line 274, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/15.aes_control_fi/latest/run.log

  UVM_FATAL @ 10013277221 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013277221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

30.aes_control_fi.3244281898
Line 278, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/30.aes_control_fi/latest/run.log

  UVM_FATAL @ 10011559552 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011559552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 12 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 13 failures:

Test aes_cipher_fi has 13 failures.

32.aes_cipher_fi.3037469196
Line 271, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/32.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10010214632 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010214632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

76.aes_cipher_fi.4018956584
Line 272, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/76.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10012410848 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012410848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 11 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 6 failures:

Test aes_core_fi has 6 failures.

5.aes_core_fi.551016384
Line 282, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_core_fi/latest/run.log

  UVM_FATAL @ 10003495172 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003495172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.aes_core_fi.1613931788
Line 271, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_core_fi/latest/run.log

  UVM_FATAL @ 10002189109 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002189109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 2 failures:

Test aes_core_fi has 2 failures.

0.aes_core_fi.2815813330
Line 266, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_core_fi/latest/run.log

  UVM_FATAL @ 10033598147 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xb9045084) == 0x0
  UVM_INFO @ 10033598147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

30.aes_core_fi.3084640411
Line 271, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/30.aes_core_fi/latest/run.log

  UVM_FATAL @ 10007561931 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x6b81a584) == 0x0
  UVM_INFO @ 10007561931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,978): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

11.aes_fi.3628293446
Line 1998, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/11.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,978): (time 32639373 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 32599373 PS)
  UVM_ERROR @  32639373 ps: (aes_core.sv:978) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  32639373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_scoreboard.sv:621) scoreboard [scoreboard] # * has 1 failures:

Test aes_reseed has 1 failures.

19.aes_reseed.169218741
Line 1279, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_reseed/latest/run.log

  UVM_FATAL @  11088977 ps: (aes_scoreboard.sv:621) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]  # 0
            TEST FAILED MESSAGES DID NOT MATCH
  
                 0 d7      e0      22      0
                 1 00      50      af      0

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_control_fi has 1 failures.
  - 49.aes_control_fi.429460573
    Line 272, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/49.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```