AES/UNMASKED Simulation Results

Wednesday December 27 2023 20:02:24 UTC

GitHub Revision: `0c759b93ab`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 85416116840666724748485424200434981761468351851988553961117902923833034512693

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	56.618us	1	1	100.00
V1	smoke	aes_smoke	18.000s	76.235us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	11.000s	61.816us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.583m	10.007ms	19	20	95.00
V1	csr_bit_bash	aes_csr_bit_bash	22.000s	2.938ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	56.000s	10.123ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	18.000s	103.691us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.583m	10.007ms	19	20	95.00
		aes_csr_aliasing	56.000s	10.123ms	4	5	80.00
V1		TOTAL			104	106	98.11
V2	algorithm	aes_smoke	18.000s	76.235us	50	50	100.00
		aes_config_error	14.000s	78.926us	50	50	100.00
		aes_stress	9.000s	87.833us	50	50	100.00
V2	key_length	aes_smoke	18.000s	76.235us	50	50	100.00
		aes_config_error	14.000s	78.926us	50	50	100.00
		aes_stress	9.000s	87.833us	50	50	100.00
V2	back2back	aes_stress	9.000s	87.833us	50	50	100.00
		aes_b2b	15.000s	577.456us	50	50	100.00
V2	backpressure	aes_stress	9.000s	87.833us	50	50	100.00
V2	multi_message	aes_smoke	18.000s	76.235us	50	50	100.00
		aes_config_error	14.000s	78.926us	50	50	100.00
		aes_stress	9.000s	87.833us	50	50	100.00
		aes_alert_reset	12.000s	129.029us	47	50	94.00
V2	failure_test	aes_man_cfg_err	8.000s	84.571us	50	50	100.00
		aes_config_error	14.000s	78.926us	50	50	100.00
		aes_alert_reset	12.000s	129.029us	47	50	94.00
V2	trigger_clear_test	aes_clear	9.000s	388.839us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	432.367us	1	1	100.00
V2	reset_recovery	aes_alert_reset	12.000s	129.029us	47	50	94.00
V2	stress	aes_stress	9.000s	87.833us	50	50	100.00
V2	sideload	aes_stress	9.000s	87.833us	50	50	100.00
		aes_sideload	8.000s	56.554us	50	50	100.00
V2	deinitialization	aes_deinit	10.000s	66.543us	50	50	100.00
V2	stress_all	aes_stress_all	36.000s	619.757us	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	60.028us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	16.000s	324.748us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	16.000s	324.748us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	11.000s	61.816us	5	5	100.00
		aes_csr_rw	3.583m	10.007ms	19	20	95.00
		aes_csr_aliasing	56.000s	10.123ms	4	5	80.00
		aes_same_csr_outstanding	3.567m	10.013ms	19	20	95.00
V2	tl_d_partial_access	aes_csr_hw_reset	11.000s	61.816us	5	5	100.00
		aes_csr_rw	3.583m	10.007ms	19	20	95.00
		aes_csr_aliasing	56.000s	10.123ms	4	5	80.00
		aes_same_csr_outstanding	3.567m	10.013ms	19	20	95.00
V2		TOTAL			497	501	99.20
V2S	reseeding	aes_reseed	11.000s	81.195us	50	50	100.00
V2S	fault_inject	aes_fi	10.000s	408.799us	50	50	100.00
		aes_control_fi	47.000s	63.031ms	270	300	90.00
		aes_cipher_fi	43.000s	10.005ms	328	350	93.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	16.000s	159.502us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	16.000s	159.502us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	16.000s	159.502us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	16.000s	159.502us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	14.000s	64.585us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	10.000s	2.573ms	5	5	100.00
		aes_tl_intg_err	29.000s	206.538us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	29.000s	206.538us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	12.000s	129.029us	47	50	94.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	16.000s	159.502us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	18.000s	76.235us	50	50	100.00
		aes_stress	9.000s	87.833us	50	50	100.00
		aes_alert_reset	12.000s	129.029us	47	50	94.00
		aes_core_fi	14.000s	130.364us	70	70	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	16.000s	159.502us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	12.000s	50.657us	50	50	100.00
		aes_stress	9.000s	87.833us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	87.833us	50	50	100.00
		aes_sideload	8.000s	56.554us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	12.000s	50.657us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	12.000s	50.657us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	12.000s	50.657us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	12.000s	50.657us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	12.000s	50.657us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	87.833us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	87.833us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	10.000s	408.799us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	10.000s	408.799us	50	50	100.00
		aes_control_fi	47.000s	63.031ms	270	300	90.00
		aes_cipher_fi	43.000s	10.005ms	328	350	93.71
		aes_ctr_fi	8.000s	105.746us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	10.000s	408.799us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	10.000s	408.799us	50	50	100.00
		aes_control_fi	47.000s	63.031ms	270	300	90.00
		aes_cipher_fi	43.000s	10.005ms	328	350	93.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	43.000s	10.005ms	328	350	93.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	10.000s	408.799us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	10.000s	408.799us	50	50	100.00
		aes_control_fi	47.000s	63.031ms	270	300	90.00
		aes_ctr_fi	8.000s	105.746us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	10.000s	408.799us	50	50	100.00
		aes_control_fi	47.000s	63.031ms	270	300	90.00
		aes_cipher_fi	43.000s	10.005ms	328	350	93.71
		aes_ctr_fi	8.000s	105.746us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	12.000s	129.029us	47	50	94.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	10.000s	408.799us	50	50	100.00
		aes_control_fi	47.000s	63.031ms	270	300	90.00
		aes_cipher_fi	43.000s	10.005ms	328	350	93.71
		aes_ctr_fi	8.000s	105.746us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	10.000s	408.799us	50	50	100.00
		aes_control_fi	47.000s	63.031ms	270	300	90.00
		aes_cipher_fi	43.000s	10.005ms	328	350	93.71
		aes_ctr_fi	8.000s	105.746us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	10.000s	408.799us	50	50	100.00
		aes_control_fi	47.000s	63.031ms	270	300	90.00
		aes_ctr_fi	8.000s	105.746us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	10.000s	408.799us	50	50	100.00
		aes_control_fi	47.000s	63.031ms	270	300	90.00
		aes_cipher_fi	43.000s	10.005ms	328	350	93.71
V2S		TOTAL			933	985	94.72
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	53.000s	2.155ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1534	1602	95.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	5	71.43
V2	13	13	11	84.62
V2S	11	11	9	81.82
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.32	97.61	94.60	98.87	93.73	97.72	93.33	98.66	97.97

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 29 failures:
- Test aes_cipher_fi has 15 failures.
  - 14.aes_cipher_fi.17550569349502497061675399470115818357982727860352183040015851324704481579036
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_cipher_fi/latest/run.log
```
  Job ID: smart:79870189-3816-4fe2-85f5-317971db74aa
```
  - 44.aes_cipher_fi.1982417287428977703617731782979068552168658344893416984248150809876026034553
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/44.aes_cipher_fi/latest/run.log
```
  Job ID: smart:84cb5408-319e-482e-b6b5-48e3caeab4f1
```
  - ... and 13 more failures.
- Test aes_control_fi has 14 failures.
  - 15.aes_control_fi.81428649221971228048877728004352488080213315419763947370190753270371169417379
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/15.aes_control_fi/latest/run.log
```
  Job ID: smart:a56bcc28-5cb3-4596-8b4f-6db06dd6cd2a
```
  - 18.aes_control_fi.18030025108155326598935985131800873244452052166135521760265798669654985630837
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/18.aes_control_fi/latest/run.log
```
  Job ID: smart:d31ad38f-a1a0-45f6-bcbb-a8330352c41d
```
  - ... and 12 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 16 failures:
- Test aes_control_fi has 16 failures.
  - 82.aes_control_fi.55860316239202326126616249327167870479775442773700061048842013895831668689919
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/82.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007518125 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007518125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 89.aes_control_fi.65525480061663471200464317214287733029750785226657272179839394239171060069302
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/89.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10013878113 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013878113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 14 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 1.aes_cipher_fi.5084296350670448594342758808429835354959699824839515153624098530685035412368
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009135743 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009135743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.aes_cipher_fi.4039534142124643753590684700400199525192908533574475837951658767565884425859
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/18.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10013825505 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013825505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

1.aes_stress_all_with_rand_reset.19635211719228276485592247988739734435840166080936421465205218161883670044510
Line 1029, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4051567657 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4051567657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.86966167570944780384831469383094873655122819993630968701013927969071535510650
Line 429, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6851146695 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 6851146695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (cip_base_vseq.sv:520) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 2 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 0.aes_stress_all_with_rand_reset.88316701009285150712517131501356376287016447826050956071894189900614127352046
    Line 348, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 135398670 ps: (cip_base_vseq.sv:520) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @ 135398670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test aes_alert_reset has 1 failures.
  - 12.aes_alert_reset.99970220355313249831740753279295901437576606339314775835377770614639657783044
    Line 4572, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/12.aes_alert_reset/latest/run.log
```
  UVM_ERROR @  19818413 ps: (cip_base_vseq.sv:520) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @  19818413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,978): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 2 failures:

Test aes_alert_reset has 2 failures.

2.aes_alert_reset.92383794465249132848354791646679582728013751947670431973136346111824988694332
Line 1872, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,978): (time 8480354 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 8470150 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,984): (time 8480354 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 8470150 PS)
  UVM_ERROR @   8480354 ps: (aes_core.sv:978) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

22.aes_alert_reset.25782582206844138658132838558649027727869286617062709253194453313919673043457
Line 1662, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/22.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,978): (time 32124747 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 32053318 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,984): (time 32124747 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 32053318 PS)
  UVM_ERROR @  32124747 ps: (aes_core.sv:978) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 2 failures:
- Test aes_csr_aliasing has 1 failures.
  - 4.aes_csr_aliasing.9775043184835012931257551120620273377616317998857689672302205649930249237593
    Line 283, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_csr_aliasing/latest/run.log
```
  UVM_FATAL @ 10123219320 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x3b03384) == 0x0
  UVM_INFO @ 10123219320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test aes_csr_rw has 1 failures.
  - 19.aes_csr_rw.44919936617277174619316785758063757781164916649457938989802331728658507383465
    Line 284, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_csr_rw/latest/run.log
```
  UVM_FATAL @ 10006799136 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x83c81e84) == 0x0
  UVM_INFO @ 10006799136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_same_csr_outstanding has 1 failures.
  - 1.aes_same_csr_outstanding.43920396446573244366027259100252171717880045631648054078930874557176748696690
    Line 283, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @ 10013335105 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x3a7e384) == 0x0
  UVM_INFO @ 10013335105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 2.aes_stress_all_with_rand_reset.40282299609598573500862269492289709452599185835149514306444225082603907953529
    Line 288, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  36588131 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  36588131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.92507748243983732377794331161756925429750349325358382925256186000918016227562
    Line 1474, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 821816927 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 821816927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```