AON_TIMER Simulation Results

Thursday May 18 2023 07:04:58 UTC

GitHub Revision: ac0bef2ce

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2907120974

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke aon_timer_smoke 1.380s 550.418us 50 50 100.00
V1 csr_hw_reset aon_timer_csr_hw_reset 2.410s 1.206ms 5 5 100.00
V1 csr_rw aon_timer_csr_rw 1.290s 522.477us 20 20 100.00
V1 csr_bit_bash aon_timer_csr_bit_bash 6.460s 5.894ms 5 5 100.00
V1 csr_aliasing aon_timer_csr_aliasing 1.240s 368.881us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aon_timer_csr_mem_rw_with_rand_reset 1.570s 476.166us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr aon_timer_csr_rw 1.290s 522.477us 20 20 100.00
aon_timer_csr_aliasing 1.240s 368.881us 5 5 100.00
V1 mem_walk aon_timer_mem_walk 1.250s 500.904us 5 5 100.00
V1 mem_partial_access aon_timer_mem_partial_access 1.100s 482.748us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 prescaler aon_timer_prescaler 1.588m 60.650ms 50 50 100.00
V2 jump aon_timer_jump 1.460s 577.079us 50 50 100.00
V2 stress_all aon_timer_stress_all 9.145m 346.733ms 50 50 100.00
V2 intr_test aon_timer_intr_test 1.260s 507.576us 50 50 100.00
V2 tl_d_oob_addr_access aon_timer_tl_errors 2.900s 904.365us 20 20 100.00
V2 tl_d_illegal_access aon_timer_tl_errors 2.900s 904.365us 20 20 100.00
V2 tl_d_outstanding_access aon_timer_csr_hw_reset 2.410s 1.206ms 5 5 100.00
aon_timer_csr_rw 1.290s 522.477us 20 20 100.00
aon_timer_csr_aliasing 1.240s 368.881us 5 5 100.00
aon_timer_same_csr_outstanding 5.620s 2.409ms 20 20 100.00
V2 tl_d_partial_access aon_timer_csr_hw_reset 2.410s 1.206ms 5 5 100.00
aon_timer_csr_rw 1.290s 522.477us 20 20 100.00
aon_timer_csr_aliasing 1.240s 368.881us 5 5 100.00
aon_timer_same_csr_outstanding 5.620s 2.409ms 20 20 100.00
V2 TOTAL 240 240 100.00
V2S tl_intg_err aon_timer_sec_cm 14.740s 8.359ms 5 5 100.00
aon_timer_tl_intg_err 14.150s 8.301ms 20 20 100.00
V2S sec_cm_bus_integrity aon_timer_tl_intg_err 14.150s 8.301ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset aon_timer_stress_all_with_rand_reset 17.757m 201.632ms 49 50 98.00
V3 TOTAL 49 50 98.00
TOTAL 429 430 99.77

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.46 99.82 94.68 100.00 -- 99.35 100.00 96.90

Failure Buckets

Past Results