AON_TIMER Simulation Results

Sunday December 24 2023 20:02:26 UTC

GitHub Revision: 671f2b57e2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 96716765175854174075659971574604807242747408006700796360560480210023744343645

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.430s	544.295us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.330s	1.284ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.360s	391.977us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	10.890s	6.263ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.510s	477.559us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.520s	519.280us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.360s	391.977us	20	20	100.00
		aon_timer_csr_aliasing	1.510s	477.559us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.170s	399.632us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.230s	464.238us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.194m	49.538ms	50	50	100.00
V2	jump	aon_timer_jump	1.390s	543.779us	50	50	100.00
V2	stress_all	aon_timer_stress_all	9.847m	380.241ms	50	50	100.00
V2	intr_test	aon_timer_intr_test	1.390s	325.999us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.830s	504.045us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.830s	504.045us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.330s	1.284ms	5	5	100.00
		aon_timer_csr_rw	1.360s	391.977us	20	20	100.00
		aon_timer_csr_aliasing	1.510s	477.559us	5	5	100.00
		aon_timer_same_csr_outstanding	4.310s	2.648ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.330s	1.284ms	5	5	100.00
		aon_timer_csr_rw	1.360s	391.977us	20	20	100.00
		aon_timer_csr_aliasing	1.510s	477.559us	5	5	100.00
		aon_timer_same_csr_outstanding	4.310s	2.648ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	tl_intg_err	aon_timer_sec_cm	12.100s	7.427ms	5	5	100.00
		aon_timer_tl_intg_err	15.390s	8.770ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	15.390s	8.770ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	17.102m	96.766ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			429	430	99.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.56	99.82	95.32	100.00	--	99.35	100.00	96.90

Failure Buckets

• UVM_ERROR (aon_timer_scoreboard.sv:360) [scoreboard] Check failed wdog_rst_req_exp === cfg.aon_intr_vif.sample_pin(.idx(0)) (* [*] vs * [*]) has 1 failures:
  • Test aon_timer_stress_all_with_rand_reset has 1 failures.

    • 34.aon_timer_stress_all_with_rand_reset.60690918948207139304069814335877990653073632337564937078927478514077686822248
      Line 1967, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/34.aon_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 96766259086 ps: (aon_timer_scoreboard.sv:360) [uvm_test_top.env.scoreboard] Check failed wdog_rst_req_exp === cfg.aon_intr_vif.sample_pin(.idx(0)) (0x1 [1] vs 0x0 [0])
        UVM_INFO @ 96766259086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2023.12.21_00.01.50
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• 2023.11.23_01.56.56
• 2023.11.02_03.22.35
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• 2023.10.26_02.47.33
• 2023.10.23_18.05.48