Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	820728413	8077894	0	0
wdog_bark_thold_rd_A	820728413	128620	0	0
wdog_bite_thold_rd_A	820728413	112183	0	0
wdog_ctrl_rd_A	820728413	112106	0	0
wdog_regwen_rd_A	820728413	129512	0	0
wkup_ctrl_rd_A	820728413	112377	0	0
wkup_thold_rd_A	820728413	129165	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	820728413	8077894	0	0
T2	23799	0	0	0
T3	264769	1	0	0
T5	31395	1	0	0
T6	765458	0	0	0
T8	0	3	0	0
T10	0	4	0	0
T13	0	126528	0	0
T14	7313	0	0	0
T15	39582	0	0	0
T16	7005	0	0	0
T17	49447	4	0	0
T18	10634	0	0	0
T19	0	65077	0	0
T27	0	287567	0	0
T43	30668	0	0	0
T50	0	439	0	0
T52	0	573	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	820728413	128620	0	0
T1	49793	24	0	0
T2	23799	0	0	0
T3	264769	50	0	0
T5	31395	5	0	0
T6	765458	263	0	0
T7	0	226	0	0
T9	0	26	0	0
T10	0	37	0	0
T14	7313	0	0	0
T15	39582	0	0	0
T16	7005	0	0	0
T17	49447	10	0	0
T18	10634	0	0	0
T47	0	3	0	0
T50	0	52	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	820728413	112183	0	0
T1	49793	22	0	0
T2	23799	0	0	0
T3	264769	84	0	0
T5	31395	6	0	0
T6	765458	232	0	0
T7	0	204	0	0
T9	0	1	0	0
T10	0	21	0	0
T14	7313	0	0	0
T15	39582	0	0	0
T16	7005	0	0	0
T17	49447	1	0	0
T18	10634	0	0	0
T47	0	4	0	0
T50	0	19	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	820728413	112106	0	0
T1	49793	44	0	0
T2	23799	0	0	0
T3	264769	93	0	0
T5	31395	0	0	0
T6	765458	241	0	0
T7	0	191	0	0
T9	0	3	0	0
T10	0	44	0	0
T13	0	4684	0	0
T14	7313	0	0	0
T15	39582	0	0	0
T16	7005	0	0	0
T17	49447	7	0	0
T18	10634	0	0	0
T47	0	6	0	0
T50	0	51	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	820728413	129512	0	0
T1	49793	92	0	0
T2	23799	0	0	0
T3	264769	76	0	0
T5	31395	5	0	0
T6	765458	453	0	0
T7	0	218	0	0
T9	0	22	0	0
T10	0	34	0	0
T14	7313	0	0	0
T15	39582	0	0	0
T16	7005	0	0	0
T17	49447	2	0	0
T18	10634	0	0	0
T47	0	3	0	0
T50	0	59	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	820728413	112377	0	0
T1	49793	38	0	0
T2	23799	0	0	0
T3	264769	77	0	0
T5	31395	2	0	0
T6	765458	213	0	0
T7	0	204	0	0
T9	0	9	0	0
T10	0	65	0	0
T13	0	4632	0	0
T14	7313	0	0	0
T15	39582	0	0	0
T16	7005	0	0	0
T17	49447	7	0	0
T18	10634	0	0	0
T50	0	25	0	0

wkup_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	820728413	129165	0	0
T1	49793	17	0	0
T2	23799	0	0	0
T3	264769	47	0	0
T5	31395	3	0	0
T6	765458	244	0	0
T7	0	228	0	0
T9	0	23	0	0
T10	0	20	0	0
T14	7313	0	0	0
T15	39582	0	0	0
T16	7005	0	0	0
T17	49447	9	0	0
T18	10634	0	0	0
T47	0	3	0	0
T50	0	64	0	0