Unified Coverage Report :: Module :: aon_timer_reg_top

Module : aon_timer_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.51	100.00	98.05			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.51	100.00	98.05			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.51	100.00	98.05			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.96	99.80	95.71	100.00		99.30	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_intr_state_wdog_timer_bark	100.00	100.00	100.00			100.00
u_intr_state_wkup_timer_expired	100.00	100.00	100.00			100.00
u_intr_test_wdog_timer_bark	100.00	100.00
u_intr_test_wkup_timer_expired	100.00	100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.69	97.14	97.62			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_wdog_bark_thold	100.00	100.00	100.00			100.00
u_wdog_bark_thold_cdc	99.17	100.00	96.67			100.00	100.00
u_wdog_bite_thold	100.00	100.00	100.00			100.00
u_wdog_bite_thold_cdc	99.17	100.00	96.67			100.00	100.00
u_wdog_count	100.00	100.00	100.00			100.00
u_wdog_count_cdc	97.11	100.00	90.14			98.31	100.00
u_wdog_ctrl_cdc	99.17	100.00	96.67			100.00	100.00
u_wdog_ctrl_enable	100.00	100.00	100.00			100.00
u_wdog_ctrl_pause_in_sleep	100.00	100.00	100.00			100.00
u_wdog_regwen	100.00	100.00	100.00			100.00
u_wkup_cause	100.00	100.00	100.00			100.00
u_wkup_cause_cdc	97.18	100.00	90.41			98.31	100.00
u_wkup_count	100.00	100.00	100.00			100.00
u_wkup_count_cdc	97.11	100.00	90.14			98.31	100.00
u_wkup_ctrl_cdc	99.17	100.00	96.67			100.00	100.00
u_wkup_ctrl_enable	100.00	100.00	100.00			100.00
u_wkup_ctrl_prescaler	100.00	100.00	100.00			100.00
u_wkup_thold	100.00	100.00	100.00			100.00
u_wkup_thold_cdc	99.17	100.00	96.67			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : aon_timer_reg_top

	Line No.	Total	Covered	Percent
TOTAL		127	127	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
ALWAYS	174	3	3	100.00
CONT_ASSIGN	203	1	1	100.00
ALWAYS	213	2	2	100.00
CONT_ASSIGN	241	1	1	100.00
ALWAYS	254	4	4	100.00
CONT_ASSIGN	284	1	1	100.00
ALWAYS	296	3	3	100.00
CONT_ASSIGN	325	1	1	100.00
ALWAYS	336	2	2	100.00
CONT_ASSIGN	364	1	1	100.00
ALWAYS	375	2	2	100.00
CONT_ASSIGN	403	1	1	100.00
ALWAYS	416	4	4	100.00
CONT_ASSIGN	446	1	1	100.00
ALWAYS	459	4	4	100.00
CONT_ASSIGN	489	1	1	100.00
CONT_ASSIGN	496	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	599	1	1	100.00
CONT_ASSIGN	658	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	748	1	1	100.00
CONT_ASSIGN	778	1	1	100.00
CONT_ASSIGN	865	1	1	100.00
CONT_ASSIGN	880	1	1	100.00
CONT_ASSIGN	896	1	1	100.00
CONT_ASSIGN	901	1	1	100.00
ALWAYS	932	13	13	100.00
CONT_ASSIGN	947	1	1	100.00
ALWAYS	951	1	1	100.00
CONT_ASSIGN	967	1	1	100.00
CONT_ASSIGN	969	1	1	100.00
CONT_ASSIGN	970	1	1	100.00
CONT_ASSIGN	973	1	1	100.00
CONT_ASSIGN	975	1	1	100.00
CONT_ASSIGN	977	1	1	100.00
CONT_ASSIGN	979	1	1	100.00
CONT_ASSIGN	980	1	1	100.00
CONT_ASSIGN	983	1	1	100.00
CONT_ASSIGN	985	1	1	100.00
CONT_ASSIGN	987	1	1	100.00
CONT_ASSIGN	989	1	1	100.00
CONT_ASSIGN	991	1	1	100.00
CONT_ASSIGN	993	1	1	100.00
CONT_ASSIGN	994	1	1	100.00
CONT_ASSIGN	996	1	1	100.00
CONT_ASSIGN	998	1	1	100.00
CONT_ASSIGN	999	1	1	100.00
ALWAYS	1004	13	13	100.00
ALWAYS	1021	16	16	100.00
CONT_ASSIGN	1077	1	1	100.00
ALWAYS	1079	10	10	100.00
CONT_ASSIGN	1118	1	1	100.00
CONT_ASSIGN	1119	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer_reg_top.sv' or '../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
79	1	1
91	1	1
92	1	1
120	1	1
121	1	1
174	1	1
175	1	1
176	1	1
203	1	1
213	1	1
214	1	1
241	1	1
254	1	1
255	1	1
256	1	1
257	1	1
284	1	1
296	1	1
297	1	1
298	1	1
325	1	1
336	1	1
337	1	1
364	1	1
375	1	1
376	1	1
403	1	1
416	1	1
417	1	1
418	1	1
419	1	1
446	1	1
459	1	1
460	1	1
461	1	1
462	1	1
489	1	1
496	1	1
510	1	1
599	1	1
658	1	1
717	1	1
748	1	1
778	1	1
865	1	1
880	1	1
896	1	1
901	1	1
932	1	1
933	1	1
934	1	1
935	1	1
936	1	1
937	1	1
938	1	1
939	1	1
940	1	1
941	1	1
942	1	1
943	1	1
944	1	1
947	1	1
951	1	1
967	1	1
969	1	1
970	1	1
973	1	1
975	1	1
977	1	1
979	1	1
980	1	1
983	1	1
985	1	1
987	1	1
989	1	1
991	1	1
993	1	1
994	1	1
996	1	1
998	1	1
999	1	1
1004	1	1
1005	1	1
1006	1	1
1007	1	1
1008	1	1
1009	1	1
1010	1	1
1011	1	1
1012	1	1
1013	1	1
1014	1	1
1015	1	1
1016	1	1
1021	1	1
1022	1	1
1024	1	1
1028	1	1
1031	1	1
1034	1	1
1037	1	1
1041	1	1
1044	1	1
1047	1	1
1050	1	1
1053	1	1
1054	1	1
1058	1	1
1059	1	1
1063	1	1
1077	1	1
1079	1	1
1080	1	1
1082	1	1
1085	1	1
1088	1	1
1091	1	1
1094	1	1
1097	1	1
1100	1	1
1103	1	1
1118	1	1
1119	1	1

---

Cond Coverage for Module : aon_timer_reg_top

	Total	Covered	Percent
Conditions	154	151	98.05
Logical	154	151	98.05
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T3,T50,T52
1	1	Covered	T1,T5,T6

 LINE       72
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T29,T30,T31
1	0	Covered	T3,T8,T10

 LINE       79
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T5,T6
0	0	1	Covered	T29,T30,T31
0	1	0	Covered	T3,T8,T10
1	0	0	Covered	T3,T8,T10

 LINE       121
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T5,T6
0	0	1	Covered	T3,T8,T10
0	1	0	Covered	T50,T52,T13
1	0	0	Covered	T50,T52,T13

 LINE       658
 EXPRESSION (aon_wdog_ctrl_we & aon_wdog_ctrl_regwen)
             --------1-------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T6,T3
1	1	Covered	T1,T6,T2

 LINE       717
 EXPRESSION (aon_wdog_bark_thold_we & aon_wdog_bark_thold_regwen)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T2

 LINE       748
 EXPRESSION (aon_wdog_bite_thold_we & aon_wdog_bite_thold_regwen)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T2

 LINE       933
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_ALERT_TEST_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       934
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WKUP_CTRL_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       935
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WKUP_THOLD_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       936
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WKUP_COUNT_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T14

 LINE       937
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WDOG_REGWEN_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       938
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WDOG_CTRL_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       939
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WDOG_BARK_THOLD_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       940
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WDOG_BITE_THOLD_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       941
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WDOG_COUNT_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T15

 LINE       942
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_INTR_STATE_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       943
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_INTR_TEST_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       944
 EXPRESSION (reg_addr == aon_timer_reg_pkg::AON_TIMER_WKUP_CAUSE_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T15

 LINE       947
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       947
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6

 LINE       951
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T3,T8,T50

 LINE       951
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1111 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1111 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1 & (~reg_be))))))

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	Status	Tests
0	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T5,T6
0	0	0	0	0	0	0	0	0	0	0	1	Covered	T3,T43,T45
0	0	0	0	0	0	0	0	0	0	1	0	Covered	T6,T14,T15
0	0	0	0	0	0	0	0	0	1	0	0	Covered	T1,T6,T14
0	0	0	0	0	0	0	0	1	0	0	0	Covered	T15,T17,T3
0	0	0	0	0	0	0	1	0	0	0	0	Covered	T5,T6,T2
0	0	0	0	0	0	1	0	0	0	0	0	Covered	T5,T6,T18
0	0	0	0	0	1	0	0	0	0	0	0	Covered	T6,T14,T2
0	0	0	0	1	0	0	0	0	0	0	0	Covered	T5,T6,T14
0	0	0	1	0	0	0	0	0	0	0	0	Covered	T14,T15,T17
0	0	1	0	0	0	0	0	0	0	0	0	Covered	T5,T6,T14
0	1	0	0	0	0	0	0	0	0	0	0	Covered	T6,T14,T2
1	0	0	0	0	0	0	0	0	0	0	0	Covered	T6,T14,T15

 LINE       951
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T6,T14,T15

 LINE       951
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T6,T14,T2

 LINE       951
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T5,T6,T14

 LINE       951
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T15
1	1	Covered	T14,T15,T17

 LINE       951
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T5,T6,T14

 LINE       951
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T6,T14,T2

 LINE       951
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T5,T6,T18

 LINE       951
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T5,T6,T2

 LINE       951
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T2
1	1	Covered	T15,T17,T3

 LINE       951
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T14
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T6,T14

 LINE       951
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T6,T14,T15

 LINE       951
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T15
1	1	Covered	T3,T43,T45

 LINE       967
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T6
1	0	1	Covered	T1,T5,T6
1	1	0	Covered	T50,T52,T13
1	1	1	Covered	T1,T5,T6

 LINE       970
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T6
1	0	1	Covered	T1,T5,T6
1	1	0	Covered	T52,T13,T19
1	1	1	Covered	T1,T5,T6

 LINE       973
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T6
1	0	1	Covered	T1,T5,T6
1	1	0	Covered	T3,T50,T52
1	1	1	Covered	T1,T5,T6

 LINE       975
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T6
1	0	1	Covered	T1,T5,T14
1	1	0	Covered	T3,T8,T50
1	1	1	Covered	T1,T5,T2

 LINE       977
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T6
1	0	1	Covered	T1,T5,T6
1	1	0	Covered	T3,T13,T19
1	1	1	Covered	T1,T5,T6

 LINE       980
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T6
1	0	1	Covered	T1,T5,T6
1	1	0	Covered	T50,T52,T13
1	1	1	Covered	T1,T5,T6

 LINE       983
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T6
1	0	1	Covered	T1,T5,T6
1	1	0	Covered	T50,T13,T19
1	1	1	Covered	T1,T5,T6

 LINE       985
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T6
1	0	1	Covered	T1,T5,T6
1	1	0	Covered	T50,T13,T19
1	1	1	Covered	T1,T5,T6

 LINE       987
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T6
1	0	1	Covered	T1,T5,T15
1	1	0	Covered	T13,T19,T27
1	1	1	Covered	T1,T5,T2

 LINE       989
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T6
1	0	1	Covered	T1,T5,T6
1	1	0	Covered	T3,T13,T19
1	1	1	Covered	T1,T5,T6

 LINE       994
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T6
1	0	1	Covered	T1,T5,T6
1	1	0	Covered	T3,T50,T13
1	1	1	Covered	T1,T5,T6

 LINE       999
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T6
1	0	1	Covered	T1,T5,T15
1	1	0	Covered	T50,T52,T13
1	1	1	Covered	T1,T5,T2

 LINE       1077
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T6

---

Branch Coverage for Module : aon_timer_reg_top

	Line No.	Total	Covered	Percent
Branches		27	27	100.00
TERNARY	947	2	2	100.00
IF	70	3	3	100.00
CASE	1022	13	13	100.00
CASE	1080	9	9	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer_reg_top.sv' or '../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	947	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T5,T6
0	1	Covered	T3,T8,T10
0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	1022	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T5,T6
addr_hit[1]	Covered	T1,T5,T6
addr_hit[2]	Covered	T1,T5,T6
addr_hit[3]	Covered	T1,T5,T6
addr_hit[4]	Covered	T1,T5,T6
addr_hit[5]	Covered	T1,T5,T6
addr_hit[6]	Covered	T1,T5,T6
addr_hit[7]	Covered	T1,T5,T6
addr_hit[8]	Covered	T1,T5,T6
addr_hit[9]	Covered	T1,T5,T6
addr_hit[10]	Covered	T1,T5,T6
addr_hit[11]	Covered	T1,T5,T6
default	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	1080	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[1]	Covered	T1,T5,T6
addr_hit[2]	Covered	T1,T5,T6
addr_hit[3]	Covered	T1,T5,T6
addr_hit[5]	Covered	T1,T5,T6
addr_hit[6]	Covered	T1,T5,T6
addr_hit[7]	Covered	T1,T5,T6
addr_hit[8]	Covered	T1,T5,T6
addr_hit[11]	Covered	T1,T5,T6
default	Covered	T1,T5,T6

---

Assert Coverage for Module : aon_timer_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	820728413	444710	0	0
reAfterRv	820728413	444709	0	0
rePulse	820728413	108761	0	0
wePulse	820728413	335948	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	820728413	444710	0	0
T1	49793	209	0	0
T2	23799	46	0	0
T3	264769	409	0	0
T5	31395	25	0	0
T6	765458	1556	0	0
T14	7313	10	0	0
T15	39582	12	0	0
T16	7005	20	0	0
T17	49447	46	0	0
T18	10634	20	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	820728413	444709	0	0
T1	49793	209	0	0
T2	23799	46	0	0
T3	264769	409	0	0
T5	31395	25	0	0
T6	765458	1556	0	0
T14	7313	10	0	0
T15	39582	12	0	0
T16	7005	20	0	0
T17	49447	46	0	0
T18	10634	20	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	820728413	108761	0	0
T1	49793	81	0	0
T2	23799	21	0	0
T3	264769	172	0	0
T5	31395	13	0	0
T6	765458	749	0	0
T14	7313	5	0	0
T15	39582	6	0	0
T16	7005	10	0	0
T17	49447	23	0	0
T18	10634	10	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	820728413	335948	0	0
T1	49793	128	0	0
T2	23799	25	0	0
T3	264769	237	0	0
T5	31395	12	0	0
T6	765458	807	0	0
T14	7313	5	0	0
T15	39582	6	0	0
T16	7005	10	0	0
T17	49447	23	0	0
T18	10634	10	0	0