CLKMGR Simulation Results

Thursday May 18 2023 07:04:58 UTC

GitHub Revision: ac0bef2ce

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2907120974

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.530s	303.140us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.870s	51.275us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.230s	219.360us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	4.950s	596.113us	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	1.820s	74.768us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.300s	270.261us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.230s	219.360us	20	20	100.00
		clkmgr_csr_aliasing	1.820s	74.768us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.110s	142.668us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.690s	285.181us	50	50	100.00
V2	extclk	clkmgr_extclk	1.660s	309.210us	50	50	100.00
V2	clk_status	clkmgr_clk_status	0.990s	154.622us	50	50	100.00
V2	jitter	clkmgr_smoke	1.530s	303.140us	50	50	100.00
V2	frequency	clkmgr_frequency	18.300s	2.359ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	18.150s	2.423ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	18.300s	2.359ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.249m	11.126ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.950s	153.413us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.550s	280.726us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	5.330s	643.864us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	5.330s	643.864us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.870s	51.275us	5	5	100.00
		clkmgr_csr_rw	1.230s	219.360us	20	20	100.00
		clkmgr_csr_aliasing	1.820s	74.768us	5	5	100.00
		clkmgr_same_csr_outstanding	1.570s	190.660us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.870s	51.275us	5	5	100.00
		clkmgr_csr_rw	1.230s	219.360us	20	20	100.00
		clkmgr_csr_aliasing	1.820s	74.768us	5	5	100.00
		clkmgr_same_csr_outstanding	1.570s	190.660us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	3.740s	617.463us	5	5	100.00
		clkmgr_tl_intg_err	2.950s	244.113us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	3.390s	727.137us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	3.390s	727.137us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	3.390s	727.137us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	3.390s	727.137us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	6.090s	1.442ms	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	2.950s	244.113us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	18.300s	2.359ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	18.150s	2.423ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	3.390s	727.137us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.450s	181.823us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.250s	190.312us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.170s	153.389us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.610s	301.620us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.470s	218.942us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.230s	219.360us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	3.740s	617.463us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.230s	219.360us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.230s	219.360us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	3.740s	617.463us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	25.880m	437.678ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			959	960	99.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.60	99.12	95.40	100.00	100.00	98.71	96.97	93.01

Failure Buckets

• Offending '((clk_enabled || $changed(clk_enabled)) || (!gated_clk))' has 1 failures:
  • Test clkmgr_stress_all_with_rand_reset has 1 failures.

    • 35.clkmgr_stress_all_with_rand_reset.181234799
      Line 967, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/35.clkmgr_stress_all_with_rand_reset/latest/run.log

            Offending '((clk_enabled || $changed(clk_enabled)) || (!gated_clk))'
        UVM_ERROR @ 20603066411 ps: (clkmgr_gated_clock_sva_if.sv:23) [ASSERT FAILED] GateClose_A
        UVM_INFO @ 20603066411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2023.05.17_17.46.49
• 2023.05.16_19.12.30
• 2023.05.15_18.30.36
• 2023.05.14_17.56.25
• 2023.05.13_18.39.16
• 2023.05.12_18.30.14
• 2023.05.12_11.14.02