CLKMGR Simulation Results

Sunday December 31 2023 20:02:18 UTC

GitHub Revision: a9c19f09f3

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 36521940887861431083267591129785326983863798057293121812910170439117479843669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.630s	291.295us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	1.120s	176.846us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	0.950s	96.469us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	8.550s	900.886us	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	1.830s	139.155us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	1.840s	62.531us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	0.950s	96.469us	20	20	100.00
		clkmgr_csr_aliasing	1.830s	139.155us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.160s	147.568us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.560s	281.174us	50	50	100.00
V2	extclk	clkmgr_extclk	1.580s	279.452us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.030s	166.258us	50	50	100.00
V2	jitter	clkmgr_smoke	1.630s	291.295us	50	50	100.00
V2	frequency	clkmgr_frequency	17.680s	2.355ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	18.050s	2.419ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	17.680s	2.355ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	59.540s	8.699ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.930s	134.531us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.280s	197.424us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	4.180s	531.203us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	4.180s	531.203us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	1.120s	176.846us	5	5	100.00
		clkmgr_csr_rw	0.950s	96.469us	20	20	100.00
		clkmgr_csr_aliasing	1.830s	139.155us	5	5	100.00
		clkmgr_same_csr_outstanding	1.550s	102.604us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	1.120s	176.846us	5	5	100.00
		clkmgr_csr_rw	0.950s	96.469us	20	20	100.00
		clkmgr_csr_aliasing	1.830s	139.155us	5	5	100.00
		clkmgr_same_csr_outstanding	1.550s	102.604us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	3.660s	617.106us	5	5	100.00
		clkmgr_tl_intg_err	3.500s	462.549us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	2.840s	567.559us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	2.840s	567.559us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	2.840s	567.559us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	2.840s	567.559us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	3.680s	536.315us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	3.500s	462.549us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	17.680s	2.355ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	18.050s	2.419ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	2.840s	567.559us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.500s	279.406us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.810s	364.118us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.080s	119.308us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.380s	210.906us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.600s	288.347us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	0.950s	96.469us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	3.660s	617.106us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	0.950s	96.469us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	0.950s	96.469us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	3.660s	617.106us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	7.200s	1.246ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	38.523m	656.319ms	49	50	98.00
V3		TOTAL			99	100	99.00
		TOTAL			1009	1010	99.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.54	99.15	95.84	100.00	100.00	98.81	97.01	98.97

Failure Buckets

• Offending '(((!clk_enabled) || $changed(clk_enabled)) || gated_clk)' has 1 failures:
  • Test clkmgr_stress_all_with_rand_reset has 1 failures.

    • 41.clkmgr_stress_all_with_rand_reset.61703798660788507189625100066025321262516939951316219921624328763342203196496
      Line 841, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/41.clkmgr_stress_all_with_rand_reset/latest/run.log

            Offending '(((!clk_enabled) || $changed(clk_enabled)) || gated_clk)'
        UVM_ERROR @ 9559754094 ps: (clkmgr_gated_clock_sva_if.sv:20) [ASSERT FAILED] GateOpen_A
        UVM_INFO @ 9559754094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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