Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	586077	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3233166

1

T4

17

T5

31

T6

25

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	942137	1			T4	19		T5	44		T6	19
values[0x0]	1324242	1			T4	24		T5	20		T6	24
values[0x1]	1552864	1			T4	15		T5	13		T6	15

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	328785	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3490458

1

T4

26

T5

36

T6

29

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16379	1			T1	1		T19	1		T2	547
valid_sources[0x01]	14364	1			T1	14		T19	1		T2	502
valid_sources[0x02]	14222	1			T1	12		T2	553		T8	4
valid_sources[0x03]	16602	1			T28	1		T1	9		T19	1
valid_sources[0x04]	14272	1			T4	2		T1	13		T2	610
valid_sources[0x05]	16260	1			T22	1		T1	22		T19	1
valid_sources[0x06]	13806	1			T1	17		T2	540		T20	1
valid_sources[0x07]	16037	1			T1	5		T19	1		T2	534
valid_sources[0x08]	16267	1			T1	20		T2	542		T8	9
valid_sources[0x09]	15352	1			T22	3		T1	7		T2	537
valid_sources[0x0a]	15100	1			T1	13		T2	535		T8	8
valid_sources[0x0b]	15194	1			T1	5		T2	576		T8	3
valid_sources[0x0c]	14525	1			T4	1		T22	1		T28	1
valid_sources[0x0d]	14062	1			T22	1		T1	10		T19	2
valid_sources[0x0e]	15072	1			T1	17		T2	564		T8	8
valid_sources[0x0f]	13824	1			T28	1		T19	2		T2	575
valid_sources[0x10]	16696	1			T22	5		T1	9		T19	1
valid_sources[0x11]	15235	1			T4	2		T2	571		T20	1
valid_sources[0x12]	15654	1			T1	10		T2	610		T8	11
valid_sources[0x13]	15868	1			T4	2		T1	1		T2	549
valid_sources[0x14]	13957	1			T27	2		T1	1		T2	516
valid_sources[0x15]	14800	1			T2	507		T8	10		T9	166
valid_sources[0x16]	14191	1			T1	9		T2	555		T8	12
valid_sources[0x17]	13333	1			T1	18		T2	508		T47	3
valid_sources[0x18]	14855	1			T1	5		T2	569		T8	3
valid_sources[0x19]	14753	1			T1	19		T2	603		T8	9
valid_sources[0x1a]	14715	1			T1	4		T2	556		T47	1
valid_sources[0x1b]	15247	1			T1	11		T2	530		T20	1
valid_sources[0x1c]	15265	1			T28	1		T1	3		T2	549
valid_sources[0x1d]	15042	1			T1	10		T2	508		T20	1
valid_sources[0x1e]	15168	1			T28	1		T1	22		T2	500
valid_sources[0x1f]	15786	1			T19	1		T2	551		T8	7
valid_sources[0x20]	15161	1			T1	12		T19	1		T2	492
valid_sources[0x21]	14583	1			T27	2		T1	4		T19	1
valid_sources[0x22]	16242	1			T1	9		T19	1		T2	583
valid_sources[0x23]	14246	1			T25	4		T1	7		T2	481
valid_sources[0x24]	16045	1			T27	2		T1	4		T19	1
valid_sources[0x25]	13946	1			T1	6		T2	523		T8	9
valid_sources[0x26]	15568	1			T4	2		T1	2		T2	522
valid_sources[0x27]	14284	1			T1	11		T2	502		T8	5
valid_sources[0x28]	14930	1			T4	1		T1	15		T2	560
valid_sources[0x29]	15187	1			T1	11		T2	579		T8	3
valid_sources[0x2a]	15618	1			T4	2		T28	2		T1	10
valid_sources[0x2b]	13545	1			T1	6		T2	527		T20	1
valid_sources[0x2c]	15665	1			T5	1		T1	6		T2	511
valid_sources[0x2d]	16064	1			T4	1		T19	1		T2	562
valid_sources[0x2e]	14075	1			T28	2		T1	2		T2	584
valid_sources[0x2f]	14916	1			T4	2		T1	1		T16	19
valid_sources[0x30]	17647	1			T1	8		T19	2		T2	529
valid_sources[0x31]	14122	1			T1	11		T19	2		T2	560
valid_sources[0x32]	13778	1			T4	2		T5	1		T1	5
valid_sources[0x33]	15511	1			T4	1		T22	7		T1	13
valid_sources[0x34]	15429	1			T1	5		T2	616		T8	5
valid_sources[0x35]	17299	1			T1	6		T2	558		T20	1
valid_sources[0x36]	14731	1			T1	3		T19	2		T2	547
valid_sources[0x37]	13349	1			T1	4		T19	2		T2	562
valid_sources[0x38]	14954	1			T5	15		T28	1		T1	2
valid_sources[0x39]	15329	1			T1	6		T19	1		T2	533
valid_sources[0x3a]	14362	1			T4	1		T1	22		T2	511
valid_sources[0x3b]	15067	1			T1	13		T2	569		T47	1
valid_sources[0x3c]	16223	1			T4	2		T22	3		T1	2
valid_sources[0x3d]	15450	1			T1	3		T2	598		T8	12
valid_sources[0x3e]	14028	1			T4	1		T1	9		T2	570
valid_sources[0x3f]	14746	1			T4	1		T27	7		T1	20
valid_sources[0x40]	14153	1			T1	6		T19	1		T2	534
valid_sources[0x41]	14927	1			T1	15		T19	1		T2	594
valid_sources[0x42]	15698	1			T1	9		T2	512		T8	7
valid_sources[0x43]	14090	1			T4	1		T22	3		T1	36
valid_sources[0x44]	13432	1			T5	3		T1	1		T19	2
valid_sources[0x45]	14681	1			T22	2		T1	24		T2	504
valid_sources[0x46]	15108	1			T4	1		T22	2		T1	1
valid_sources[0x47]	13918	1			T1	5		T2	491		T20	1
valid_sources[0x48]	14672	1			T1	5		T2	570		T8	11
valid_sources[0x49]	14814	1			T5	2		T1	13		T19	1
valid_sources[0x4a]	15125	1			T5	10		T27	8		T1	7
valid_sources[0x4b]	15500	1			T28	1		T1	6		T18	7
valid_sources[0x4c]	14922	1			T4	1		T1	1		T2	518
valid_sources[0x4d]	15449	1			T5	14		T1	1		T2	528
valid_sources[0x4e]	14329	1			T1	20		T19	1		T2	589
valid_sources[0x4f]	15032	1			T1	7		T19	1		T2	542
valid_sources[0x50]	14777	1			T22	1		T1	34		T2	478
valid_sources[0x51]	16103	1			T22	1		T28	2		T1	17
valid_sources[0x52]	13007	1			T22	2		T28	2		T1	6
valid_sources[0x53]	15609	1			T4	2		T1	17		T2	531
valid_sources[0x54]	13873	1			T1	2		T2	546		T8	10
valid_sources[0x55]	14764	1			T1	11		T2	526		T47	2
valid_sources[0x56]	15668	1			T1	13		T19	1		T2	542
valid_sources[0x57]	16708	1			T1	3		T19	1		T2	577
valid_sources[0x58]	13933	1			T1	2		T19	1		T2	550
valid_sources[0x59]	15591	1			T22	1		T1	16		T19	1
valid_sources[0x5a]	14345	1			T22	1		T25	6		T27	2
valid_sources[0x5b]	14201	1			T22	2		T1	4		T2	565
valid_sources[0x5c]	14865	1			T22	1		T1	8		T2	579
valid_sources[0x5d]	13955	1			T4	1		T28	1		T1	4
valid_sources[0x5e]	14804	1			T4	2		T1	3		T2	517
valid_sources[0x5f]	15335	1			T1	15		T19	2		T2	573
valid_sources[0x60]	15631	1			T2	535		T8	9		T9	4
valid_sources[0x61]	14981	1			T1	17		T2	573		T8	5
valid_sources[0x62]	15607	1			T1	14		T2	584		T47	3
valid_sources[0x63]	15108	1			T1	11		T2	572		T8	12
valid_sources[0x64]	14255	1			T28	1		T1	17		T2	533
valid_sources[0x65]	14285	1			T4	1		T22	2		T1	5
valid_sources[0x66]	13623	1			T22	1		T1	14		T2	536
valid_sources[0x67]	14528	1			T4	2		T19	1		T2	502
valid_sources[0x68]	14563	1			T1	4		T2	566		T8	9
valid_sources[0x69]	16327	1			T4	1		T22	2		T2	514
valid_sources[0x6a]	13774	1			T1	9		T2	522		T8	7
valid_sources[0x6b]	17328	1			T27	5		T1	1		T2	533
valid_sources[0x6c]	15606	1			T28	1		T1	3		T2	535
valid_sources[0x6d]	15280	1			T1	6		T2	561		T20	1
valid_sources[0x6e]	16845	1			T1	6		T19	1		T2	574
valid_sources[0x6f]	14506	1			T1	3		T2	520		T20	1
valid_sources[0x70]	15012	1			T1	2		T19	2		T2	546
valid_sources[0x71]	16060	1			T1	5		T2	526		T8	9
valid_sources[0x72]	16209	1			T2	609		T8	11		T9	1
valid_sources[0x73]	14691	1			T1	13		T2	559		T8	3
valid_sources[0x74]	13824	1			T1	14		T2	570		T20	1
valid_sources[0x75]	14362	1			T1	8		T19	1		T2	557
valid_sources[0x76]	15767	1			T4	1		T28	1		T1	18
valid_sources[0x77]	15169	1			T4	1		T1	9		T2	467
valid_sources[0x78]	13156	1			T1	8		T2	622		T20	1
valid_sources[0x79]	12813	1			T1	9		T2	536		T8	6
valid_sources[0x7a]	15026	1			T1	2		T2	487		T47	4
valid_sources[0x7b]	14460	1			T1	3		T2	508		T8	11
valid_sources[0x7c]	16064	1			T5	5		T28	1		T1	9
valid_sources[0x7d]	15013	1			T1	8		T2	560		T47	2
valid_sources[0x7e]	14196	1			T1	12		T2	543		T20	2
valid_sources[0x7f]	16183	1			T1	14		T19	1		T2	574
valid_sources[0x80]	13837	1			T1	22		T19	1		T2	521

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

817602

1

T4

7

T5

23

T6

11

values[0x0]

all_enables

biggest_size

1231268

1

T4

7

T5

7

T6

9

values[0x1]

all_enables

biggest_size

1184296

1

T4

3

T5

1

T6

5