Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	780386295	74398	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	780386295	74398	0	0
T1	1254980	139	0	0
T2	1968205	2320	0	0
T3	192095	244	0	0
T8	0	102	0	0
T9	0	748	0	0
T10	0	1167	0	0
T11	0	208	0	0
T12	0	56	0	0
T13	0	336	0	0
T14	0	233	0	0
T15	5570	0	0	0
T16	6040	0	0	0
T17	7195	0	0	0
T18	8000	0	0	0
T19	74950	0	0	0
T20	9380	0	0	0
T21	4595	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	156077259	11037	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156077259	11037	0	0
T1	250996	23	0	0
T2	393641	344	0	0
T3	38419	39	0	0
T8	0	17	0	0
T9	0	108	0	0
T10	0	187	0	0
T11	0	32	0	0
T12	0	9	0	0
T13	0	54	0	0
T14	0	31	0	0
T15	1114	0	0	0
T16	1208	0	0	0
T17	1439	0	0	0
T18	1600	0	0	0
T19	14990	0	0	0
T20	1876	0	0	0
T21	919	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	156077259	14919	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156077259	14919	0	0
T1	250996	28	0	0
T2	393641	471	0	0
T3	38419	51	0	0
T8	0	21	0	0
T9	0	151	0	0
T10	0	237	0	0
T11	0	40	0	0
T12	0	11	0	0
T13	0	65	0	0
T14	0	46	0	0
T15	1114	0	0	0
T16	1208	0	0	0
T17	1439	0	0	0
T18	1600	0	0	0
T19	14990	0	0	0
T20	1876	0	0	0
T21	919	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	156077259	22701	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156077259	22701	0	0
T1	250996	38	0	0
T2	393641	759	0	0
T3	38419	67	0	0
T8	0	28	0	0
T9	0	231	0	0
T10	0	323	0	0
T11	0	65	0	0
T12	0	16	0	0
T13	0	96	0	0
T14	0	76	0	0
T15	1114	0	0	0
T16	1208	0	0	0
T17	1439	0	0	0
T18	1600	0	0	0
T19	14990	0	0	0
T20	1876	0	0	0
T21	919	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	156077259	10785	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156077259	10785	0	0
T1	250996	22	0	0
T2	393641	290	0	0
T3	38419	37	0	0
T8	0	16	0	0
T9	0	107	0	0
T10	0	183	0	0
T11	0	30	0	0
T12	0	9	0	0
T13	0	52	0	0
T14	0	32	0	0
T15	1114	0	0	0
T16	1208	0	0	0
T17	1439	0	0	0
T18	1600	0	0	0
T19	14990	0	0	0
T20	1876	0	0	0
T21	919	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	156077259	14956	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156077259	14956	0	0
T1	250996	28	0	0
T2	393641	456	0	0
T3	38419	50	0	0
T8	0	20	0	0
T9	0	151	0	0
T10	0	237	0	0
T11	0	41	0	0
T12	0	11	0	0
T13	0	69	0	0
T14	0	48	0	0
T15	1114	0	0	0
T16	1208	0	0	0
T17	1439	0	0	0
T18	1600	0	0	0
T19	14990	0	0	0
T20	1876	0	0	0
T21	919	0	0	0