Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T19,T2

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	156077259	153235127	0	0
AllClkBypReqTrue_A	156077259	145664	0	0
IoClkBypReqFalse_A	156077259	153149257	0	2415
IoClkBypReqTrue_A	156077259	226596	0	0
LcClkBypAckFalse_A	156077259	153246822	0	0
LcClkBypAckTrue_A	156077259	133969	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156077259	153235127	0	0
T4	1783	1680	0	0
T5	2547	2483	0	0
T6	2475	2070	0	0
T22	1399	1277	0	0
T23	1471	1407	0	0
T24	1494	1356	0	0
T25	1626	1479	0	0
T26	1506	1227	0	0
T27	2232	1806	0	0
T28	2034	1737	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156077259	145664	0	0
T2	0	764	0	0
T4	1783	86	0	0
T5	2547	0	0	0
T6	2475	264	0	0
T15	0	98	0	0
T16	0	17	0	0
T21	0	25	0	0
T22	1399	0	0	0
T23	1471	0	0	0
T24	1494	126	0	0
T25	1626	77	0	0
T26	1506	0	0	0
T27	2232	281	0	0
T28	2034	137	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156077259	153149257	0	2415
T4	1783	1723	0	3
T5	2547	2481	0	3
T6	2475	1951	0	3
T22	1399	1275	0	3
T23	1471	1405	0	3
T24	1494	1107	0	3
T25	1626	1339	0	3
T26	1506	1225	0	3
T27	2232	1702	0	3
T28	2034	1600	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156077259	226596	0	0
T4	1783	41	0	0
T5	2547	0	0	0
T6	2475	381	0	0
T15	0	142	0	0
T16	0	81	0	0
T17	0	218	0	0
T18	0	42	0	0
T22	1399	0	0	0
T23	1471	0	0	0
T24	1494	373	0	0
T25	1626	215	0	0
T26	1506	0	0	0
T27	2232	383	0	0
T28	2034	272	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156077259	153246822	0	0
T4	1783	1757	0	0
T5	2547	2483	0	0
T6	2475	2128	0	0
T22	1399	1277	0	0
T23	1471	1407	0	0
T24	1494	1371	0	0
T25	1626	1463	0	0
T26	1506	1227	0	0
T27	2232	1735	0	0
T28	2034	1743	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156077259	133969	0	0
T4	1783	9	0	0
T5	2547	0	0	0
T6	2475	206	0	0
T15	0	111	0	0
T16	0	42	0	0
T17	0	58	0	0
T18	0	1	0	0
T22	1399	0	0	0
T23	1471	0	0	0
T24	1494	111	0	0
T25	1626	93	0	0
T26	1506	0	0	0
T27	2232	352	0	0
T28	2034	131	0	0