Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2103237516	15520	0	0
TransStop_A	2103237516	7886	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2103237516	15520	0	0
T1	3871956	110	0	0
T2	0	194	0	0
T5	20384	24	0	0
T6	9904	0	0	0
T8	0	30	0	0
T9	0	205	0	0
T20	0	4	0	0
T22	5832	4	0	0
T23	11776	4	0	0
T24	85396	0	0	0
T25	13268	0	0	0
T26	6148	0	0	0
T27	14888	0	0	0
T28	9356	0	0	0
T103	0	4	0	0
T104	0	34	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2103237516	7886	0	0
T1	3871956	56	0	0
T2	0	104	0	0
T5	20384	7	0	0
T6	9904	0	0	0
T8	0	24	0	0
T9	0	123	0	0
T20	0	4	0	0
T22	5832	4	0	0
T23	11776	4	0	0
T24	85396	0	0	0
T25	13268	0	0	0
T26	6148	0	0	0
T27	14888	0	0	0
T28	9356	0	0	0
T103	0	4	0	0
T104	0	20	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	525809379	3875	0	0
TransStop_A	525809379	1955	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525809379	3875	0	0
T1	967989	31	0	0
T2	0	52	0	0
T5	5096	6	0	0
T6	2476	0	0	0
T8	0	8	0	0
T9	0	55	0	0
T20	0	1	0	0
T22	1458	1	0	0
T23	2944	1	0	0
T24	21349	0	0	0
T25	3317	0	0	0
T26	1537	0	0	0
T27	3722	0	0	0
T28	2339	0	0	0
T103	0	1	0	0
T104	0	10	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525809379	1955	0	0
T1	967989	17	0	0
T2	0	27	0	0
T5	5096	3	0	0
T6	2476	0	0	0
T8	0	7	0	0
T9	0	32	0	0
T20	0	1	0	0
T22	1458	1	0	0
T23	2944	1	0	0
T24	21349	0	0	0
T25	3317	0	0	0
T26	1537	0	0	0
T27	3722	0	0	0
T28	2339	0	0	0
T103	0	1	0	0
T104	0	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	525809379	3853	0	0
TransStop_A	525809379	1962	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525809379	3853	0	0
T1	967989	29	0	0
T2	0	54	0	0
T5	5096	8	0	0
T6	2476	0	0	0
T8	0	8	0	0
T9	0	50	0	0
T20	0	1	0	0
T22	1458	1	0	0
T23	2944	1	0	0
T24	21349	0	0	0
T25	3317	0	0	0
T26	1537	0	0	0
T27	3722	0	0	0
T28	2339	0	0	0
T103	0	1	0	0
T104	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525809379	1962	0	0
T1	967989	14	0	0
T2	0	26	0	0
T5	5096	2	0	0
T6	2476	0	0	0
T8	0	7	0	0
T9	0	30	0	0
T20	0	1	0	0
T22	1458	1	0	0
T23	2944	1	0	0
T24	21349	0	0	0
T25	3317	0	0	0
T26	1537	0	0	0
T27	3722	0	0	0
T28	2339	0	0	0
T103	0	1	0	0
T104	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	525809379	3907	0	0
TransStop_A	525809379	1991	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525809379	3907	0	0
T1	967989	25	0	0
T2	0	38	0	0
T5	5096	6	0	0
T6	2476	0	0	0
T8	0	8	0	0
T9	0	50	0	0
T20	0	1	0	0
T22	1458	1	0	0
T23	2944	1	0	0
T24	21349	0	0	0
T25	3317	0	0	0
T26	1537	0	0	0
T27	3722	0	0	0
T28	2339	0	0	0
T103	0	1	0	0
T104	0	8	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525809379	1991	0	0
T1	967989	13	0	0
T2	0	23	0	0
T5	5096	1	0	0
T6	2476	0	0	0
T8	0	5	0	0
T9	0	31	0	0
T20	0	1	0	0
T22	1458	1	0	0
T23	2944	1	0	0
T24	21349	0	0	0
T25	3317	0	0	0
T26	1537	0	0	0
T27	3722	0	0	0
T28	2339	0	0	0
T103	0	1	0	0
T104	0	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	525809379	3885	0	0
TransStop_A	525809379	1978	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525809379	3885	0	0
T1	967989	25	0	0
T2	0	50	0	0
T5	5096	4	0	0
T6	2476	0	0	0
T8	0	6	0	0
T9	0	50	0	0
T20	0	1	0	0
T22	1458	1	0	0
T23	2944	1	0	0
T24	21349	0	0	0
T25	3317	0	0	0
T26	1537	0	0	0
T27	3722	0	0	0
T28	2339	0	0	0
T103	0	1	0	0
T104	0	9	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525809379	1978	0	0
T1	967989	12	0	0
T2	0	28	0	0
T5	5096	1	0	0
T6	2476	0	0	0
T8	0	5	0	0
T9	0	30	0	0
T20	0	1	0	0
T22	1458	1	0	0
T23	2944	1	0	0
T24	21349	0	0	0
T25	3317	0	0	0
T26	1537	0	0	0
T27	3722	0	0	0
T28	2339	0	0	0
T103	0	1	0	0
T104	0	4	0	0