Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	156077259	16144241	0	61

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156077259	16144241	0	61
T1	250996	11106	0	0
T2	393641	270808	0	0
T3	38419	17093	0	1
T8	0	8188	0	0
T9	0	63572	0	0
T10	0	77684	0	0
T11	0	18846	0	1
T12	0	344980	0	0
T13	0	24375	0	1
T14	0	0	0	1
T15	1114	0	0	0
T16	1208	0	0	0
T17	1439	0	0	0
T18	1600	0	0	0
T19	14990	0	0	0
T20	1876	0	0	0
T21	919	0	0	0
T29	0	0	0	1
T33	0	1096	0	1
T36	0	0	0	1
T69	0	0	0	1
T105	0	0	0	1
T106	0	0	0	1