Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	157019298	4671187	0	0
clk_enables_rd_A	157019298	60014	0	0
clk_hints_rd_A	157019298	52845	0	0
extclk_ctrl_rd_A	157019298	65578	0	0
extclk_ctrl_regwen_rd_A	157019298	50747	0	0
jitter_enable_rd_A	157019298	71764	0	0
jitter_regwen_rd_A	157019298	56397	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157019298	4671187	0	0
T2	393641	190844	0	0
T3	38419	0	0	0
T8	208427	0	0	0
T9	0	71208	0	0
T10	0	178038	0	0
T12	0	59871	0	0
T20	1876	0	0	0
T21	919	0	0	0
T30	59474	0	0	0
T38	1695	0	0	0
T40	0	67434	0	0
T47	3027	0	0	0
T48	2270	0	0	0
T49	1193	0	0	0
T64	0	122401	0	0
T65	0	57844	0	0
T66	0	31041	0	0
T67	0	48189	0	0
T68	0	74399	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157019298	60014	0	0
T3	38419	0	0	0
T8	208427	0	0	0
T9	197741	0	0	0
T12	0	2442	0	0
T20	1876	4	0	0
T21	919	0	0	0
T30	59474	0	0	0
T38	1695	0	0	0
T40	0	2582	0	0
T47	3027	0	0	0
T48	2270	0	0	0
T49	1193	0	0	0
T65	0	2429	0	0
T122	0	4	0	0
T123	0	5	0	0
T124	0	1	0	0
T125	0	1107	0	0
T126	0	15	0	0
T127	0	1130	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157019298	52845	0	0
T3	38419	0	0	0
T8	208427	0	0	0
T9	197741	0	0	0
T12	0	2125	0	0
T20	1876	5	0	0
T21	919	0	0	0
T30	59474	0	0	0
T38	1695	0	0	0
T40	0	2332	0	0
T47	3027	0	0	0
T48	2270	0	0	0
T49	1193	0	0	0
T65	0	2140	0	0
T122	0	7	0	0
T123	0	6	0	0
T125	0	860	0	0
T126	0	20	0	0
T127	0	1141	0	0
T128	0	3190	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157019298	65578	0	0
T1	250996	0	0	0
T12	0	2733	0	0
T15	1114	0	0	0
T16	1208	0	0	0
T17	1439	0	0	0
T18	1600	1	0	0
T24	1494	45	0	0
T25	1626	0	0	0
T26	1506	0	0	0
T27	2232	0	0	0
T28	2034	0	0	0
T90	0	38	0	0
T129	0	83	0	0
T130	0	25	0	0
T131	0	53	0	0
T132	0	24	0	0
T133	0	2	0	0
T134	0	55	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157019298	50747	0	0
T11	118354	0	0	0
T12	0	2132	0	0
T40	0	2365	0	0
T65	0	1944	0	0
T90	41281	8	0	0
T125	0	805	0	0
T127	0	923	0	0
T128	0	3406	0	0
T130	1332	0	0	0
T135	0	62	0	0
T136	0	59	0	0
T137	0	2487	0	0
T138	1161	0	0	0
T139	1643	0	0	0
T140	1038	0	0	0
T141	1459	0	0	0
T142	959	0	0	0
T143	8170	0	0	0
T144	3638	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157019298	71764	0	0
T3	38419	0	0	0
T8	208427	0	0	0
T9	197741	0	0	0
T12	0	2707	0	0
T20	1876	109	0	0
T21	919	0	0	0
T30	59474	0	0	0
T38	1695	0	0	0
T40	0	3799	0	0
T47	3027	0	0	0
T48	2270	0	0	0
T49	1193	0	0	0
T65	0	3336	0	0
T122	0	106	0	0
T123	0	206	0	0
T124	0	100	0	0
T125	0	1335	0	0
T126	0	460	0	0
T145	0	78	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157019298	56397	0	0
T12	204361	2321	0	0
T13	68283	0	0	0
T14	187994	0	0	0
T40	0	2585	0	0
T65	0	2279	0	0
T125	0	1071	0	0
T127	0	1238	0	0
T128	0	3743	0	0
T131	2215	0	0	0
T137	0	2633	0	0
T146	0	1228	0	0
T147	0	2790	0	0
T148	0	2474	0	0
T149	869	0	0	0
T150	1410	0	0	0
T151	109574	0	0	0
T152	1487	0	0	0
T153	1842	0	0	0
T154	1301	0	0	0